src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  52 {
  53         if (!ws->get_chip_name)
  54                 return NULL;
  55         return ws->get_chip_name(ws);
  56 }
  57
  58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60         struct si_screen *sscreen = (struct si_screen *)pscreen;
  61
  62         switch (param) {
  63         /* Supported features (boolean caps). */
  64         case PIPE_CAP_ACCELERATED:
  65         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  66         case PIPE_CAP_ANISOTROPIC_FILTER:
  67         case PIPE_CAP_POINT_SPRITE:
  68         case PIPE_CAP_OCCLUSION_QUERY:
  69         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  70         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72         case PIPE_CAP_TEXTURE_SWIZZLE:
  73         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  74         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  75         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  76         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  77         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  78         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81         case PIPE_CAP_SM3:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  83         case PIPE_CAP_PRIMITIVE_RESTART:
  84         case PIPE_CAP_CONDITIONAL_RENDER:
  85         case PIPE_CAP_TEXTURE_BARRIER:
  86         case PIPE_CAP_INDEP_BLEND_ENABLE:
  87         case PIPE_CAP_INDEP_BLEND_FUNC:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  89         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  90         case PIPE_CAP_START_INSTANCE:
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  93         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  94         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  95         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  96         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97         case PIPE_CAP_TGSI_INSTANCEID:
  98         case PIPE_CAP_COMPUTE:
  99         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 100         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 101         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 102         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 103         case PIPE_CAP_CUBE_MAP_ARRAY:
 104         case PIPE_CAP_SAMPLE_SHADING:
 105         case PIPE_CAP_DRAW_INDIRECT:
 106         case PIPE_CAP_CLIP_HALFZ:
 107         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 108         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 109         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 110         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 111         case PIPE_CAP_TGSI_TEXCOORD:
 112         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 113         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 114         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 115         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 116         case PIPE_CAP_SHAREABLE_SHADERS:
 117         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 118         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 119         case PIPE_CAP_TEXTURE_QUERY_LOD:
 120         case PIPE_CAP_TEXTURE_GATHER_SM5:
 121         case PIPE_CAP_TGSI_TXQS:
 122         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 123         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 124         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 125         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 126         case PIPE_CAP_INVALIDATE_BUFFER:
 127         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 128         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 129         case PIPE_CAP_QUERY_MEMORY_INFO:
 130         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 131         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 132         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 133         case PIPE_CAP_GENERATE_MIPMAP:
 134         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 135         case PIPE_CAP_STRING_MARKER:
 136         case PIPE_CAP_CLEAR_TEXTURE:
 137         case PIPE_CAP_CULL_DISTANCE:
 138         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 139         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 140         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 141         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 142         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143         case PIPE_CAP_DOUBLES:
 144         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 145         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 146         case PIPE_CAP_BINDLESS_TEXTURE:
 147         case PIPE_CAP_QUERY_TIMESTAMP:
 148         case PIPE_CAP_QUERY_TIME_ELAPSED:
 149         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 150         case PIPE_CAP_QUERY_SO_OVERFLOW:
 151         case PIPE_CAP_MEMOBJ:
 152         case PIPE_CAP_LOAD_CONSTBUF:
 153         case PIPE_CAP_INT64:
 154         case PIPE_CAP_INT64_DIVMOD:
 155         case PIPE_CAP_TGSI_CLOCK:
 156         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 157         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 158         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 159         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 160         case PIPE_CAP_TGSI_BALLOT:
 161         case PIPE_CAP_TGSI_VOTE:
 162         case PIPE_CAP_TGSI_FS_FBFETCH:
 163                 return 1;
 164
 165         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 166                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 167
 168         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 169                 return sscreen->info.has_gpu_reset_status_query ||
 170                        sscreen->info.has_gpu_reset_counter_query;
 171
 172         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 173                 return sscreen->info.has_2d_tiling;
 174
 175         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 176                 return SI_MAP_BUFFER_ALIGNMENT;
 177
 178         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 179         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 181         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 182         case PIPE_CAP_MAX_VERTEX_STREAMS:
 183         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 185                 return 4;
 186
 187         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 188         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 189                 if (sscreen->info.has_indirect_compute_dispatch)
 190                                 return 450;
 191                 return 420;
 192
 193         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 194                 /* Optimal number for good TexSubImage performance on Polaris10. */
 195                 return 64 * 1024 * 1024;
 196
 197         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 199                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 200
 201         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 202         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 203         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 204                 return !sscreen->info.has_unaligned_shader_loads;
 205
 206         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 207                 return sscreen->info.has_sparse_vm_mappings ?
 208                                 RADEON_SPARSE_PAGE_SIZE : 0;
 209
 210         case PIPE_CAP_PACKED_UNIFORMS:
 211                 if (sscreen->debug_flags & DBG(NIR))
 212                         return 1;
 213                 return 0;
 214
 215         /* Unsupported features. */
 216         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 217         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219         case PIPE_CAP_USER_VERTEX_BUFFERS:
 220         case PIPE_CAP_FAKE_SW_MSAA:
 221         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 222         case PIPE_CAP_VERTEXID_NOBASE:
 223         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 224         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 225         case PIPE_CAP_UMA:
 226         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 227         case PIPE_CAP_POST_DEPTH_COVERAGE:
 228         case PIPE_CAP_TILE_RASTER_ORDER:
 229         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 230         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 231         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 232         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 233         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 234         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 235         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 236         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 237         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 238                 return 0;
 239
 240         case PIPE_CAP_FENCE_SIGNAL:
 241                 return sscreen->info.has_syncobj;
 242
 243         case PIPE_CAP_CONSTBUF0_FLAGS:
 244                 return SI_RESOURCE_FLAG_32BIT;
 245
 246         case PIPE_CAP_NATIVE_FENCE_FD:
 247                 return sscreen->info.has_fence_to_handle;
 248
 249         case PIPE_CAP_DRAW_PARAMETERS:
 250         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 251         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 252                 return sscreen->has_draw_indirect_multi;
 253
 254         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 255                 return 30;
 256
 257         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 258                 return sscreen->info.chip_class <= VI ?
 259                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 260
 261         /* Stream output. */
 262         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 263         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 264                 return 32*4;
 265
 266         /* Geometry shader output. */
 267         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 268                 return 1024;
 269         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 270                 return 4095;
 271         case PIPE_CAP_MAX_GS_INVOCATIONS:
 272                 /* The closed driver exposes 127, but 125 is the greatest
 273                  * number that works. */
 274                 return 125;
 275
 276         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 277                 return 2048;
 278
 279         /* Texturing. */
 280         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 281         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 282                 return 15; /* 16384 */
 283         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 284                 /* textures support 8192, but layered rendering supports 2048 */
 285                 return 12;
 286         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 287                 /* textures support 8192, but layered rendering supports 2048 */
 288                 return 2048;
 289
 290         /* Viewports and render targets. */
 291         case PIPE_CAP_MAX_VIEWPORTS:
 292                 return SI_MAX_VIEWPORTS;
 293         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 294         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 295         case PIPE_CAP_MAX_RENDER_TARGETS:
 296                 return 8;
 297         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 298                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 299
 300         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 301         case PIPE_CAP_MIN_TEXEL_OFFSET:
 302                 return -32;
 303
 304         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 305         case PIPE_CAP_MAX_TEXEL_OFFSET:
 306                 return 31;
 307
 308         case PIPE_CAP_ENDIANNESS:
 309                 return PIPE_ENDIAN_LITTLE;
 310
 311         case PIPE_CAP_VENDOR_ID:
 312                 return ATI_VENDOR_ID;
 313         case PIPE_CAP_DEVICE_ID:
 314                 return sscreen->info.pci_id;
 315         case PIPE_CAP_VIDEO_MEMORY:
 316                 return sscreen->info.vram_size >> 20;
 317         case PIPE_CAP_PCI_GROUP:
 318                 return sscreen->info.pci_domain;
 319         case PIPE_CAP_PCI_BUS:
 320                 return sscreen->info.pci_bus;
 321         case PIPE_CAP_PCI_DEVICE:
 322                 return sscreen->info.pci_dev;
 323         case PIPE_CAP_PCI_FUNCTION:
 324                 return sscreen->info.pci_func;
 325
 326         default:
 327                 return u_pipe_screen_get_param_defaults(pscreen, param);
 328         }
 329 }
 330
 331 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 332 {
 333         switch (param) {
 334         case PIPE_CAPF_MAX_LINE_WIDTH:
 335         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 336         case PIPE_CAPF_MAX_POINT_WIDTH:
 337         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 338                 /* This depends on the quant mode, though the precise interactions
 339                  * are unknown. */
 340                 return 2048;
 341         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342                 return 16.0f;
 343         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 344                 return 16.0f;
 345         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 346         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 347         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 348                 return 0.0f;
 349         }
 350         return 0.0f;
 351 }
 352
 353 static int si_get_shader_param(struct pipe_screen* pscreen,
 354                                enum pipe_shader_type shader,
 355                                enum pipe_shader_cap param)
 356 {
 357         struct si_screen *sscreen = (struct si_screen *)pscreen;
 358
 359         switch(shader)
 360         {
 361         case PIPE_SHADER_FRAGMENT:
 362         case PIPE_SHADER_VERTEX:
 363         case PIPE_SHADER_GEOMETRY:
 364         case PIPE_SHADER_TESS_CTRL:
 365         case PIPE_SHADER_TESS_EVAL:
 366                 break;
 367         case PIPE_SHADER_COMPUTE:
 368                 switch (param) {
 369                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 370                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 371
 372                         if (sscreen->info.has_indirect_compute_dispatch)
 373                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 374
 375                         return ir;
 376                 }
 377
 378                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 379                         uint64_t max_const_buffer_size;
 380                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 381                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 382                                 &max_const_buffer_size);
 383                         return MIN2(max_const_buffer_size, INT_MAX);
 384                 }
 385                 default:
 386                         /* If compute shaders don't require a special value
 387                          * for this cap, we can return the same value we
 388                          * do for other shader types. */
 389                         break;
 390                 }
 391                 break;
 392         default:
 393                 return 0;
 394         }
 395
 396         switch (param) {
 397         /* Shader limits. */
 398         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 399         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 400         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 401         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 402         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 403                 return 16384;
 404         case PIPE_SHADER_CAP_MAX_INPUTS:
 405                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 406         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 407                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 408         case PIPE_SHADER_CAP_MAX_TEMPS:
 409                 return 256; /* Max native temporaries. */
 410         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 411                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 412         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 413                 return SI_NUM_CONST_BUFFERS;
 414         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 415         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 416                 return SI_NUM_SAMPLERS;
 417         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 418                 return SI_NUM_SHADER_BUFFERS;
 419         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 420                 return SI_NUM_IMAGES;
 421         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 422                 if (sscreen->debug_flags & DBG(NIR))
 423                         return 0;
 424                 return 32;
 425         case PIPE_SHADER_CAP_PREFERRED_IR:
 426                 if (sscreen->debug_flags & DBG(NIR))
 427                         return PIPE_SHADER_IR_NIR;
 428                 return PIPE_SHADER_IR_TGSI;
 429         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 430                 return 4;
 431
 432         /* Supported boolean features. */
 433         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 434         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 435         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 436         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 437         case PIPE_SHADER_CAP_INTEGERS:
 438         case PIPE_SHADER_CAP_INT64_ATOMICS:
 439         case PIPE_SHADER_CAP_FP16:
 440         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 441         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 442         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 443         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 444         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 445         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 446                 return 1;
 447
 448         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 449                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 450                 if (shader == PIPE_SHADER_GEOMETRY)
 451                         return 0;
 452
 453                 if (shader == PIPE_SHADER_VERTEX &&
 454                     !sscreen->llvm_has_working_vgpr_indexing)
 455                         return 0;
 456
 457                 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
 458                  * This means we don't support INTERP instructions with
 459                  * indirect indexing on inputs.
 460                  */
 461                 if (shader == PIPE_SHADER_FRAGMENT &&
 462                     !sscreen->llvm_has_working_vgpr_indexing &&
 463                     HAVE_LLVM < 0x0700)
 464                         return 0;
 465
 466                 /* TCS and TES load inputs directly from LDS or offchip
 467                  * memory, so indirect indexing is always supported.
 468                  * PS has to support indirect indexing, because we can't
 469                  * lower that to TEMPs for INTERP instructions.
 470                  */
 471                 return 1;
 472
 473         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 474                 return sscreen->llvm_has_working_vgpr_indexing ||
 475                        /* TCS stores outputs directly to memory. */
 476                        shader == PIPE_SHADER_TESS_CTRL;
 477
 478         /* Unsupported boolean features. */
 479         case PIPE_SHADER_CAP_SUBROUTINES:
 480         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 481         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 482         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 483                 return 0;
 484         case PIPE_SHADER_CAP_SCALAR_ISA:
 485                 return 1;
 486         }
 487         return 0;
 488 }
 489
 490 static const struct nir_shader_compiler_options nir_options = {
 491         .lower_scmp = true,
 492         .lower_flrp32 = true,
 493         .lower_flrp64 = true,
 494         .lower_fpow = true,
 495         .lower_fsat = true,
 496         .lower_fdiv = true,
 497         .lower_sub = true,
 498         .lower_ffma = true,
 499         .lower_pack_snorm_2x16 = true,
 500         .lower_pack_snorm_4x8 = true,
 501         .lower_pack_unorm_2x16 = true,
 502         .lower_pack_unorm_4x8 = true,
 503         .lower_unpack_snorm_2x16 = true,
 504         .lower_unpack_snorm_4x8 = true,
 505         .lower_unpack_unorm_2x16 = true,
 506         .lower_unpack_unorm_4x8 = true,
 507         .lower_extract_byte = true,
 508         .lower_extract_word = true,
 509         .max_unroll_iterations = 32,
 510         .native_integers = true,
 511 };
 512
 513 static const void *
 514 si_get_compiler_options(struct pipe_screen *screen,
 515                         enum pipe_shader_ir ir,
 516                         enum pipe_shader_type shader)
 517 {
 518         assert(ir == PIPE_SHADER_IR_NIR);
 519         return &nir_options;
 520 }
 521
 522 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 523 {
 524         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 525 }
 526
 527 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 528 {
 529         struct si_screen *sscreen = (struct si_screen *)pscreen;
 530
 531         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 532 }
 533
 534 static const char* si_get_name(struct pipe_screen *pscreen)
 535 {
 536         struct si_screen *sscreen = (struct si_screen*)pscreen;
 537
 538         return sscreen->renderer_string;
 539 }
 540
 541 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 542                                         enum pipe_video_profile profile,
 543                                         enum pipe_video_entrypoint entrypoint,
 544                                         enum pipe_video_cap param)
 545 {
 546         switch (param) {
 547         case PIPE_VIDEO_CAP_SUPPORTED:
 548                 return vl_profile_supported(screen, profile, entrypoint);
 549         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 550                 return 1;
 551         case PIPE_VIDEO_CAP_MAX_WIDTH:
 552         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 553                 return vl_video_buffer_max_size(screen);
 554         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 555                 return PIPE_FORMAT_NV12;
 556         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 557                 return false;
 558         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 559                 return false;
 560         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 561                 return true;
 562         case PIPE_VIDEO_CAP_MAX_LEVEL:
 563                 return vl_level_supported(screen, profile);
 564         default:
 565                 return 0;
 566         }
 567 }
 568
 569 static int si_get_video_param(struct pipe_screen *screen,
 570                               enum pipe_video_profile profile,
 571                               enum pipe_video_entrypoint entrypoint,
 572                               enum pipe_video_cap param)
 573 {
 574         struct si_screen *sscreen = (struct si_screen *)screen;
 575         enum pipe_video_format codec = u_reduce_video_profile(profile);
 576
 577         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 578                 switch (param) {
 579                 case PIPE_VIDEO_CAP_SUPPORTED:
 580                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 581                                 (si_vce_is_fw_version_supported(sscreen) ||
 582                                 sscreen->info.family == CHIP_RAVEN)) ||
 583                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 584                                 (sscreen->info.family == CHIP_RAVEN ||
 585                                 si_radeon_uvd_enc_supported(sscreen)));
 586                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 587                         return 1;
 588                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 589                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 590                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 591                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 592                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 593                         return PIPE_FORMAT_NV12;
 594                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 595                         return false;
 596                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 597                         return false;
 598                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 599                         return true;
 600                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 601                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 602                 default:
 603                         return 0;
 604                 }
 605         }
 606
 607         switch (param) {
 608         case PIPE_VIDEO_CAP_SUPPORTED:
 609                 switch (codec) {
 610                 case PIPE_VIDEO_FORMAT_MPEG12:
 611                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 612                 case PIPE_VIDEO_FORMAT_MPEG4:
 613                         return 1;
 614                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 615                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 616                              sscreen->info.family == CHIP_POLARIS11) &&
 617                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 618                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 619                                 return false;
 620                         }
 621                         return true;
 622                 case PIPE_VIDEO_FORMAT_VC1:
 623                         return true;
 624                 case PIPE_VIDEO_FORMAT_HEVC:
 625                         /* Carrizo only supports HEVC Main */
 626                         if (sscreen->info.family >= CHIP_STONEY)
 627                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 628                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 629                         else if (sscreen->info.family >= CHIP_CARRIZO)
 630                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 631                         return false;
 632                 case PIPE_VIDEO_FORMAT_JPEG:
 633                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 634                                 return false;
 635                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 636                                 RVID_ERR("No MJPEG support for the kernel version\n");
 637                                 return false;
 638                         }
 639                         return true;
 640                 case PIPE_VIDEO_FORMAT_VP9:
 641                         if (sscreen->info.family < CHIP_RAVEN)
 642                                 return false;
 643                         return true;
 644                 default:
 645                         return false;
 646                 }
 647         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 648                 return 1;
 649         case PIPE_VIDEO_CAP_MAX_WIDTH:
 650                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 651         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 652                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 653         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 654                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 655                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 656                         return PIPE_FORMAT_P016;
 657                 else
 658                         return PIPE_FORMAT_NV12;
 659
 660         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 661         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 662                 enum pipe_video_format format = u_reduce_video_profile(profile);
 663
 664                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 665                         return false; //The firmware doesn't support interlaced HEVC.
 666                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 667                         return false;
 668                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 669                         return false;
 670                 return true;
 671         }
 672         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 673                 return true;
 674         case PIPE_VIDEO_CAP_MAX_LEVEL:
 675                 switch (profile) {
 676                 case PIPE_VIDEO_PROFILE_MPEG1:
 677                         return 0;
 678                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 679                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 680                         return 3;
 681                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 682                         return 3;
 683                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 684                         return 5;
 685                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 686                         return 1;
 687                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 688                         return 2;
 689                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 690                         return 4;
 691                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 692                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 693                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 694                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 695                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 696                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 697                         return 186;
 698                 default:
 699                         return 0;
 700                 }
 701         default:
 702                 return 0;
 703         }
 704 }
 705
 706 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 707                                           enum pipe_format format,
 708                                           enum pipe_video_profile profile,
 709                                           enum pipe_video_entrypoint entrypoint)
 710 {
 711         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 712         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 713                 return (format == PIPE_FORMAT_NV12) ||
 714                         (format == PIPE_FORMAT_P016);
 715
 716         /* we can only handle this one with UVD */
 717         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 718                 return format == PIPE_FORMAT_NV12;
 719
 720         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 721 }
 722
 723 static unsigned get_max_threads_per_block(struct si_screen *screen,
 724                                           enum pipe_shader_ir ir_type)
 725 {
 726         if (ir_type == PIPE_SHADER_IR_NATIVE)
 727                 return 256;
 728
 729         /* Only 16 waves per thread-group on gfx9. */
 730         if (screen->info.chip_class >= GFX9)
 731                 return 1024;
 732
 733         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 734          * round number.
 735          */
 736         return 2048;
 737 }
 738
 739 static int si_get_compute_param(struct pipe_screen *screen,
 740                                 enum pipe_shader_ir ir_type,
 741                                 enum pipe_compute_cap param,
 742                                 void *ret)
 743 {
 744         struct si_screen *sscreen = (struct si_screen *)screen;
 745
 746         //TODO: select these params by asic
 747         switch (param) {
 748         case PIPE_COMPUTE_CAP_IR_TARGET: {
 749                 const char *gpu, *triple;
 750
 751                 triple = "amdgcn-mesa-mesa3d";
 752                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 753                 if (ret) {
 754                         sprintf(ret, "%s-%s", gpu, triple);
 755                 }
 756                 /* +2 for dash and terminating NIL byte */
 757                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 758         }
 759         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 760                 if (ret) {
 761                         uint64_t *grid_dimension = ret;
 762                         grid_dimension[0] = 3;
 763                 }
 764                 return 1 * sizeof(uint64_t);
 765
 766         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 767                 if (ret) {
 768                         uint64_t *grid_size = ret;
 769                         grid_size[0] = 65535;
 770                         grid_size[1] = 65535;
 771                         grid_size[2] = 65535;
 772                 }
 773                 return 3 * sizeof(uint64_t) ;
 774
 775         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 776                 if (ret) {
 777                         uint64_t *block_size = ret;
 778                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 779                         block_size[0] = threads_per_block;
 780                         block_size[1] = threads_per_block;
 781                         block_size[2] = threads_per_block;
 782                 }
 783                 return 3 * sizeof(uint64_t);
 784
 785         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 786                 if (ret) {
 787                         uint64_t *max_threads_per_block = ret;
 788                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 789                 }
 790                 return sizeof(uint64_t);
 791         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 792                 if (ret) {
 793                         uint32_t *address_bits = ret;
 794                         address_bits[0] = 64;
 795                 }
 796                 return 1 * sizeof(uint32_t);
 797
 798         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 799                 if (ret) {
 800                         uint64_t *max_global_size = ret;
 801                         uint64_t max_mem_alloc_size;
 802
 803                         si_get_compute_param(screen, ir_type,
 804                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 805                                 &max_mem_alloc_size);
 806
 807                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 808                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 809                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 810                          * make sure we never report more than
 811                          * 4 * MAX_MEM_ALLOC_SIZE.
 812                          */
 813                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 814                                                 MAX2(sscreen->info.gart_size,
 815                                                      sscreen->info.vram_size));
 816                 }
 817                 return sizeof(uint64_t);
 818
 819         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 820                 if (ret) {
 821                         uint64_t *max_local_size = ret;
 822                         /* Value reported by the closed source driver. */
 823                         *max_local_size = 32768;
 824                 }
 825                 return sizeof(uint64_t);
 826
 827         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 828                 if (ret) {
 829                         uint64_t *max_input_size = ret;
 830                         /* Value reported by the closed source driver. */
 831                         *max_input_size = 1024;
 832                 }
 833                 return sizeof(uint64_t);
 834
 835         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 836                 if (ret) {
 837                         uint64_t *max_mem_alloc_size = ret;
 838
 839                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 840                 }
 841                 return sizeof(uint64_t);
 842
 843         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 844                 if (ret) {
 845                         uint32_t *max_clock_frequency = ret;
 846                         *max_clock_frequency = sscreen->info.max_shader_clock;
 847                 }
 848                 return sizeof(uint32_t);
 849
 850         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 851                 if (ret) {
 852                         uint32_t *max_compute_units = ret;
 853                         *max_compute_units = sscreen->info.num_good_compute_units;
 854                 }
 855                 return sizeof(uint32_t);
 856
 857         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 858                 if (ret) {
 859                         uint32_t *images_supported = ret;
 860                         *images_supported = 0;
 861                 }
 862                 return sizeof(uint32_t);
 863         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 864                 break; /* unused */
 865         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 866                 if (ret) {
 867                         uint32_t *subgroup_size = ret;
 868                         *subgroup_size = 64;
 869                 }
 870                 return sizeof(uint32_t);
 871         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 872                 if (ret) {
 873                         uint64_t *max_variable_threads_per_block = ret;
 874                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 875                                 *max_variable_threads_per_block = 0;
 876                         else
 877                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 878                 }
 879                 return sizeof(uint64_t);
 880         }
 881
 882         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 883         return 0;
 884 }
 885
 886 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 887 {
 888         struct si_screen *sscreen = (struct si_screen*)screen;
 889
 890         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 891                         sscreen->info.clock_crystal_freq;
 892 }
 893
 894 static void si_query_memory_info(struct pipe_screen *screen,
 895                                  struct pipe_memory_info *info)
 896 {
 897         struct si_screen *sscreen = (struct si_screen*)screen;
 898         struct radeon_winsys *ws = sscreen->ws;
 899         unsigned vram_usage, gtt_usage;
 900
 901         info->total_device_memory = sscreen->info.vram_size / 1024;
 902         info->total_staging_memory = sscreen->info.gart_size / 1024;
 903
 904         /* The real TTM memory usage is somewhat random, because:
 905          *
 906          * 1) TTM delays freeing memory, because it can only free it after
 907          *    fences expire.
 908          *
 909          * 2) The memory usage can be really low if big VRAM evictions are
 910          *    taking place, but the real usage is well above the size of VRAM.
 911          *
 912          * Instead, return statistics of this process.
 913          */
 914         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 915         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 916
 917         info->avail_device_memory =
 918                 vram_usage <= info->total_device_memory ?
 919                                 info->total_device_memory - vram_usage : 0;
 920         info->avail_staging_memory =
 921                 gtt_usage <= info->total_staging_memory ?
 922                                 info->total_staging_memory - gtt_usage : 0;
 923
 924         info->device_memory_evicted =
 925                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 926
 927         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 928                 info->nr_device_memory_evictions =
 929                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 930         else
 931                 /* Just return the number of evicted 64KB pages. */
 932                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 933 }
 934
 935 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 936 {
 937         struct si_screen *sscreen = (struct si_screen*)pscreen;
 938
 939         return sscreen->disk_shader_cache;
 940 }
 941
 942 static void si_init_renderer_string(struct si_screen *sscreen)
 943 {
 944         struct radeon_winsys *ws = sscreen->ws;
 945         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 946         struct utsname uname_data;
 947
 948         const char *marketing_name = si_get_marketing_name(ws);
 949
 950         if (marketing_name) {
 951                 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
 952                 snprintf(second_name, sizeof(second_name), "%s, ",
 953                          sscreen->info.name);
 954         } else {
 955                 snprintf(first_name, sizeof(first_name), "AMD %s",
 956                          sscreen->info.name);
 957         }
 958
 959         if (uname(&uname_data) == 0)
 960                 snprintf(kernel_version, sizeof(kernel_version),
 961                          ", %s", uname_data.release);
 962
 963         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 964                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 965                  first_name, second_name, sscreen->info.drm_major,
 966                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 967                  kernel_version,
 968                  (HAVE_LLVM >> 8) & 0xff,
 969                  HAVE_LLVM & 0xff,
 970                  MESA_LLVM_VERSION_PATCH);
 971 }
 972
 973 void si_init_screen_get_functions(struct si_screen *sscreen)
 974 {
 975         sscreen->b.get_name = si_get_name;
 976         sscreen->b.get_vendor = si_get_vendor;
 977         sscreen->b.get_device_vendor = si_get_device_vendor;
 978         sscreen->b.get_param = si_get_param;
 979         sscreen->b.get_paramf = si_get_paramf;
 980         sscreen->b.get_compute_param = si_get_compute_param;
 981         sscreen->b.get_timestamp = si_get_timestamp;
 982         sscreen->b.get_shader_param = si_get_shader_param;
 983         sscreen->b.get_compiler_options = si_get_compiler_options;
 984         sscreen->b.get_device_uuid = si_get_device_uuid;
 985         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 986         sscreen->b.query_memory_info = si_query_memory_info;
 987         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 988
 989         if (sscreen->info.has_hw_decode) {
 990                 sscreen->b.get_video_param = si_get_video_param;
 991                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 992         } else {
 993                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 994                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 995         }
 996
 997         si_init_renderer_string(sscreen);
 998 }