2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
35 #include <sys/utsname.h>
37 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
45 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
50 static const char *si_get_marketing_name(struct radeon_winsys
*ws
)
52 if (!ws
->get_chip_name
)
54 return ws
->get_chip_name(ws
);
57 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
59 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
62 /* Supported features (boolean caps). */
63 case PIPE_CAP_ACCELERATED
:
64 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
65 case PIPE_CAP_ANISOTROPIC_FILTER
:
66 case PIPE_CAP_POINT_SPRITE
:
67 case PIPE_CAP_OCCLUSION_QUERY
:
68 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
69 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
70 case PIPE_CAP_TEXTURE_SWIZZLE
:
71 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
72 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
73 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
74 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
75 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
76 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
77 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
79 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
80 case PIPE_CAP_PRIMITIVE_RESTART
:
81 case PIPE_CAP_CONDITIONAL_RENDER
:
82 case PIPE_CAP_TEXTURE_BARRIER
:
83 case PIPE_CAP_INDEP_BLEND_ENABLE
:
84 case PIPE_CAP_INDEP_BLEND_FUNC
:
85 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
86 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
87 case PIPE_CAP_START_INSTANCE
:
88 case PIPE_CAP_NPOT_TEXTURES
:
89 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
90 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
91 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
92 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
93 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
94 case PIPE_CAP_TGSI_INSTANCEID
:
95 case PIPE_CAP_COMPUTE
:
96 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
97 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
98 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
99 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
100 case PIPE_CAP_CUBE_MAP_ARRAY
:
101 case PIPE_CAP_SAMPLE_SHADING
:
102 case PIPE_CAP_DRAW_INDIRECT
:
103 case PIPE_CAP_CLIP_HALFZ
:
104 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
105 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
106 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
107 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
108 case PIPE_CAP_TGSI_TEXCOORD
:
109 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
110 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
111 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
112 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
113 case PIPE_CAP_SHAREABLE_SHADERS
:
114 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
115 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
116 case PIPE_CAP_TEXTURE_QUERY_LOD
:
117 case PIPE_CAP_TEXTURE_GATHER_SM5
:
118 case PIPE_CAP_TGSI_TXQS
:
119 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
120 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
121 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
122 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
123 case PIPE_CAP_INVALIDATE_BUFFER
:
124 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
125 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
126 case PIPE_CAP_QUERY_MEMORY_INFO
:
127 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
128 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
129 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
130 case PIPE_CAP_GENERATE_MIPMAP
:
131 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
132 case PIPE_CAP_STRING_MARKER
:
133 case PIPE_CAP_CLEAR_TEXTURE
:
134 case PIPE_CAP_CULL_DISTANCE
:
135 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
136 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
137 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
138 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
139 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
140 case PIPE_CAP_DOUBLES
:
141 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
142 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
143 case PIPE_CAP_BINDLESS_TEXTURE
:
144 case PIPE_CAP_QUERY_TIMESTAMP
:
145 case PIPE_CAP_QUERY_TIME_ELAPSED
:
146 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
147 case PIPE_CAP_QUERY_SO_OVERFLOW
:
148 case PIPE_CAP_MEMOBJ
:
149 case PIPE_CAP_LOAD_CONSTBUF
:
151 case PIPE_CAP_INT64_DIVMOD
:
152 case PIPE_CAP_TGSI_CLOCK
:
153 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
154 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
155 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
156 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
157 case PIPE_CAP_TGSI_BALLOT
:
158 case PIPE_CAP_TGSI_VOTE
:
159 case PIPE_CAP_TGSI_FS_FBFETCH
:
162 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
163 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
165 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
166 return sscreen
->info
.has_gpu_reset_status_query
||
167 sscreen
->info
.has_gpu_reset_counter_query
;
169 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
170 return sscreen
->info
.has_2d_tiling
;
172 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
173 return SI_MAP_BUFFER_ALIGNMENT
;
175 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
176 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
177 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
178 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
179 case PIPE_CAP_MAX_VERTEX_STREAMS
:
180 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
181 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
184 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
185 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
186 if (sscreen
->info
.has_indirect_compute_dispatch
)
187 return param
== PIPE_CAP_GLSL_FEATURE_LEVEL
?
191 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
192 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
194 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
195 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
196 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
197 return !sscreen
->info
.has_unaligned_shader_loads
;
199 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
200 return sscreen
->info
.has_sparse_vm_mappings
?
201 RADEON_SPARSE_PAGE_SIZE
: 0;
203 case PIPE_CAP_PACKED_UNIFORMS
:
204 if (sscreen
->debug_flags
& DBG(NIR
))
208 /* Unsupported features. */
209 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
210 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
211 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
212 case PIPE_CAP_USER_VERTEX_BUFFERS
:
213 case PIPE_CAP_FAKE_SW_MSAA
:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
215 case PIPE_CAP_VERTEXID_NOBASE
:
216 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
217 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
219 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
220 case PIPE_CAP_POST_DEPTH_COVERAGE
:
221 case PIPE_CAP_TILE_RASTER_ORDER
:
222 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
223 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
224 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
225 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
226 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
227 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
228 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
229 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
230 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
233 case PIPE_CAP_FENCE_SIGNAL
:
234 return sscreen
->info
.has_syncobj
;
236 case PIPE_CAP_CONSTBUF0_FLAGS
:
237 return SI_RESOURCE_FLAG_32BIT
;
239 case PIPE_CAP_NATIVE_FENCE_FD
:
240 return sscreen
->info
.has_fence_to_handle
;
242 case PIPE_CAP_DRAW_PARAMETERS
:
243 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
244 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
245 return sscreen
->has_draw_indirect_multi
;
247 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
250 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
251 return sscreen
->info
.chip_class
<= VI
?
252 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
255 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
256 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
259 /* Geometry shader output. */
260 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
262 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
264 case PIPE_CAP_MAX_GS_INVOCATIONS
:
267 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
271 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
272 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
273 return 15; /* 16384 */
274 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
275 /* textures support 8192, but layered rendering supports 2048 */
277 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
278 /* textures support 8192, but layered rendering supports 2048 */
281 /* Viewports and render targets. */
282 case PIPE_CAP_MAX_VIEWPORTS
:
283 return SI_MAX_VIEWPORTS
;
284 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
285 case PIPE_CAP_MAX_RENDER_TARGETS
:
287 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
288 return sscreen
->info
.has_eqaa_surface_allocator
? 2 : 0;
290 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
291 case PIPE_CAP_MIN_TEXEL_OFFSET
:
294 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
295 case PIPE_CAP_MAX_TEXEL_OFFSET
:
298 case PIPE_CAP_ENDIANNESS
:
299 return PIPE_ENDIAN_LITTLE
;
301 case PIPE_CAP_VENDOR_ID
:
302 return ATI_VENDOR_ID
;
303 case PIPE_CAP_DEVICE_ID
:
304 return sscreen
->info
.pci_id
;
305 case PIPE_CAP_VIDEO_MEMORY
:
306 return sscreen
->info
.vram_size
>> 20;
307 case PIPE_CAP_PCI_GROUP
:
308 return sscreen
->info
.pci_domain
;
309 case PIPE_CAP_PCI_BUS
:
310 return sscreen
->info
.pci_bus
;
311 case PIPE_CAP_PCI_DEVICE
:
312 return sscreen
->info
.pci_dev
;
313 case PIPE_CAP_PCI_FUNCTION
:
314 return sscreen
->info
.pci_func
;
319 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
322 case PIPE_CAPF_MAX_LINE_WIDTH
:
323 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
324 case PIPE_CAPF_MAX_POINT_WIDTH
:
325 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
327 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
329 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
331 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
332 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
333 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
339 static int si_get_shader_param(struct pipe_screen
* pscreen
,
340 enum pipe_shader_type shader
,
341 enum pipe_shader_cap param
)
343 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
347 case PIPE_SHADER_FRAGMENT
:
348 case PIPE_SHADER_VERTEX
:
349 case PIPE_SHADER_GEOMETRY
:
350 case PIPE_SHADER_TESS_CTRL
:
351 case PIPE_SHADER_TESS_EVAL
:
353 case PIPE_SHADER_COMPUTE
:
355 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
356 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
358 if (sscreen
->info
.has_indirect_compute_dispatch
)
359 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
364 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
365 uint64_t max_const_buffer_size
;
366 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
367 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
368 &max_const_buffer_size
);
369 return MIN2(max_const_buffer_size
, INT_MAX
);
372 /* If compute shaders don't require a special value
373 * for this cap, we can return the same value we
374 * do for other shader types. */
384 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
385 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
386 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
387 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
388 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
390 case PIPE_SHADER_CAP_MAX_INPUTS
:
391 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
392 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
393 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
394 case PIPE_SHADER_CAP_MAX_TEMPS
:
395 return 256; /* Max native temporaries. */
396 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
397 return 4096 * sizeof(float[4]); /* actually only memory limits this */
398 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
399 return SI_NUM_CONST_BUFFERS
;
400 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
401 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
402 return SI_NUM_SAMPLERS
;
403 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
404 return SI_NUM_SHADER_BUFFERS
;
405 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
406 return SI_NUM_IMAGES
;
407 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
408 if (sscreen
->debug_flags
& DBG(NIR
))
411 case PIPE_SHADER_CAP_PREFERRED_IR
:
412 if (sscreen
->debug_flags
& DBG(NIR
))
413 return PIPE_SHADER_IR_NIR
;
414 return PIPE_SHADER_IR_TGSI
;
415 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
418 /* Supported boolean features. */
419 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
420 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
421 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
422 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
423 case PIPE_SHADER_CAP_INTEGERS
:
424 case PIPE_SHADER_CAP_INT64_ATOMICS
:
425 case PIPE_SHADER_CAP_FP16
:
426 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
427 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
428 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
429 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
430 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
431 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
434 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
435 /* TODO: Indirect indexing of GS inputs is unimplemented. */
436 if (shader
== PIPE_SHADER_GEOMETRY
)
439 if (shader
== PIPE_SHADER_VERTEX
&&
440 !sscreen
->llvm_has_working_vgpr_indexing
)
443 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
444 * This means we don't support INTERP instructions with
445 * indirect indexing on inputs.
447 if (shader
== PIPE_SHADER_FRAGMENT
&&
448 !sscreen
->llvm_has_working_vgpr_indexing
&&
452 /* TCS and TES load inputs directly from LDS or offchip
453 * memory, so indirect indexing is always supported.
454 * PS has to support indirect indexing, because we can't
455 * lower that to TEMPs for INTERP instructions.
459 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
460 return sscreen
->llvm_has_working_vgpr_indexing
||
461 /* TCS stores outputs directly to memory. */
462 shader
== PIPE_SHADER_TESS_CTRL
;
464 /* Unsupported boolean features. */
465 case PIPE_SHADER_CAP_SUBROUTINES
:
466 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
467 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
468 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
470 case PIPE_SHADER_CAP_SCALAR_ISA
:
476 static const struct nir_shader_compiler_options nir_options
= {
478 .lower_flrp32
= true,
479 .lower_flrp64
= true,
485 .lower_pack_snorm_2x16
= true,
486 .lower_pack_snorm_4x8
= true,
487 .lower_pack_unorm_2x16
= true,
488 .lower_pack_unorm_4x8
= true,
489 .lower_unpack_snorm_2x16
= true,
490 .lower_unpack_snorm_4x8
= true,
491 .lower_unpack_unorm_2x16
= true,
492 .lower_unpack_unorm_4x8
= true,
493 .lower_extract_byte
= true,
494 .lower_extract_word
= true,
495 .max_unroll_iterations
= 32,
496 .native_integers
= true,
500 si_get_compiler_options(struct pipe_screen
*screen
,
501 enum pipe_shader_ir ir
,
502 enum pipe_shader_type shader
)
504 assert(ir
== PIPE_SHADER_IR_NIR
);
508 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
510 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
513 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
515 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
517 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
520 static const char* si_get_name(struct pipe_screen
*pscreen
)
522 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
524 return sscreen
->renderer_string
;
527 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
528 enum pipe_video_profile profile
,
529 enum pipe_video_entrypoint entrypoint
,
530 enum pipe_video_cap param
)
533 case PIPE_VIDEO_CAP_SUPPORTED
:
534 return vl_profile_supported(screen
, profile
, entrypoint
);
535 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
537 case PIPE_VIDEO_CAP_MAX_WIDTH
:
538 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
539 return vl_video_buffer_max_size(screen
);
540 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
541 return PIPE_FORMAT_NV12
;
542 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
544 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
546 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
548 case PIPE_VIDEO_CAP_MAX_LEVEL
:
549 return vl_level_supported(screen
, profile
);
555 static int si_get_video_param(struct pipe_screen
*screen
,
556 enum pipe_video_profile profile
,
557 enum pipe_video_entrypoint entrypoint
,
558 enum pipe_video_cap param
)
560 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
561 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
563 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
565 case PIPE_VIDEO_CAP_SUPPORTED
:
566 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
567 (si_vce_is_fw_version_supported(sscreen
) ||
568 sscreen
->info
.family
== CHIP_RAVEN
)) ||
569 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
570 (sscreen
->info
.family
== CHIP_RAVEN
||
571 si_radeon_uvd_enc_supported(sscreen
)));
572 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
574 case PIPE_VIDEO_CAP_MAX_WIDTH
:
575 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
576 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
577 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
578 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
579 return PIPE_FORMAT_NV12
;
580 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
582 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
584 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
586 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
587 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
594 case PIPE_VIDEO_CAP_SUPPORTED
:
596 case PIPE_VIDEO_FORMAT_MPEG12
:
597 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
598 case PIPE_VIDEO_FORMAT_MPEG4
:
600 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
601 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
602 sscreen
->info
.family
== CHIP_POLARIS11
) &&
603 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
604 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
608 case PIPE_VIDEO_FORMAT_VC1
:
610 case PIPE_VIDEO_FORMAT_HEVC
:
611 /* Carrizo only supports HEVC Main */
612 if (sscreen
->info
.family
>= CHIP_STONEY
)
613 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
614 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
615 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
616 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
618 case PIPE_VIDEO_FORMAT_JPEG
:
619 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
621 if (!(sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 19)) {
622 RVID_ERR("No MJPEG support for the kernel version\n");
626 case PIPE_VIDEO_FORMAT_VP9
:
627 if (sscreen
->info
.family
< CHIP_RAVEN
)
633 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
635 case PIPE_VIDEO_CAP_MAX_WIDTH
:
636 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
637 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
638 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
639 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
640 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
||
641 profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
642 return PIPE_FORMAT_P016
;
644 return PIPE_FORMAT_NV12
;
646 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
647 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
648 enum pipe_video_format format
= u_reduce_video_profile(profile
);
650 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
651 return false; //The firmware doesn't support interlaced HEVC.
652 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
654 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
658 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
660 case PIPE_VIDEO_CAP_MAX_LEVEL
:
662 case PIPE_VIDEO_PROFILE_MPEG1
:
664 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
665 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
667 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
669 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
671 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
673 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
675 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
677 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
678 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
679 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
680 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
681 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
682 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
692 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
693 enum pipe_format format
,
694 enum pipe_video_profile profile
,
695 enum pipe_video_entrypoint entrypoint
)
697 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
698 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
699 return (format
== PIPE_FORMAT_NV12
) ||
700 (format
== PIPE_FORMAT_P016
);
702 /* we can only handle this one with UVD */
703 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
704 return format
== PIPE_FORMAT_NV12
;
706 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
709 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
710 enum pipe_shader_ir ir_type
)
712 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
715 /* Only 16 waves per thread-group on gfx9. */
716 if (screen
->info
.chip_class
>= GFX9
)
719 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
725 static int si_get_compute_param(struct pipe_screen
*screen
,
726 enum pipe_shader_ir ir_type
,
727 enum pipe_compute_cap param
,
730 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
732 //TODO: select these params by asic
734 case PIPE_COMPUTE_CAP_IR_TARGET
: {
735 const char *gpu
, *triple
;
737 triple
= "amdgcn-mesa-mesa3d";
738 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
740 sprintf(ret
, "%s-%s", gpu
, triple
);
742 /* +2 for dash and terminating NIL byte */
743 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
745 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
747 uint64_t *grid_dimension
= ret
;
748 grid_dimension
[0] = 3;
750 return 1 * sizeof(uint64_t);
752 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
754 uint64_t *grid_size
= ret
;
755 grid_size
[0] = 65535;
756 grid_size
[1] = 65535;
757 grid_size
[2] = 65535;
759 return 3 * sizeof(uint64_t) ;
761 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
763 uint64_t *block_size
= ret
;
764 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
765 block_size
[0] = threads_per_block
;
766 block_size
[1] = threads_per_block
;
767 block_size
[2] = threads_per_block
;
769 return 3 * sizeof(uint64_t);
771 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
773 uint64_t *max_threads_per_block
= ret
;
774 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
776 return sizeof(uint64_t);
777 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
779 uint32_t *address_bits
= ret
;
780 address_bits
[0] = 64;
782 return 1 * sizeof(uint32_t);
784 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
786 uint64_t *max_global_size
= ret
;
787 uint64_t max_mem_alloc_size
;
789 si_get_compute_param(screen
, ir_type
,
790 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
791 &max_mem_alloc_size
);
793 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
794 * 1/4 of the MAX_GLOBAL_SIZE. Since the
795 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
796 * make sure we never report more than
797 * 4 * MAX_MEM_ALLOC_SIZE.
799 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
800 MAX2(sscreen
->info
.gart_size
,
801 sscreen
->info
.vram_size
));
803 return sizeof(uint64_t);
805 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
807 uint64_t *max_local_size
= ret
;
808 /* Value reported by the closed source driver. */
809 *max_local_size
= 32768;
811 return sizeof(uint64_t);
813 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
815 uint64_t *max_input_size
= ret
;
816 /* Value reported by the closed source driver. */
817 *max_input_size
= 1024;
819 return sizeof(uint64_t);
821 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
823 uint64_t *max_mem_alloc_size
= ret
;
825 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
827 return sizeof(uint64_t);
829 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
831 uint32_t *max_clock_frequency
= ret
;
832 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
834 return sizeof(uint32_t);
836 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
838 uint32_t *max_compute_units
= ret
;
839 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
841 return sizeof(uint32_t);
843 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
845 uint32_t *images_supported
= ret
;
846 *images_supported
= 0;
848 return sizeof(uint32_t);
849 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
851 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
853 uint32_t *subgroup_size
= ret
;
856 return sizeof(uint32_t);
857 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
859 uint64_t *max_variable_threads_per_block
= ret
;
860 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
861 *max_variable_threads_per_block
= 0;
863 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
865 return sizeof(uint64_t);
868 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
872 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
874 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
876 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
877 sscreen
->info
.clock_crystal_freq
;
880 static void si_query_memory_info(struct pipe_screen
*screen
,
881 struct pipe_memory_info
*info
)
883 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
884 struct radeon_winsys
*ws
= sscreen
->ws
;
885 unsigned vram_usage
, gtt_usage
;
887 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
888 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
890 /* The real TTM memory usage is somewhat random, because:
892 * 1) TTM delays freeing memory, because it can only free it after
895 * 2) The memory usage can be really low if big VRAM evictions are
896 * taking place, but the real usage is well above the size of VRAM.
898 * Instead, return statistics of this process.
900 vram_usage
= ws
->query_value(ws
, RADEON_VRAM_USAGE
) / 1024;
901 gtt_usage
= ws
->query_value(ws
, RADEON_GTT_USAGE
) / 1024;
903 info
->avail_device_memory
=
904 vram_usage
<= info
->total_device_memory
?
905 info
->total_device_memory
- vram_usage
: 0;
906 info
->avail_staging_memory
=
907 gtt_usage
<= info
->total_staging_memory
?
908 info
->total_staging_memory
- gtt_usage
: 0;
910 info
->device_memory_evicted
=
911 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
913 if (sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 4)
914 info
->nr_device_memory_evictions
=
915 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
917 /* Just return the number of evicted 64KB pages. */
918 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
921 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
923 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
925 return sscreen
->disk_shader_cache
;
928 static void si_init_renderer_string(struct si_screen
*sscreen
)
930 struct radeon_winsys
*ws
= sscreen
->ws
;
931 char first_name
[256], second_name
[32] = {}, kernel_version
[128] = {};
932 struct utsname uname_data
;
934 const char *marketing_name
= si_get_marketing_name(ws
);
936 if (marketing_name
) {
937 snprintf(first_name
, sizeof(first_name
), "%s", marketing_name
);
938 snprintf(second_name
, sizeof(second_name
), "%s, ",
941 snprintf(first_name
, sizeof(first_name
), "AMD %s",
945 if (uname(&uname_data
) == 0)
946 snprintf(kernel_version
, sizeof(kernel_version
),
947 ", %s", uname_data
.release
);
949 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
950 "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
951 first_name
, second_name
, sscreen
->info
.drm_major
,
952 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
954 (HAVE_LLVM
>> 8) & 0xff,
956 MESA_LLVM_VERSION_PATCH
);
959 void si_init_screen_get_functions(struct si_screen
*sscreen
)
961 sscreen
->b
.get_name
= si_get_name
;
962 sscreen
->b
.get_vendor
= si_get_vendor
;
963 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
964 sscreen
->b
.get_param
= si_get_param
;
965 sscreen
->b
.get_paramf
= si_get_paramf
;
966 sscreen
->b
.get_compute_param
= si_get_compute_param
;
967 sscreen
->b
.get_timestamp
= si_get_timestamp
;
968 sscreen
->b
.get_shader_param
= si_get_shader_param
;
969 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
970 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
971 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
972 sscreen
->b
.query_memory_info
= si_query_memory_info
;
973 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
975 if (sscreen
->info
.has_hw_decode
) {
976 sscreen
->b
.get_video_param
= si_get_video_param
;
977 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
979 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
980 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
983 si_init_renderer_string(sscreen
);