src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53         struct si_screen *sscreen = (struct si_screen *)pscreen;
  54
  55         switch (param) {
  56         /* Supported features (boolean caps). */
  57         case PIPE_CAP_ACCELERATED:
  58         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  59         case PIPE_CAP_ANISOTROPIC_FILTER:
  60         case PIPE_CAP_POINT_SPRITE:
  61         case PIPE_CAP_OCCLUSION_QUERY:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79         case PIPE_CAP_CONDITIONAL_RENDER:
  80         case PIPE_CAP_TEXTURE_BARRIER:
  81         case PIPE_CAP_INDEP_BLEND_ENABLE:
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85         case PIPE_CAP_START_INSTANCE:
  86         case PIPE_CAP_NPOT_TEXTURES:
  87         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92         case PIPE_CAP_TGSI_INSTANCEID:
  93         case PIPE_CAP_COMPUTE:
  94         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98         case PIPE_CAP_CUBE_MAP_ARRAY:
  99         case PIPE_CAP_SAMPLE_SHADING:
 100         case PIPE_CAP_DRAW_INDIRECT:
 101         case PIPE_CAP_CLIP_HALFZ:
 102         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106         case PIPE_CAP_TGSI_TEXCOORD:
 107         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111         case PIPE_CAP_SHAREABLE_SHADERS:
 112         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114         case PIPE_CAP_TEXTURE_QUERY_LOD:
 115         case PIPE_CAP_TEXTURE_GATHER_SM5:
 116         case PIPE_CAP_TGSI_TXQS:
 117         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121         case PIPE_CAP_INVALIDATE_BUFFER:
 122         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124         case PIPE_CAP_QUERY_MEMORY_INFO:
 125         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128         case PIPE_CAP_GENERATE_MIPMAP:
 129         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130         case PIPE_CAP_STRING_MARKER:
 131         case PIPE_CAP_CLEAR_TEXTURE:
 132         case PIPE_CAP_CULL_DISTANCE:
 133         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138         case PIPE_CAP_DOUBLES:
 139         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141         case PIPE_CAP_BINDLESS_TEXTURE:
 142         case PIPE_CAP_QUERY_TIMESTAMP:
 143         case PIPE_CAP_QUERY_TIME_ELAPSED:
 144         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145         case PIPE_CAP_MEMOBJ:
 146         case PIPE_CAP_LOAD_CONSTBUF:
 147         case PIPE_CAP_INT64:
 148         case PIPE_CAP_INT64_DIVMOD:
 149         case PIPE_CAP_TGSI_CLOCK:
 150         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 153         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 154         case PIPE_CAP_TGSI_BALLOT:
 155         case PIPE_CAP_TGSI_VOTE:
 156         case PIPE_CAP_FBFETCH:
 157         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 158         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 159         case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
 160         case PIPE_CAP_TGSI_DIV:
 161                 return 1;
 162
 163         case PIPE_CAP_QUERY_SO_OVERFLOW:
 164                 return !sscreen->use_ngg_streamout;
 165
 166         case PIPE_CAP_POST_DEPTH_COVERAGE:
 167                 return sscreen->info.chip_class >= GFX10;
 168
 169         case PIPE_CAP_GRAPHICS:
 170                 return sscreen->info.has_graphics;
 171
 172         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 173                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 174
 175         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 176                 return sscreen->info.has_gpu_reset_status_query;
 177
 178         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179                 return sscreen->info.has_2d_tiling;
 180
 181         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 182                 return SI_MAP_BUFFER_ALIGNMENT;
 183
 184         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 185         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 187         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 188         case PIPE_CAP_MAX_VERTEX_STREAMS:
 189         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 190         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 191                 return 4;
 192
 193         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 194         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 195                 if (sscreen->info.has_indirect_compute_dispatch)
 196                                 return 450;
 197                 return 420;
 198
 199         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 200                 /* Optimal number for good TexSubImage performance on Polaris10. */
 201                 return 64 * 1024 * 1024;
 202
 203         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 205                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 206
 207         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 208         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 210                 return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads;
 211
 212         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 213                 return sscreen->info.has_sparse_vm_mappings ?
 214                                 RADEON_SPARSE_PAGE_SIZE : 0;
 215
 216         case PIPE_CAP_PACKED_UNIFORMS:
 217         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 218                 if (sscreen->options.enable_nir)
 219                         return 1;
 220                 return 0;
 221
 222         /* Unsupported features. */
 223         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 224         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 225         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 226         case PIPE_CAP_USER_VERTEX_BUFFERS:
 227         case PIPE_CAP_FAKE_SW_MSAA:
 228         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 229         case PIPE_CAP_VERTEXID_NOBASE:
 230         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 231         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 232         case PIPE_CAP_UMA:
 233         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 234         case PIPE_CAP_TILE_RASTER_ORDER:
 235         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 236         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 237         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 238         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 239         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 240         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 241         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 242         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 243         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 244                 return 0;
 245
 246         case PIPE_CAP_FENCE_SIGNAL:
 247                 return sscreen->info.has_syncobj;
 248
 249         case PIPE_CAP_CONSTBUF0_FLAGS:
 250                 return SI_RESOURCE_FLAG_32BIT;
 251
 252         case PIPE_CAP_NATIVE_FENCE_FD:
 253                 return sscreen->info.has_fence_to_handle;
 254
 255         case PIPE_CAP_DRAW_PARAMETERS:
 256         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 257         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 258                 return sscreen->has_draw_indirect_multi;
 259
 260         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 261                 return 30;
 262
 263         case PIPE_CAP_MAX_VARYINGS:
 264                 return 32;
 265
 266         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 267                 return sscreen->info.chip_class <= GFX8 ?
 268                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 269
 270         /* Stream output. */
 271         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 272         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 273                 return 32*4;
 274
 275         /* Geometry shader output. */
 276         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 277                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 278                  * gfx8 and earlier can do 1024.
 279                  */
 280                 return 256;
 281         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 282                 return 4095;
 283         case PIPE_CAP_MAX_GS_INVOCATIONS:
 284                 /* The closed driver exposes 127, but 125 is the greatest
 285                  * number that works. */
 286                 return 125;
 287
 288         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 289                 return 2048;
 290
 291         /* Texturing. */
 292         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 293                 return 16384;
 294         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 295                 return 15; /* 16384 */
 296         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 297                 if (sscreen->info.chip_class >= GFX10)
 298                         return 14;
 299                 /* textures support 8192, but layered rendering supports 2048 */
 300                 return 12;
 301         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 302                 if (sscreen->info.chip_class >= GFX10)
 303                         return 8192;
 304                 /* textures support 8192, but layered rendering supports 2048 */
 305                 return 2048;
 306
 307         /* Viewports and render targets. */
 308         case PIPE_CAP_MAX_VIEWPORTS:
 309                 return SI_MAX_VIEWPORTS;
 310         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 311         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 312         case PIPE_CAP_MAX_RENDER_TARGETS:
 313                 return 8;
 314         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 315                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 316
 317         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 318         case PIPE_CAP_MIN_TEXEL_OFFSET:
 319                 return -32;
 320
 321         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 322         case PIPE_CAP_MAX_TEXEL_OFFSET:
 323                 return 31;
 324
 325         case PIPE_CAP_ENDIANNESS:
 326                 return PIPE_ENDIAN_LITTLE;
 327
 328         case PIPE_CAP_VENDOR_ID:
 329                 return ATI_VENDOR_ID;
 330         case PIPE_CAP_DEVICE_ID:
 331                 return sscreen->info.pci_id;
 332         case PIPE_CAP_VIDEO_MEMORY:
 333                 return sscreen->info.vram_size >> 20;
 334         case PIPE_CAP_PCI_GROUP:
 335                 return sscreen->info.pci_domain;
 336         case PIPE_CAP_PCI_BUS:
 337                 return sscreen->info.pci_bus;
 338         case PIPE_CAP_PCI_DEVICE:
 339                 return sscreen->info.pci_dev;
 340         case PIPE_CAP_PCI_FUNCTION:
 341                 return sscreen->info.pci_func;
 342         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 343                 return HAVE_LLVM >= 0x1000;
 344
 345         default:
 346                 return u_pipe_screen_get_param_defaults(pscreen, param);
 347         }
 348 }
 349
 350 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 351 {
 352         switch (param) {
 353         case PIPE_CAPF_MAX_LINE_WIDTH:
 354         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355                 /* This depends on the quant mode, though the precise interactions
 356                  * are unknown. */
 357                 return 2048;
 358         case PIPE_CAPF_MAX_POINT_WIDTH:
 359         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 360                 return SI_MAX_POINT_SIZE;
 361         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 362                 return 16.0f;
 363         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 364                 return 16.0f;
 365         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 366         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 367         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 368                 return 0.0f;
 369         }
 370         return 0.0f;
 371 }
 372
 373 static int si_get_shader_param(struct pipe_screen* pscreen,
 374                                enum pipe_shader_type shader,
 375                                enum pipe_shader_cap param)
 376 {
 377         struct si_screen *sscreen = (struct si_screen *)pscreen;
 378
 379         switch(shader)
 380         {
 381         case PIPE_SHADER_FRAGMENT:
 382         case PIPE_SHADER_VERTEX:
 383         case PIPE_SHADER_GEOMETRY:
 384         case PIPE_SHADER_TESS_CTRL:
 385         case PIPE_SHADER_TESS_EVAL:
 386                 break;
 387         case PIPE_SHADER_COMPUTE:
 388                 switch (param) {
 389                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 390                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 391
 392                         if (sscreen->info.has_indirect_compute_dispatch)
 393                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 394
 395                         return ir;
 396                 }
 397
 398                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 399                         uint64_t max_const_buffer_size;
 400                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 401                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 402                                 &max_const_buffer_size);
 403                         return MIN2(max_const_buffer_size, INT_MAX);
 404                 }
 405                 default:
 406                         /* If compute shaders don't require a special value
 407                          * for this cap, we can return the same value we
 408                          * do for other shader types. */
 409                         break;
 410                 }
 411                 break;
 412         default:
 413                 return 0;
 414         }
 415
 416         switch (param) {
 417         /* Shader limits. */
 418         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 419         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 420         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 421         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 422         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 423                 return 16384;
 424         case PIPE_SHADER_CAP_MAX_INPUTS:
 425                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 426         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 427                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 428         case PIPE_SHADER_CAP_MAX_TEMPS:
 429                 return 256; /* Max native temporaries. */
 430         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 431                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 432         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 433                 return SI_NUM_CONST_BUFFERS;
 434         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 435         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 436                 return SI_NUM_SAMPLERS;
 437         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 438                 return SI_NUM_SHADER_BUFFERS;
 439         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 440                 return SI_NUM_IMAGES;
 441         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 442                 if (sscreen->options.enable_nir)
 443                         return 0;
 444                 return 32;
 445         case PIPE_SHADER_CAP_PREFERRED_IR:
 446                 if (sscreen->options.enable_nir)
 447                         return PIPE_SHADER_IR_NIR;
 448                 return PIPE_SHADER_IR_TGSI;
 449         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 450                 return 4;
 451
 452         /* Supported boolean features. */
 453         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 454         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 455         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 456         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 457         case PIPE_SHADER_CAP_INTEGERS:
 458         case PIPE_SHADER_CAP_INT64_ATOMICS:
 459         case PIPE_SHADER_CAP_FP16:
 460         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 461         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 462         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 463         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 464         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 465         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 466                 return 1;
 467
 468         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 469                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 470                 if (shader == PIPE_SHADER_GEOMETRY)
 471                         return 0;
 472
 473                 if (shader == PIPE_SHADER_VERTEX &&
 474                     !sscreen->llvm_has_working_vgpr_indexing)
 475                         return 0;
 476
 477                 /* TCS and TES load inputs directly from LDS or offchip
 478                  * memory, so indirect indexing is always supported.
 479                  * PS has to support indirect indexing, because we can't
 480                  * lower that to TEMPs for INTERP instructions.
 481                  */
 482                 return 1;
 483
 484         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 485                 return sscreen->llvm_has_working_vgpr_indexing ||
 486                        /* TCS stores outputs directly to memory. */
 487                        shader == PIPE_SHADER_TESS_CTRL;
 488
 489         /* Unsupported boolean features. */
 490         case PIPE_SHADER_CAP_SUBROUTINES:
 491         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 492         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 493         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 494                 return 0;
 495         case PIPE_SHADER_CAP_SCALAR_ISA:
 496                 return 1;
 497         }
 498         return 0;
 499 }
 500
 501 static const struct nir_shader_compiler_options nir_options = {
 502         .lower_scmp = true,
 503         .lower_flrp32 = true,
 504         .lower_flrp64 = true,
 505         .lower_fsat = true,
 506         .lower_fdiv = true,
 507         .lower_bitfield_insert_to_bitfield_select = true,
 508         .lower_bitfield_extract = true,
 509         .lower_sub = true,
 510         .lower_ffma = true,
 511         .lower_fmod = true,
 512         .lower_pack_snorm_4x8 = true,
 513         .lower_pack_unorm_4x8 = true,
 514         .lower_unpack_snorm_2x16 = true,
 515         .lower_unpack_snorm_4x8 = true,
 516         .lower_unpack_unorm_2x16 = true,
 517         .lower_unpack_unorm_4x8 = true,
 518         .lower_extract_byte = true,
 519         .lower_extract_word = true,
 520         .lower_rotate = true,
 521         .optimize_sample_mask_in = true,
 522         .max_unroll_iterations = 32,
 523         .use_interpolated_input_intrinsics = true,
 524 };
 525
 526 static const void *
 527 si_get_compiler_options(struct pipe_screen *screen,
 528                         enum pipe_shader_ir ir,
 529                         enum pipe_shader_type shader)
 530 {
 531         assert(ir == PIPE_SHADER_IR_NIR);
 532         return &nir_options;
 533 }
 534
 535 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 536 {
 537         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 538 }
 539
 540 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 541 {
 542         struct si_screen *sscreen = (struct si_screen *)pscreen;
 543
 544         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 545 }
 546
 547 static const char* si_get_name(struct pipe_screen *pscreen)
 548 {
 549         struct si_screen *sscreen = (struct si_screen*)pscreen;
 550
 551         return sscreen->renderer_string;
 552 }
 553
 554 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 555                                         enum pipe_video_profile profile,
 556                                         enum pipe_video_entrypoint entrypoint,
 557                                         enum pipe_video_cap param)
 558 {
 559         switch (param) {
 560         case PIPE_VIDEO_CAP_SUPPORTED:
 561                 return vl_profile_supported(screen, profile, entrypoint);
 562         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 563                 return 1;
 564         case PIPE_VIDEO_CAP_MAX_WIDTH:
 565         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 566                 return vl_video_buffer_max_size(screen);
 567         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 568                 return PIPE_FORMAT_NV12;
 569         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 570                 return false;
 571         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 572                 return false;
 573         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 574                 return true;
 575         case PIPE_VIDEO_CAP_MAX_LEVEL:
 576                 return vl_level_supported(screen, profile);
 577         default:
 578                 return 0;
 579         }
 580 }
 581
 582 static int si_get_video_param(struct pipe_screen *screen,
 583                               enum pipe_video_profile profile,
 584                               enum pipe_video_entrypoint entrypoint,
 585                               enum pipe_video_cap param)
 586 {
 587         struct si_screen *sscreen = (struct si_screen *)screen;
 588         enum pipe_video_format codec = u_reduce_video_profile(profile);
 589
 590         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 591                 switch (param) {
 592                 case PIPE_VIDEO_CAP_SUPPORTED:
 593                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 594                                 (si_vce_is_fw_version_supported(sscreen) ||
 595                                 sscreen->info.family >= CHIP_RAVEN)) ||
 596                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 597                                 (sscreen->info.family >= CHIP_RAVEN ||
 598                                 si_radeon_uvd_enc_supported(sscreen)));
 599                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 600                         return 1;
 601                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 602                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 603                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 604                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 605                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 606                         return PIPE_FORMAT_NV12;
 607                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 608                         return false;
 609                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 610                         return false;
 611                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 612                         return true;
 613                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 614                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 615                 default:
 616                         return 0;
 617                 }
 618         }
 619
 620         switch (param) {
 621         case PIPE_VIDEO_CAP_SUPPORTED:
 622                 switch (codec) {
 623                 case PIPE_VIDEO_FORMAT_MPEG12:
 624                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 625                 case PIPE_VIDEO_FORMAT_MPEG4:
 626                         return 1;
 627                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 628                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 629                              sscreen->info.family == CHIP_POLARIS11) &&
 630                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 631                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 632                                 return false;
 633                         }
 634                         return true;
 635                 case PIPE_VIDEO_FORMAT_VC1:
 636                         return true;
 637                 case PIPE_VIDEO_FORMAT_HEVC:
 638                         /* Carrizo only supports HEVC Main */
 639                         if (sscreen->info.family >= CHIP_STONEY)
 640                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 641                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 642                         else if (sscreen->info.family >= CHIP_CARRIZO)
 643                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 644                         return false;
 645                 case PIPE_VIDEO_FORMAT_JPEG:
 646                         if (sscreen->info.family == CHIP_RAVEN ||
 647                             sscreen->info.family == CHIP_RAVEN2 ||
 648                             sscreen->info.family == CHIP_NAVI10)
 649                                 return true;
 650                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 651                                 return false;
 652                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 653                                 RVID_ERR("No MJPEG support for the kernel version\n");
 654                                 return false;
 655                         }
 656                         return true;
 657                 case PIPE_VIDEO_FORMAT_VP9:
 658                         if (sscreen->info.family < CHIP_RAVEN)
 659                                 return false;
 660                         return true;
 661                 default:
 662                         return false;
 663                 }
 664         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 665                 return 1;
 666         case PIPE_VIDEO_CAP_MAX_WIDTH:
 667                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 668         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 669                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 670         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 671                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 672                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 673                         return PIPE_FORMAT_P016;
 674                 else
 675                         return PIPE_FORMAT_NV12;
 676
 677         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 678         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 679                 enum pipe_video_format format = u_reduce_video_profile(profile);
 680
 681                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 682                         return false; //The firmware doesn't support interlaced HEVC.
 683                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 684                         return false;
 685                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 686                         return false;
 687                 return true;
 688         }
 689         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 690                 return true;
 691         case PIPE_VIDEO_CAP_MAX_LEVEL:
 692                 switch (profile) {
 693                 case PIPE_VIDEO_PROFILE_MPEG1:
 694                         return 0;
 695                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 696                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 697                         return 3;
 698                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 699                         return 3;
 700                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 701                         return 5;
 702                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 703                         return 1;
 704                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 705                         return 2;
 706                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 707                         return 4;
 708                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 709                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 710                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 711                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 712                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 713                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 714                         return 186;
 715                 default:
 716                         return 0;
 717                 }
 718         default:
 719                 return 0;
 720         }
 721 }
 722
 723 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 724                                        enum pipe_format format,
 725                                        enum pipe_video_profile profile,
 726                                        enum pipe_video_entrypoint entrypoint)
 727 {
 728         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 729         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 730                 return (format == PIPE_FORMAT_NV12) ||
 731                         (format == PIPE_FORMAT_P016);
 732
 733         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 734         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 735                 return format == PIPE_FORMAT_P016;
 736
 737
 738         /* we can only handle this one with UVD */
 739         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 740                 return format == PIPE_FORMAT_NV12;
 741
 742         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 743 }
 744
 745 static unsigned get_max_threads_per_block(struct si_screen *screen,
 746                                           enum pipe_shader_ir ir_type)
 747 {
 748         if (ir_type == PIPE_SHADER_IR_NATIVE)
 749                 return 256;
 750
 751         /* Only 16 waves per thread-group on gfx9. */
 752         if (screen->info.chip_class >= GFX9)
 753                 return 1024;
 754
 755         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 756          * round number.
 757          */
 758         return 2048;
 759 }
 760
 761 static int si_get_compute_param(struct pipe_screen *screen,
 762                                 enum pipe_shader_ir ir_type,
 763                                 enum pipe_compute_cap param,
 764                                 void *ret)
 765 {
 766         struct si_screen *sscreen = (struct si_screen *)screen;
 767
 768         //TODO: select these params by asic
 769         switch (param) {
 770         case PIPE_COMPUTE_CAP_IR_TARGET: {
 771                 const char *gpu, *triple;
 772
 773                 triple = "amdgcn-mesa-mesa3d";
 774                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 775                 if (ret) {
 776                         sprintf(ret, "%s-%s", gpu, triple);
 777                 }
 778                 /* +2 for dash and terminating NIL byte */
 779                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 780         }
 781         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 782                 if (ret) {
 783                         uint64_t *grid_dimension = ret;
 784                         grid_dimension[0] = 3;
 785                 }
 786                 return 1 * sizeof(uint64_t);
 787
 788         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 789                 if (ret) {
 790                         uint64_t *grid_size = ret;
 791                         grid_size[0] = 65535;
 792                         grid_size[1] = 65535;
 793                         grid_size[2] = 65535;
 794                 }
 795                 return 3 * sizeof(uint64_t) ;
 796
 797         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 798                 if (ret) {
 799                         uint64_t *block_size = ret;
 800                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 801                         block_size[0] = threads_per_block;
 802                         block_size[1] = threads_per_block;
 803                         block_size[2] = threads_per_block;
 804                 }
 805                 return 3 * sizeof(uint64_t);
 806
 807         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 808                 if (ret) {
 809                         uint64_t *max_threads_per_block = ret;
 810                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 811                 }
 812                 return sizeof(uint64_t);
 813         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 814                 if (ret) {
 815                         uint32_t *address_bits = ret;
 816                         address_bits[0] = 64;
 817                 }
 818                 return 1 * sizeof(uint32_t);
 819
 820         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 821                 if (ret) {
 822                         uint64_t *max_global_size = ret;
 823                         uint64_t max_mem_alloc_size;
 824
 825                         si_get_compute_param(screen, ir_type,
 826                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 827                                 &max_mem_alloc_size);
 828
 829                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 830                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 831                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 832                          * make sure we never report more than
 833                          * 4 * MAX_MEM_ALLOC_SIZE.
 834                          */
 835                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 836                                                 MAX2(sscreen->info.gart_size,
 837                                                      sscreen->info.vram_size));
 838                 }
 839                 return sizeof(uint64_t);
 840
 841         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 842                 if (ret) {
 843                         uint64_t *max_local_size = ret;
 844                         /* Value reported by the closed source driver. */
 845                         *max_local_size = 32768;
 846                 }
 847                 return sizeof(uint64_t);
 848
 849         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 850                 if (ret) {
 851                         uint64_t *max_input_size = ret;
 852                         /* Value reported by the closed source driver. */
 853                         *max_input_size = 1024;
 854                 }
 855                 return sizeof(uint64_t);
 856
 857         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 858                 if (ret) {
 859                         uint64_t *max_mem_alloc_size = ret;
 860
 861                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 862                 }
 863                 return sizeof(uint64_t);
 864
 865         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 866                 if (ret) {
 867                         uint32_t *max_clock_frequency = ret;
 868                         *max_clock_frequency = sscreen->info.max_shader_clock;
 869                 }
 870                 return sizeof(uint32_t);
 871
 872         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 873                 if (ret) {
 874                         uint32_t *max_compute_units = ret;
 875                         *max_compute_units = sscreen->info.num_good_compute_units;
 876                 }
 877                 return sizeof(uint32_t);
 878
 879         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 880                 if (ret) {
 881                         uint32_t *images_supported = ret;
 882                         *images_supported = 0;
 883                 }
 884                 return sizeof(uint32_t);
 885         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 886                 break; /* unused */
 887         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 888                 if (ret) {
 889                         uint32_t *subgroup_size = ret;
 890                         *subgroup_size = sscreen->compute_wave_size;
 891                 }
 892                 return sizeof(uint32_t);
 893         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 894                 if (ret) {
 895                         uint64_t *max_variable_threads_per_block = ret;
 896                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 897                                 *max_variable_threads_per_block = 0;
 898                         else
 899                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 900                 }
 901                 return sizeof(uint64_t);
 902         }
 903
 904         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 905         return 0;
 906 }
 907
 908 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 909 {
 910         struct si_screen *sscreen = (struct si_screen*)screen;
 911
 912         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 913                         sscreen->info.clock_crystal_freq;
 914 }
 915
 916 static void si_query_memory_info(struct pipe_screen *screen,
 917                                  struct pipe_memory_info *info)
 918 {
 919         struct si_screen *sscreen = (struct si_screen*)screen;
 920         struct radeon_winsys *ws = sscreen->ws;
 921         unsigned vram_usage, gtt_usage;
 922
 923         info->total_device_memory = sscreen->info.vram_size / 1024;
 924         info->total_staging_memory = sscreen->info.gart_size / 1024;
 925
 926         /* The real TTM memory usage is somewhat random, because:
 927          *
 928          * 1) TTM delays freeing memory, because it can only free it after
 929          *    fences expire.
 930          *
 931          * 2) The memory usage can be really low if big VRAM evictions are
 932          *    taking place, but the real usage is well above the size of VRAM.
 933          *
 934          * Instead, return statistics of this process.
 935          */
 936         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 937         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 938
 939         info->avail_device_memory =
 940                 vram_usage <= info->total_device_memory ?
 941                                 info->total_device_memory - vram_usage : 0;
 942         info->avail_staging_memory =
 943                 gtt_usage <= info->total_staging_memory ?
 944                                 info->total_staging_memory - gtt_usage : 0;
 945
 946         info->device_memory_evicted =
 947                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 948
 949         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 950                 info->nr_device_memory_evictions =
 951                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 952         else
 953                 /* Just return the number of evicted 64KB pages. */
 954                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 955 }
 956
 957 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 958 {
 959         struct si_screen *sscreen = (struct si_screen*)pscreen;
 960
 961         return sscreen->disk_shader_cache;
 962 }
 963
 964 static void si_init_renderer_string(struct si_screen *sscreen)
 965 {
 966         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 967         struct utsname uname_data;
 968
 969         if (sscreen->info.marketing_name) {
 970                 snprintf(first_name, sizeof(first_name), "%s",
 971                          sscreen->info.marketing_name);
 972                 snprintf(second_name, sizeof(second_name), "%s, ",
 973                          sscreen->info.name);
 974         } else {
 975                 snprintf(first_name, sizeof(first_name), "AMD %s",
 976                          sscreen->info.name);
 977         }
 978
 979         if (uname(&uname_data) == 0)
 980                 snprintf(kernel_version, sizeof(kernel_version),
 981                          ", %s", uname_data.release);
 982
 983         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 984                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 985                  first_name, second_name, sscreen->info.drm_major,
 986                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 987                  kernel_version);
 988 }
 989
 990 void si_init_screen_get_functions(struct si_screen *sscreen)
 991 {
 992         sscreen->b.get_name = si_get_name;
 993         sscreen->b.get_vendor = si_get_vendor;
 994         sscreen->b.get_device_vendor = si_get_device_vendor;
 995         sscreen->b.get_param = si_get_param;
 996         sscreen->b.get_paramf = si_get_paramf;
 997         sscreen->b.get_compute_param = si_get_compute_param;
 998         sscreen->b.get_timestamp = si_get_timestamp;
 999         sscreen->b.get_shader_param = si_get_shader_param;
1000         sscreen->b.get_compiler_options = si_get_compiler_options;
1001         sscreen->b.get_device_uuid = si_get_device_uuid;
1002         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1003         sscreen->b.query_memory_info = si_query_memory_info;
1004         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1005
1006         if (sscreen->info.has_hw_decode) {
1007                 sscreen->b.get_video_param = si_get_video_param;
1008                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1009         } else {
1010                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1011                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1012         }
1013
1014         si_init_renderer_string(sscreen);
1015 }