src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26 #include "radeon/radeon_uvd_enc.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_video.h"
  29 #include "si_pipe.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_video.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38    /* Don't change this. Games such as Alien Isolation are broken if this
  39     * returns "Advanced Micro Devices, Inc."
  40     */
  41    return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46    return "AMD";
  47 }
  48
  49 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  50 {
  51    struct si_screen *sscreen = (struct si_screen *)pscreen;
  52
  53    switch (param) {
  54    /* Supported features (boolean caps). */
  55    case PIPE_CAP_ACCELERATED:
  56    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  57    case PIPE_CAP_ANISOTROPIC_FILTER:
  58    case PIPE_CAP_POINT_SPRITE:
  59    case PIPE_CAP_OCCLUSION_QUERY:
  60    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61    case PIPE_CAP_TEXTURE_SHADOW_LOD:
  62    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64    case PIPE_CAP_TEXTURE_SWIZZLE:
  65    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77    case PIPE_CAP_PRIMITIVE_RESTART:
  78    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
  79    case PIPE_CAP_CONDITIONAL_RENDER:
  80    case PIPE_CAP_TEXTURE_BARRIER:
  81    case PIPE_CAP_INDEP_BLEND_ENABLE:
  82    case PIPE_CAP_INDEP_BLEND_FUNC:
  83    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85    case PIPE_CAP_START_INSTANCE:
  86    case PIPE_CAP_NPOT_TEXTURES:
  87    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92    case PIPE_CAP_TGSI_INSTANCEID:
  93    case PIPE_CAP_COMPUTE:
  94    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98    case PIPE_CAP_CUBE_MAP_ARRAY:
  99    case PIPE_CAP_SAMPLE_SHADING:
 100    case PIPE_CAP_DRAW_INDIRECT:
 101    case PIPE_CAP_CLIP_HALFZ:
 102    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106    case PIPE_CAP_TGSI_TEXCOORD:
 107    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111    case PIPE_CAP_SHAREABLE_SHADERS:
 112    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114    case PIPE_CAP_TEXTURE_QUERY_LOD:
 115    case PIPE_CAP_TEXTURE_GATHER_SM5:
 116    case PIPE_CAP_TGSI_TXQS:
 117    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121    case PIPE_CAP_INVALIDATE_BUFFER:
 122    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124    case PIPE_CAP_QUERY_MEMORY_INFO:
 125    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128    case PIPE_CAP_GENERATE_MIPMAP:
 129    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130    case PIPE_CAP_STRING_MARKER:
 131    case PIPE_CAP_CLEAR_TEXTURE:
 132    case PIPE_CAP_CULL_DISTANCE:
 133    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138    case PIPE_CAP_DOUBLES:
 139    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141    case PIPE_CAP_BINDLESS_TEXTURE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_QUERY_TIME_ELAPSED:
 144    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145    case PIPE_CAP_MEMOBJ:
 146    case PIPE_CAP_LOAD_CONSTBUF:
 147    case PIPE_CAP_INT64:
 148    case PIPE_CAP_INT64_DIVMOD:
 149    case PIPE_CAP_TGSI_CLOCK:
 150    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TGSI_BALLOT:
 154    case PIPE_CAP_TGSI_VOTE:
 155    case PIPE_CAP_FBFETCH:
 156    case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158    case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159    case PIPE_CAP_TGSI_DIV:
 160    case PIPE_CAP_PACKED_UNIFORMS:
 161    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162    case PIPE_CAP_GL_SPIRV:
 163    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 164    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
 165    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
 166    case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
 167       return 1;
 168
 169    case PIPE_CAP_GLSL_ZERO_INIT:
 170       return 2;
 171
 172    case PIPE_CAP_QUERY_SO_OVERFLOW:
 173       return !sscreen->use_ngg_streamout;
 174
 175    case PIPE_CAP_POST_DEPTH_COVERAGE:
 176       return sscreen->info.chip_class >= GFX10;
 177
 178    case PIPE_CAP_GRAPHICS:
 179       return sscreen->info.has_graphics;
 180
 181    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 182       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 183
 184    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 185       return sscreen->info.has_gpu_reset_status_query;
 186
 187    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 188       return sscreen->info.has_2d_tiling;
 189
 190    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 191       return SI_MAP_BUFFER_ALIGNMENT;
 192
 193    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 194    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 196    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 197    case PIPE_CAP_MAX_VERTEX_STREAMS:
 198    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 199    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 200       return 4;
 201
 202    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 203    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 204       if (!sscreen->info.has_indirect_compute_dispatch)
 205          return 420;
 206       return 460;
 207
 208    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 209       /* Optimal number for good TexSubImage performance on Polaris10. */
 210       return 64 * 1024 * 1024;
 211
 212    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 213       return 4096 * 1024;
 214
 215    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 216    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 217       /* Align it down to 256 bytes. I've chosen the number randomly. */
 218       return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256);
 219
 220    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 223       return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 224
 225    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 226       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 227
 228    case PIPE_CAP_UMA:
 229    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 230       return 0;
 231
 232    case PIPE_CAP_FENCE_SIGNAL:
 233       return sscreen->info.has_syncobj;
 234
 235    case PIPE_CAP_CONSTBUF0_FLAGS:
 236       return SI_RESOURCE_FLAG_32BIT;
 237
 238    case PIPE_CAP_NATIVE_FENCE_FD:
 239       return sscreen->info.has_fence_to_handle;
 240
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 243    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 244       return sscreen->has_draw_indirect_multi;
 245
 246    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 247       return 30;
 248
 249    case PIPE_CAP_MAX_VARYINGS:
 250       return 32;
 251
 252    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 253       return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 254
 255    /* Stream output. */
 256    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 257    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 258       return 32 * 4;
 259
 260    /* Geometry shader output. */
 261    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 262       /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 263        * gfx8 and earlier can do 1024.
 264        */
 265       return 256;
 266    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 267       return 4095;
 268    case PIPE_CAP_MAX_GS_INVOCATIONS:
 269       /* Even though the hw supports more, we officially wanna expose only 32. */
 270       return 32;
 271
 272    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 273       return 2048;
 274
 275    /* Texturing. */
 276    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 277       return 16384;
 278    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 279       return 15; /* 16384 */
 280    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 281       if (sscreen->info.chip_class >= GFX10)
 282          return 14;
 283       /* textures support 8192, but layered rendering supports 2048 */
 284       return 12;
 285    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 286       if (sscreen->info.chip_class >= GFX10)
 287          return 8192;
 288       /* textures support 8192, but layered rendering supports 2048 */
 289       return 2048;
 290
 291    /* Viewports and render targets. */
 292    case PIPE_CAP_MAX_VIEWPORTS:
 293       return SI_MAX_VIEWPORTS;
 294    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 295    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 296    case PIPE_CAP_MAX_RENDER_TARGETS:
 297       return 8;
 298    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 299       return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 300
 301    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 302    case PIPE_CAP_MIN_TEXEL_OFFSET:
 303       return -32;
 304
 305    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 306    case PIPE_CAP_MAX_TEXEL_OFFSET:
 307       return 31;
 308
 309    case PIPE_CAP_ENDIANNESS:
 310       return PIPE_ENDIAN_LITTLE;
 311
 312    case PIPE_CAP_VENDOR_ID:
 313       return ATI_VENDOR_ID;
 314    case PIPE_CAP_DEVICE_ID:
 315       return sscreen->info.pci_id;
 316    case PIPE_CAP_VIDEO_MEMORY:
 317       return sscreen->info.vram_size >> 20;
 318    case PIPE_CAP_PCI_GROUP:
 319       return sscreen->info.pci_domain;
 320    case PIPE_CAP_PCI_BUS:
 321       return sscreen->info.pci_bus;
 322    case PIPE_CAP_PCI_DEVICE:
 323       return sscreen->info.pci_dev;
 324    case PIPE_CAP_PCI_FUNCTION:
 325       return sscreen->info.pci_func;
 326    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 327       return LLVM_VERSION_MAJOR >= 10;
 328
 329    default:
 330       return u_pipe_screen_get_param_defaults(pscreen, param);
 331    }
 332 }
 333
 334 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 335 {
 336    switch (param) {
 337    case PIPE_CAPF_MAX_LINE_WIDTH:
 338    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339       /* This depends on the quant mode, though the precise interactions
 340        * are unknown. */
 341       return 2048;
 342    case PIPE_CAPF_MAX_POINT_WIDTH:
 343    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 344       return SI_MAX_POINT_SIZE;
 345    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 346       return 16.0f;
 347    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 348       return 16.0f;
 349    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 350    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 351    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 352       return 0.0f;
 353    }
 354    return 0.0f;
 355 }
 356
 357 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
 358                                enum pipe_shader_cap param)
 359 {
 360    struct si_screen *sscreen = (struct si_screen *)pscreen;
 361
 362    switch (shader) {
 363    case PIPE_SHADER_FRAGMENT:
 364    case PIPE_SHADER_VERTEX:
 365    case PIPE_SHADER_GEOMETRY:
 366    case PIPE_SHADER_TESS_CTRL:
 367    case PIPE_SHADER_TESS_EVAL:
 368       break;
 369    case PIPE_SHADER_COMPUTE:
 370       switch (param) {
 371       case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 372          int ir = 1 << PIPE_SHADER_IR_NATIVE;
 373
 374          if (sscreen->info.has_indirect_compute_dispatch)
 375             ir |= 1 << PIPE_SHADER_IR_NIR;
 376
 377          return ir;
 378       }
 379       default:
 380          /* If compute shaders don't require a special value
 381           * for this cap, we can return the same value we
 382           * do for other shader types. */
 383          break;
 384       }
 385       break;
 386    default:
 387       return 0;
 388    }
 389
 390    switch (param) {
 391    /* Shader limits. */
 392    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 393    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 394    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 395    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 396    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 397       return 16384;
 398    case PIPE_SHADER_CAP_MAX_INPUTS:
 399       return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 400    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 401       return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 402    case PIPE_SHADER_CAP_MAX_TEMPS:
 403       return 256; /* Max native temporaries. */
 404    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 405       return si_get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE);
 406    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 407       return SI_NUM_CONST_BUFFERS;
 408    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 409    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 410       return SI_NUM_SAMPLERS;
 411    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 412       return SI_NUM_SHADER_BUFFERS;
 413    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 414       return SI_NUM_IMAGES;
 415    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 416       return 0;
 417    case PIPE_SHADER_CAP_PREFERRED_IR:
 418       return PIPE_SHADER_IR_NIR;
 419    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 420       return 4;
 421
 422    /* Supported boolean features. */
 423    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 425    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 426    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 427    case PIPE_SHADER_CAP_INTEGERS:
 428    case PIPE_SHADER_CAP_INT64_ATOMICS:
 429    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 431    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 432    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 434    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 435       return 1;
 436
 437    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 438       /* TODO: Indirect indexing of GS inputs is unimplemented. */
 439       if (shader == PIPE_SHADER_GEOMETRY)
 440          return 0;
 441
 442       if (shader == PIPE_SHADER_VERTEX && !sscreen->llvm_has_working_vgpr_indexing)
 443          return 0;
 444
 445       /* TCS and TES load inputs directly from LDS or offchip
 446        * memory, so indirect indexing is always supported.
 447        * PS has to support indirect indexing, because we can't
 448        * lower that to TEMPs for INTERP instructions.
 449        */
 450       return 1;
 451
 452    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 453       return sscreen->llvm_has_working_vgpr_indexing ||
 454              /* TCS stores outputs directly to memory. */
 455              shader == PIPE_SHADER_TESS_CTRL;
 456
 457    /* Unsupported boolean features. */
 458    case PIPE_SHADER_CAP_FP16:
 459    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 460    case PIPE_SHADER_CAP_INT16:
 461    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 462    case PIPE_SHADER_CAP_SUBROUTINES:
 463    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 464    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 465    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 466       return 0;
 467    }
 468    return 0;
 469 }
 470
 471 static const struct nir_shader_compiler_options nir_options = {
 472    .lower_scmp = true,
 473    .lower_flrp32 = true,
 474    .lower_flrp64 = true,
 475    .lower_fsat = true,
 476    .lower_fdiv = true,
 477    .lower_bitfield_insert_to_bitfield_select = true,
 478    .lower_bitfield_extract = true,
 479    .lower_sub = true,
 480    .fuse_ffma = true,
 481    .lower_fmod = true,
 482    .lower_pack_snorm_4x8 = true,
 483    .lower_pack_unorm_4x8 = true,
 484    .lower_unpack_snorm_2x16 = true,
 485    .lower_unpack_snorm_4x8 = true,
 486    .lower_unpack_unorm_2x16 = true,
 487    .lower_unpack_unorm_4x8 = true,
 488    .lower_extract_byte = true,
 489    .lower_extract_word = true,
 490    .lower_rotate = true,
 491    .lower_to_scalar = true,
 492    .optimize_sample_mask_in = true,
 493    .max_unroll_iterations = 32,
 494    .use_interpolated_input_intrinsics = true,
 495 };
 496
 497 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
 498                                            enum pipe_shader_type shader)
 499 {
 500    assert(ir == PIPE_SHADER_IR_NIR);
 501    return &nir_options;
 502 }
 503
 504 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 505 {
 506    ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 507 }
 508
 509 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 510 {
 511    struct si_screen *sscreen = (struct si_screen *)pscreen;
 512
 513    ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 514 }
 515
 516 static const char *si_get_name(struct pipe_screen *pscreen)
 517 {
 518    struct si_screen *sscreen = (struct si_screen *)pscreen;
 519
 520    return sscreen->renderer_string;
 521 }
 522
 523 static int si_get_video_param_no_decode(struct pipe_screen *screen, enum pipe_video_profile profile,
 524                                         enum pipe_video_entrypoint entrypoint,
 525                                         enum pipe_video_cap param)
 526 {
 527    switch (param) {
 528    case PIPE_VIDEO_CAP_SUPPORTED:
 529       return vl_profile_supported(screen, profile, entrypoint);
 530    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 531       return 1;
 532    case PIPE_VIDEO_CAP_MAX_WIDTH:
 533    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 534       return vl_video_buffer_max_size(screen);
 535    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 536       return PIPE_FORMAT_NV12;
 537    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 538       return false;
 539    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 540       return false;
 541    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 542       return true;
 543    case PIPE_VIDEO_CAP_MAX_LEVEL:
 544       return vl_level_supported(screen, profile);
 545    default:
 546       return 0;
 547    }
 548 }
 549
 550 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
 551                               enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
 552 {
 553    struct si_screen *sscreen = (struct si_screen *)screen;
 554    enum pipe_video_format codec = u_reduce_video_profile(profile);
 555
 556    if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 557       switch (param) {
 558       case PIPE_VIDEO_CAP_SUPPORTED:
 559          return (
 560             (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 561              (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
 562             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 563              (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
 564             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
 565       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 566          return 1;
 567       case PIPE_VIDEO_CAP_MAX_WIDTH:
 568          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 569       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 570          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 571       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 572          return PIPE_FORMAT_NV12;
 573       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 574          return false;
 575       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 576          return false;
 577       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 578          return true;
 579       case PIPE_VIDEO_CAP_STACKED_FRAMES:
 580          return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 581       default:
 582          return 0;
 583       }
 584    }
 585
 586    switch (param) {
 587    case PIPE_VIDEO_CAP_SUPPORTED:
 588       switch (codec) {
 589       case PIPE_VIDEO_FORMAT_MPEG12:
 590          return profile != PIPE_VIDEO_PROFILE_MPEG1;
 591       case PIPE_VIDEO_FORMAT_MPEG4:
 592          return 1;
 593       case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 594          if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
 595              sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
 596             RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 597             return false;
 598          }
 599          return true;
 600       case PIPE_VIDEO_FORMAT_VC1:
 601          return true;
 602       case PIPE_VIDEO_FORMAT_HEVC:
 603          /* Carrizo only supports HEVC Main */
 604          if (sscreen->info.family >= CHIP_STONEY)
 605             return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 606                     profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 607          else if (sscreen->info.family >= CHIP_CARRIZO)
 608             return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 609          return false;
 610       case PIPE_VIDEO_FORMAT_JPEG:
 611          if (sscreen->info.family >= CHIP_RAVEN)
 612             return true;
 613          if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 614             return false;
 615          if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 616             RVID_ERR("No MJPEG support for the kernel version\n");
 617             return false;
 618          }
 619          return true;
 620       case PIPE_VIDEO_FORMAT_VP9:
 621          if (sscreen->info.family < CHIP_RAVEN)
 622             return false;
 623          return true;
 624       default:
 625          return false;
 626       }
 627    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 628       return 1;
 629    case PIPE_VIDEO_CAP_MAX_WIDTH:
 630       switch (codec) {
 631       case PIPE_VIDEO_FORMAT_HEVC:
 632       case PIPE_VIDEO_FORMAT_VP9:
 633          return (sscreen->info.family < CHIP_RENOIR)
 634                    ? ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096)
 635                    : 8192;
 636       default:
 637          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 638       }
 639    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 640       switch (codec) {
 641       case PIPE_VIDEO_FORMAT_HEVC:
 642       case PIPE_VIDEO_FORMAT_VP9:
 643          return (sscreen->info.family < CHIP_RENOIR)
 644                    ? ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096)
 645                    : 4352;
 646       default:
 647          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 648       }
 649    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 650       if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 651          return PIPE_FORMAT_P010;
 652       else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 653          return PIPE_FORMAT_P010;
 654       else
 655          return PIPE_FORMAT_NV12;
 656
 657    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 658    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 659       enum pipe_video_format format = u_reduce_video_profile(profile);
 660
 661       if (format == PIPE_VIDEO_FORMAT_HEVC)
 662          return false; // The firmware doesn't support interlaced HEVC.
 663       else if (format == PIPE_VIDEO_FORMAT_JPEG)
 664          return false;
 665       else if (format == PIPE_VIDEO_FORMAT_VP9)
 666          return false;
 667       return true;
 668    }
 669    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 670       return true;
 671    case PIPE_VIDEO_CAP_MAX_LEVEL:
 672       switch (profile) {
 673       case PIPE_VIDEO_PROFILE_MPEG1:
 674          return 0;
 675       case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 676       case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 677          return 3;
 678       case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 679          return 3;
 680       case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 681          return 5;
 682       case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 683          return 1;
 684       case PIPE_VIDEO_PROFILE_VC1_MAIN:
 685          return 2;
 686       case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 687          return 4;
 688       case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 689       case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 690       case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 691          return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 692       case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 693       case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 694          return 186;
 695       default:
 696          return 0;
 697       }
 698    default:
 699       return 0;
 700    }
 701 }
 702
 703 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
 704                                        enum pipe_video_profile profile,
 705                                        enum pipe_video_entrypoint entrypoint)
 706 {
 707    /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 708    if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 709       return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
 710              (format == PIPE_FORMAT_P016);
 711
 712    /* Vp9 profile 2 supports 10 bit decoding using P016 */
 713    if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 714       return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
 715
 716    /* we can only handle this one with UVD */
 717    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 718       return format == PIPE_FORMAT_NV12;
 719
 720    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 721 }
 722
 723 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
 724 {
 725    if (ir_type == PIPE_SHADER_IR_NATIVE)
 726       return 256;
 727
 728    /* LLVM 10 only supports 1024 threads per block. */
 729    return 1024;
 730 }
 731
 732 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
 733                                 enum pipe_compute_cap param, void *ret)
 734 {
 735    struct si_screen *sscreen = (struct si_screen *)screen;
 736
 737    // TODO: select these params by asic
 738    switch (param) {
 739    case PIPE_COMPUTE_CAP_IR_TARGET: {
 740       const char *gpu, *triple;
 741
 742       triple = "amdgcn-mesa-mesa3d";
 743       gpu = ac_get_llvm_processor_name(sscreen->info.family);
 744       if (ret) {
 745          sprintf(ret, "%s-%s", gpu, triple);
 746       }
 747       /* +2 for dash and terminating NIL byte */
 748       return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 749    }
 750    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 751       if (ret) {
 752          uint64_t *grid_dimension = ret;
 753          grid_dimension[0] = 3;
 754       }
 755       return 1 * sizeof(uint64_t);
 756
 757    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 758       if (ret) {
 759          uint64_t *grid_size = ret;
 760          grid_size[0] = 65535;
 761          grid_size[1] = 65535;
 762          grid_size[2] = 65535;
 763       }
 764       return 3 * sizeof(uint64_t);
 765
 766    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 767       if (ret) {
 768          uint64_t *block_size = ret;
 769          unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 770          block_size[0] = threads_per_block;
 771          block_size[1] = threads_per_block;
 772          block_size[2] = threads_per_block;
 773       }
 774       return 3 * sizeof(uint64_t);
 775
 776    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 777       if (ret) {
 778          uint64_t *max_threads_per_block = ret;
 779          *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 780       }
 781       return sizeof(uint64_t);
 782    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 783       if (ret) {
 784          uint32_t *address_bits = ret;
 785          address_bits[0] = 64;
 786       }
 787       return 1 * sizeof(uint32_t);
 788
 789    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 790       if (ret) {
 791          uint64_t *max_global_size = ret;
 792          uint64_t max_mem_alloc_size;
 793
 794          si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 795                               &max_mem_alloc_size);
 796
 797          /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 798           * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 799           * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 800           * make sure we never report more than
 801           * 4 * MAX_MEM_ALLOC_SIZE.
 802           */
 803          *max_global_size =
 804             MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
 805       }
 806       return sizeof(uint64_t);
 807
 808    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 809       if (ret) {
 810          uint64_t *max_local_size = ret;
 811          /* Value reported by the closed source driver. */
 812          *max_local_size = 32768;
 813       }
 814       return sizeof(uint64_t);
 815
 816    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 817       if (ret) {
 818          uint64_t *max_input_size = ret;
 819          /* Value reported by the closed source driver. */
 820          *max_input_size = 1024;
 821       }
 822       return sizeof(uint64_t);
 823
 824    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 825       if (ret) {
 826          uint64_t *max_mem_alloc_size = ret;
 827
 828          *max_mem_alloc_size = sscreen->info.max_alloc_size;
 829       }
 830       return sizeof(uint64_t);
 831
 832    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 833       if (ret) {
 834          uint32_t *max_clock_frequency = ret;
 835          *max_clock_frequency = sscreen->info.max_shader_clock;
 836       }
 837       return sizeof(uint32_t);
 838
 839    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 840       if (ret) {
 841          uint32_t *max_compute_units = ret;
 842          *max_compute_units = sscreen->info.num_good_compute_units;
 843       }
 844       return sizeof(uint32_t);
 845
 846    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 847       if (ret) {
 848          uint32_t *images_supported = ret;
 849          *images_supported = 0;
 850       }
 851       return sizeof(uint32_t);
 852    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 853       break; /* unused */
 854    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 855       if (ret) {
 856          uint32_t *subgroup_size = ret;
 857          *subgroup_size = sscreen->compute_wave_size;
 858       }
 859       return sizeof(uint32_t);
 860    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 861       if (ret) {
 862          uint64_t *max_variable_threads_per_block = ret;
 863          if (ir_type == PIPE_SHADER_IR_NATIVE)
 864             *max_variable_threads_per_block = 0;
 865          else
 866             *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 867       }
 868       return sizeof(uint64_t);
 869    }
 870
 871    fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 872    return 0;
 873 }
 874
 875 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 876 {
 877    struct si_screen *sscreen = (struct si_screen *)screen;
 878
 879    return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 880           sscreen->info.clock_crystal_freq;
 881 }
 882
 883 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
 884 {
 885    struct si_screen *sscreen = (struct si_screen *)screen;
 886    struct radeon_winsys *ws = sscreen->ws;
 887    unsigned vram_usage, gtt_usage;
 888
 889    info->total_device_memory = sscreen->info.vram_size / 1024;
 890    info->total_staging_memory = sscreen->info.gart_size / 1024;
 891
 892    /* The real TTM memory usage is somewhat random, because:
 893     *
 894     * 1) TTM delays freeing memory, because it can only free it after
 895     *    fences expire.
 896     *
 897     * 2) The memory usage can be really low if big VRAM evictions are
 898     *    taking place, but the real usage is well above the size of VRAM.
 899     *
 900     * Instead, return statistics of this process.
 901     */
 902    vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 903    gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 904
 905    info->avail_device_memory =
 906       vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
 907    info->avail_staging_memory =
 908       gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
 909
 910    info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 911
 912    if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 913       info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
 914    else
 915       /* Just return the number of evicted 64KB pages. */
 916       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 917 }
 918
 919 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 920 {
 921    struct si_screen *sscreen = (struct si_screen *)pscreen;
 922
 923    return sscreen->disk_shader_cache;
 924 }
 925
 926 static void si_init_renderer_string(struct si_screen *sscreen)
 927 {
 928    char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 929    struct utsname uname_data;
 930
 931    if (sscreen->info.marketing_name) {
 932       snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
 933       snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
 934    } else {
 935       snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
 936    }
 937
 938    if (uname(&uname_data) == 0)
 939       snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
 940
 941    snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 942             "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
 943             sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 944             kernel_version);
 945 }
 946
 947 void si_init_screen_get_functions(struct si_screen *sscreen)
 948 {
 949    sscreen->b.get_name = si_get_name;
 950    sscreen->b.get_vendor = si_get_vendor;
 951    sscreen->b.get_device_vendor = si_get_device_vendor;
 952    sscreen->b.get_param = si_get_param;
 953    sscreen->b.get_paramf = si_get_paramf;
 954    sscreen->b.get_compute_param = si_get_compute_param;
 955    sscreen->b.get_timestamp = si_get_timestamp;
 956    sscreen->b.get_shader_param = si_get_shader_param;
 957    sscreen->b.get_compiler_options = si_get_compiler_options;
 958    sscreen->b.get_device_uuid = si_get_device_uuid;
 959    sscreen->b.get_driver_uuid = si_get_driver_uuid;
 960    sscreen->b.query_memory_info = si_query_memory_info;
 961    sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 962
 963    if (sscreen->info.has_hw_decode) {
 964       sscreen->b.get_video_param = si_get_video_param;
 965       sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 966    } else {
 967       sscreen->b.get_video_param = si_get_video_param_no_decode;
 968       sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 969    }
 970
 971    si_init_renderer_string(sscreen);
 972 }