src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27
  28 #include "util/os_time.h"
  29
  30 /* initialize */
  31 void si_need_gfx_cs_space(struct si_context *ctx)
  32 {
  33         struct radeon_winsys_cs *cs = ctx->gfx_cs;
  34
  35         /* There is no need to flush the DMA IB here, because
  36          * r600_need_dma_space always flushes the GFX IB if there is
  37          * a conflict, which means any unflushed DMA commands automatically
  38          * precede the GFX IB (= they had no dependency on the GFX IB when
  39          * they were submitted).
  40          */
  41
  42         /* There are two memory usage counters in the winsys for all buffers
  43          * that have been added (cs_add_buffer) and two counters in the pipe
  44          * driver for those that haven't been added yet.
  45          */
  46         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  47                                                    ctx->vram, ctx->gtt))) {
  48                 ctx->gtt = 0;
  49                 ctx->vram = 0;
  50                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  51                 return;
  52         }
  53         ctx->gtt = 0;
  54         ctx->vram = 0;
  55
  56         /* If the IB is sufficiently large, don't count the space needed
  57          * and just flush if there is not enough space left.
  58          *
  59          * Also reserve space for stopping queries at the end of IB, because
  60          * the number of active queries is mostly unlimited.
  61          */
  62         unsigned need_dwords = 2048 + ctx->num_cs_dw_queries_suspend;
  63         if (!ctx->ws->cs_check_space(cs, need_dwords))
  64                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  65 }
  66
  67 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  68                      struct pipe_fence_handle **fence)
  69 {
  70         struct radeon_winsys_cs *cs = ctx->gfx_cs;
  71         struct radeon_winsys *ws = ctx->ws;
  72         unsigned wait_flags = 0;
  73
  74         if (ctx->gfx_flush_in_progress)
  75                 return;
  76
  77         if (ctx->chip_class == VI && ctx->screen->info.drm_minor <= 1) {
  78                 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
  79                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  80                               SI_CONTEXT_CS_PARTIAL_FLUSH |
  81                               SI_CONTEXT_INV_GLOBAL_L2;
  82         } else if (ctx->chip_class == SI) {
  83                 /* The kernel flushes L2 before shaders are finished. */
  84                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  85                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  86         } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
  87                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  88                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  89         }
  90
  91         /* Drop this flush if it's a no-op. */
  92         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
  93             (!wait_flags || !ctx->gfx_last_ib_is_busy))
  94                 return;
  95
  96         if (si_check_device_reset(ctx))
  97                 return;
  98
  99         if (ctx->screen->debug_flags & DBG(CHECK_VM))
 100                 flags &= ~PIPE_FLUSH_ASYNC;
 101
 102         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
 103          * responsible for flushing the DMA IB and merging the fences from both.
 104          * This code is only needed when the driver flushes the GFX IB
 105          * internally, and it never asks for a fence handle.
 106          */
 107         if (radeon_emitted(ctx->dma_cs, 0)) {
 108                 assert(fence == NULL); /* internal flushes only */
 109                 si_flush_dma_cs(ctx, flags, NULL);
 110         }
 111
 112         ctx->gfx_flush_in_progress = true;
 113
 114         if (!LIST_IS_EMPTY(&ctx->active_queries))
 115                 si_suspend_queries(ctx);
 116
 117         ctx->streamout.suspended = false;
 118         if (ctx->streamout.begin_emitted) {
 119                 si_emit_streamout_end(ctx);
 120                 ctx->streamout.suspended = true;
 121         }
 122
 123         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 124          * because the kernel doesn't wait for it. */
 125         if (ctx->chip_class >= CIK)
 126                 si_cp_dma_wait_for_idle(ctx);
 127
 128         /* Wait for draw calls to finish if needed. */
 129         if (wait_flags) {
 130                 ctx->flags |= wait_flags;
 131                 si_emit_cache_flush(ctx);
 132         }
 133         ctx->gfx_last_ib_is_busy = wait_flags == 0;
 134
 135         if (ctx->current_saved_cs) {
 136                 si_trace_emit(ctx);
 137                 si_log_hw_flush(ctx);
 138
 139                 /* Save the IB for debug contexts. */
 140                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 141                 ctx->current_saved_cs->flushed = true;
 142                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 143         }
 144
 145         /* Flush the CS. */
 146         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 147         if (fence)
 148                 ws->fence_reference(fence, ctx->last_gfx_fence);
 149
 150         /* This must be after cs_flush returns, since the context's API
 151          * thread can concurrently read this value in si_fence_finish. */
 152         ctx->num_gfx_cs_flushes++;
 153
 154         /* Check VM faults if needed. */
 155         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 156                 /* Use conservative timeout 800ms, after which we won't wait any
 157                  * longer and assume the GPU is hung.
 158                  */
 159                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 160
 161                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 162         }
 163
 164         if (ctx->current_saved_cs)
 165                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 166
 167         si_begin_new_gfx_cs(ctx);
 168         ctx->gfx_flush_in_progress = false;
 169 }
 170
 171 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 172 {
 173         static const uint32_t zeros[1];
 174         assert(!ctx->current_saved_cs);
 175
 176         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 177         if (!ctx->current_saved_cs)
 178                 return;
 179
 180         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 181
 182         ctx->current_saved_cs->trace_buf = (struct r600_resource*)
 183                                  pipe_buffer_create(ctx->b.screen, 0,
 184                                                     PIPE_USAGE_STAGING, 8);
 185         if (!ctx->current_saved_cs->trace_buf) {
 186                 free(ctx->current_saved_cs);
 187                 ctx->current_saved_cs = NULL;
 188                 return;
 189         }
 190
 191         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 192                                     0, sizeof(zeros), zeros);
 193         ctx->current_saved_cs->trace_id = 0;
 194
 195         si_trace_emit(ctx);
 196
 197         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 198                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 199 }
 200
 201 void si_begin_new_gfx_cs(struct si_context *ctx)
 202 {
 203         if (ctx->is_debug)
 204                 si_begin_gfx_cs_debug(ctx);
 205
 206         /* Always invalidate caches at the beginning of IBs, because external
 207          * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
 208          * buffers.
 209          *
 210          * Note that the cache flush done by the kernel at the end of GFX IBs
 211          * isn't useful here, because that flush can finish after the following
 212          * IB starts drawing.
 213          *
 214          * TODO: Do we also need to invalidate CB & DB caches?
 215          */
 216         ctx->flags |= SI_CONTEXT_INV_ICACHE |
 217                       SI_CONTEXT_INV_SMEM_L1 |
 218                       SI_CONTEXT_INV_VMEM_L1 |
 219                       SI_CONTEXT_INV_GLOBAL_L2 |
 220                       SI_CONTEXT_START_PIPELINE_STATS;
 221
 222         /* set all valid group as dirty so they get reemited on
 223          * next draw command
 224          */
 225         si_pm4_reset_emitted(ctx);
 226
 227         /* The CS initialization should be emitted before everything else. */
 228         si_pm4_emit(ctx, ctx->init_config);
 229         if (ctx->init_config_gs_rings)
 230                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 231
 232         if (ctx->queued.named.ls)
 233                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 234         if (ctx->queued.named.hs)
 235                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 236         if (ctx->queued.named.es)
 237                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 238         if (ctx->queued.named.gs)
 239                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 240         if (ctx->queued.named.vs)
 241                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 242         if (ctx->queued.named.ps)
 243                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 244         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 245                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 246
 247         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 248         bool has_clear_state = ctx->screen->has_clear_state;
 249         if (has_clear_state) {
 250                 ctx->framebuffer.dirty_cbufs =
 251                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 252                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 253                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 254         } else {
 255                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 256                 ctx->framebuffer.dirty_zsbuf = true;
 257         }
 258         /* This should always be marked as dirty to set the framebuffer scissor
 259          * at least. */
 260         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 261
 262         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 263         /* CLEAR_STATE sets zeros. */
 264         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 265                 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 266         ctx->msaa_sample_locs.nr_samples = 0;
 267         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 268         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 269         /* CLEAR_STATE sets 0xffff. */
 270         if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
 271                 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 272         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 273         /* CLEAR_STATE sets zeros. */
 274         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 275                 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 276         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 277         if (ctx->chip_class >= GFX9)
 278                 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
 279         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 280         si_mark_atom_dirty(ctx, &ctx->spi_map);
 281         si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
 282         si_mark_atom_dirty(ctx, &ctx->render_cond_atom);
 283         si_all_descriptors_begin_new_cs(ctx);
 284         si_all_resident_buffers_begin_new_cs(ctx);
 285
 286         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 287         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 288         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 289         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 290         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 291
 292         si_mark_atom_dirty(ctx, &ctx->scratch_state);
 293         if (ctx->scratch_buffer) {
 294                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 295         }
 296
 297         if (ctx->streamout.suspended) {
 298                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 299                 si_streamout_buffers_dirty(ctx);
 300         }
 301
 302         if (!LIST_IS_EMPTY(&ctx->active_queries))
 303                 si_resume_queries(ctx);
 304
 305         assert(!ctx->gfx_cs->prev_dw);
 306         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 307
 308         /* Invalidate various draw states so that they are emitted before
 309          * the first draw call. */
 310         si_invalidate_draw_sh_constants(ctx);
 311         ctx->last_index_size = -1;
 312         ctx->last_primitive_restart_en = -1;
 313         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 314         ctx->last_gs_out_prim = -1;
 315         ctx->last_prim = -1;
 316         ctx->last_multi_vgt_param = -1;
 317         ctx->last_rast_prim = -1;
 318         ctx->last_sc_line_stipple = ~0;
 319         ctx->last_vs_state = ~0;
 320         ctx->last_ls = NULL;
 321         ctx->last_tcs = NULL;
 322         ctx->last_tes_sh_base = -1;
 323         ctx->last_num_tcs_input_cp = -1;
 324
 325         ctx->cs_shader_state.initialized = false;
 326 }