src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27
  28 #include "util/os_time.h"
  29 #include "util/u_upload_mgr.h"
  30
  31 /* initialize */
  32 void si_need_gfx_cs_space(struct si_context *ctx)
  33 {
  34         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  35
  36         /* There is no need to flush the DMA IB here, because
  37          * si_need_dma_space always flushes the GFX IB if there is
  38          * a conflict, which means any unflushed DMA commands automatically
  39          * precede the GFX IB (= they had no dependency on the GFX IB when
  40          * they were submitted).
  41          */
  42
  43         /* There are two memory usage counters in the winsys for all buffers
  44          * that have been added (cs_add_buffer) and two counters in the pipe
  45          * driver for those that haven't been added yet.
  46          */
  47         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  48                                                    ctx->vram, ctx->gtt))) {
  49                 ctx->gtt = 0;
  50                 ctx->vram = 0;
  51                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  52                 return;
  53         }
  54         ctx->gtt = 0;
  55         ctx->vram = 0;
  56
  57         /* If the IB is sufficiently large, don't count the space needed
  58          * and just flush if there is not enough space left.
  59          *
  60          * Also reserve space for stopping queries at the end of IB, because
  61          * the number of active queries is mostly unlimited.
  62          */
  63         unsigned need_dwords = 2048 + ctx->num_cs_dw_queries_suspend;
  64         if (!ctx->ws->cs_check_space(cs, need_dwords))
  65                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  66 }
  67
  68 void si_unref_sdma_uploads(struct si_context *sctx)
  69 {
  70         for (unsigned i = 0; i < sctx->num_sdma_uploads; i++) {
  71                 si_resource_reference(&sctx->sdma_uploads[i].dst, NULL);
  72                 si_resource_reference(&sctx->sdma_uploads[i].src, NULL);
  73         }
  74         sctx->num_sdma_uploads = 0;
  75 }
  76
  77 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  78                      struct pipe_fence_handle **fence)
  79 {
  80         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  81         struct radeon_winsys *ws = ctx->ws;
  82         unsigned wait_flags = 0;
  83
  84         if (ctx->gfx_flush_in_progress)
  85                 return;
  86
  87         if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
  88                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  89                               SI_CONTEXT_CS_PARTIAL_FLUSH |
  90                               SI_CONTEXT_INV_GLOBAL_L2;
  91         } else if (ctx->chip_class == SI) {
  92                 /* The kernel flushes L2 before shaders are finished. */
  93                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  94                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  95         } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
  96                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  97                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  98         }
  99
 100         /* Drop this flush if it's a no-op. */
 101         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
 102             (!wait_flags || !ctx->gfx_last_ib_is_busy))
 103                 return;
 104
 105         if (si_check_device_reset(ctx))
 106                 return;
 107
 108         if (ctx->screen->debug_flags & DBG(CHECK_VM))
 109                 flags &= ~PIPE_FLUSH_ASYNC;
 110
 111         ctx->gfx_flush_in_progress = true;
 112
 113         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
 114          * responsible for flushing the DMA IB and merging the fences from both.
 115          * If the driver flushes the GFX IB internally, and it should never ask
 116          * for a fence handle.
 117          */
 118         assert(!radeon_emitted(ctx->dma_cs, 0) || fence == NULL);
 119
 120         /* Update the sdma_uploads list by flushing the uploader. */
 121         u_upload_unmap(ctx->b.const_uploader);
 122
 123         /* Execute SDMA uploads. */
 124         ctx->sdma_uploads_in_progress = true;
 125         for (unsigned i = 0; i < ctx->num_sdma_uploads; i++) {
 126                 struct si_sdma_upload *up = &ctx->sdma_uploads[i];
 127                 struct pipe_box box;
 128
 129                 assert(up->src_offset % 4 == 0 && up->dst_offset % 4 == 0 &&
 130                        up->size % 4 == 0);
 131
 132                 u_box_1d(up->src_offset, up->size, &box);
 133                 ctx->dma_copy(&ctx->b, &up->dst->b.b, 0, up->dst_offset, 0, 0,
 134                               &up->src->b.b, 0, &box);
 135         }
 136         ctx->sdma_uploads_in_progress = false;
 137         si_unref_sdma_uploads(ctx);
 138
 139         /* Flush SDMA (preamble IB). */
 140         if (radeon_emitted(ctx->dma_cs, 0))
 141                 si_flush_dma_cs(ctx, flags, NULL);
 142
 143         if (ctx->has_graphics) {
 144                 if (!LIST_IS_EMPTY(&ctx->active_queries))
 145                         si_suspend_queries(ctx);
 146
 147                 ctx->streamout.suspended = false;
 148                 if (ctx->streamout.begin_emitted) {
 149                         si_emit_streamout_end(ctx);
 150                         ctx->streamout.suspended = true;
 151                 }
 152         }
 153
 154         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 155          * because the kernel doesn't wait for it. */
 156         if (ctx->chip_class >= CIK)
 157                 si_cp_dma_wait_for_idle(ctx);
 158
 159         /* Wait for draw calls to finish if needed. */
 160         if (wait_flags) {
 161                 ctx->flags |= wait_flags;
 162                 si_emit_cache_flush(ctx);
 163         }
 164         ctx->gfx_last_ib_is_busy = wait_flags == 0;
 165
 166         if (ctx->current_saved_cs) {
 167                 si_trace_emit(ctx);
 168
 169                 /* Save the IB for debug contexts. */
 170                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 171                 ctx->current_saved_cs->flushed = true;
 172                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 173
 174                 si_log_hw_flush(ctx);
 175         }
 176
 177         /* Flush the CS. */
 178         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 179         if (fence)
 180                 ws->fence_reference(fence, ctx->last_gfx_fence);
 181
 182         ctx->num_gfx_cs_flushes++;
 183
 184         /* Check VM faults if needed. */
 185         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 186                 /* Use conservative timeout 800ms, after which we won't wait any
 187                  * longer and assume the GPU is hung.
 188                  */
 189                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 190
 191                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 192         }
 193
 194         if (ctx->current_saved_cs)
 195                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 196
 197         si_begin_new_gfx_cs(ctx);
 198         ctx->gfx_flush_in_progress = false;
 199 }
 200
 201 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 202 {
 203         static const uint32_t zeros[1];
 204         assert(!ctx->current_saved_cs);
 205
 206         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 207         if (!ctx->current_saved_cs)
 208                 return;
 209
 210         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 211
 212         ctx->current_saved_cs->trace_buf = si_resource(
 213                 pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
 214         if (!ctx->current_saved_cs->trace_buf) {
 215                 free(ctx->current_saved_cs);
 216                 ctx->current_saved_cs = NULL;
 217                 return;
 218         }
 219
 220         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 221                                     0, sizeof(zeros), zeros);
 222         ctx->current_saved_cs->trace_id = 0;
 223
 224         si_trace_emit(ctx);
 225
 226         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 227                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 228 }
 229
 230 void si_begin_new_gfx_cs(struct si_context *ctx)
 231 {
 232         if (ctx->is_debug)
 233                 si_begin_gfx_cs_debug(ctx);
 234
 235         /* Always invalidate caches at the beginning of IBs, because external
 236          * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
 237          * buffers.
 238          *
 239          * Note that the cache flush done by the kernel at the end of GFX IBs
 240          * isn't useful here, because that flush can finish after the following
 241          * IB starts drawing.
 242          *
 243          * TODO: Do we also need to invalidate CB & DB caches?
 244          */
 245         ctx->flags |= SI_CONTEXT_INV_ICACHE |
 246                       SI_CONTEXT_INV_SMEM_L1 |
 247                       SI_CONTEXT_INV_VMEM_L1 |
 248                       SI_CONTEXT_INV_GLOBAL_L2 |
 249                       SI_CONTEXT_START_PIPELINE_STATS;
 250
 251         ctx->cs_shader_state.initialized = false;
 252         si_all_descriptors_begin_new_cs(ctx);
 253         si_all_resident_buffers_begin_new_cs(ctx);
 254
 255         if (!ctx->has_graphics) {
 256                 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 257                 return;
 258         }
 259
 260         /* set all valid group as dirty so they get reemited on
 261          * next draw command
 262          */
 263         si_pm4_reset_emitted(ctx);
 264
 265         /* The CS initialization should be emitted before everything else. */
 266         si_pm4_emit(ctx, ctx->init_config);
 267         if (ctx->init_config_gs_rings)
 268                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 269
 270         if (ctx->queued.named.ls)
 271                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 272         if (ctx->queued.named.hs)
 273                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 274         if (ctx->queued.named.es)
 275                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 276         if (ctx->queued.named.gs)
 277                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 278         if (ctx->queued.named.vs)
 279                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 280         if (ctx->queued.named.ps)
 281                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 282         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 283                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 284
 285         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 286         bool has_clear_state = ctx->screen->has_clear_state;
 287         if (has_clear_state) {
 288                 ctx->framebuffer.dirty_cbufs =
 289                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 290                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 291                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 292         } else {
 293                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 294                 ctx->framebuffer.dirty_zsbuf = true;
 295         }
 296         /* This should always be marked as dirty to set the framebuffer scissor
 297          * at least. */
 298         si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
 299
 300         si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
 301         /* CLEAR_STATE sets zeros. */
 302         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 303                 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
 304         ctx->sample_locs_num_samples = 0;
 305         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
 306         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
 307         /* CLEAR_STATE sets 0xffff. */
 308         if (!has_clear_state || ctx->sample_mask != 0xffff)
 309                 si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
 310         si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
 311         /* CLEAR_STATE sets zeros. */
 312         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 313                 si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
 314         si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
 315         if (ctx->chip_class >= GFX9)
 316                 si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
 317         si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
 318         si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
 319         si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
 320         si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
 321         /* CLEAR_STATE disables all window rectangles. */
 322         if (!has_clear_state || ctx->num_window_rectangles > 0)
 323                 si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
 324
 325         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 326         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 327         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 328         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 329         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 330         si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 331
 332         si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
 333         if (ctx->scratch_buffer) {
 334                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 335         }
 336
 337         if (ctx->streamout.suspended) {
 338                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 339                 si_streamout_buffers_dirty(ctx);
 340         }
 341
 342         if (!LIST_IS_EMPTY(&ctx->active_queries))
 343                 si_resume_queries(ctx);
 344
 345         assert(!ctx->gfx_cs->prev_dw);
 346         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 347
 348         /* Invalidate various draw states so that they are emitted before
 349          * the first draw call. */
 350         si_invalidate_draw_sh_constants(ctx);
 351         ctx->last_index_size = -1;
 352         ctx->last_primitive_restart_en = -1;
 353         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 354         ctx->last_prim = -1;
 355         ctx->last_multi_vgt_param = -1;
 356         ctx->last_rast_prim = -1;
 357         ctx->last_sc_line_stipple = ~0;
 358         ctx->last_vs_state = ~0;
 359         ctx->last_ls = NULL;
 360         ctx->last_tcs = NULL;
 361         ctx->last_tes_sh_base = -1;
 362         ctx->last_num_tcs_input_cp = -1;
 363         ctx->last_ls_hs_config = -1; /* impossible value */
 364
 365         if (has_clear_state) {
 366                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
 367                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
 368                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
 369                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
 370                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
 371                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
 372                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
 373                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
 374                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
 375                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
 376                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
 377                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
 378                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
 379                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
 380                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
 381                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
 382                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
 383                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
 384                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
 385                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ]  = 0x3f800000;
 386                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ]  = 0x3f800000;
 387                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ]  = 0x3f800000;
 388                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ]  = 0x3f800000;
 389                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
 390                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
 391                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE]     = 0xffff;
 392                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE]  = 0x00000000;
 393                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1]  = 0x00000000;
 394                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2]  = 0x00000000;
 395                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3]  = 0x00000000;
 396                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_OUT_PRIM_TYPE]    = 0x00000000;
 397                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE]  = 0x00000000;
 398                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT]  = 0x00000000;
 399                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE]  = 0x00000000;
 400                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1]  = 0x00000000;
 401                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2]  = 0x00000000;
 402                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3]  = 0x00000000;
 403                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT]  = 0x00000000;
 404                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL]  = 0x00000000;
 405                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP]  = 0x00000000;
 406                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE]  = 0x00000000;
 407                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
 408                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
 409                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
 410                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
 411                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
 412                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA]  = 0x00000000;
 413                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR]  = 0x00000000;
 414                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL]  = 0x00000000;
 415                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL]  = 0x00000002;
 416                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT]  = 0x00000000;
 417                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]  = 0x00000000;
 418                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 0xffffffff;
 419                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
 420                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 0x0000001e; /* From VI */
 421
 422                 /* Set all saved registers state to saved. */
 423                 ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
 424         } else {
 425                 /* Set all saved registers state to unknown. */
 426                 ctx->tracked_regs.reg_saved = 0;
 427         }
 428
 429         /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
 430         memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
 431 }