2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_build_pm4.h"
29 #include "util/os_time.h"
30 #include "util/u_upload_mgr.h"
33 void si_need_gfx_cs_space(struct si_context
*ctx
)
35 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
37 /* There is no need to flush the DMA IB here, because
38 * si_need_dma_space always flushes the GFX IB if there is
39 * a conflict, which means any unflushed DMA commands automatically
40 * precede the GFX IB (= they had no dependency on the GFX IB when
41 * they were submitted).
44 /* There are two memory usage counters in the winsys for all buffers
45 * that have been added (cs_add_buffer) and two counters in the pipe
46 * driver for those that haven't been added yet.
48 if (unlikely(!radeon_cs_memory_below_limit(ctx
->screen
, ctx
->gfx_cs
, ctx
->vram
, ctx
->gtt
))) {
51 si_flush_gfx_cs(ctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
57 unsigned need_dwords
= si_get_minimum_num_gfx_cs_dwords(ctx
);
58 if (!ctx
->ws
->cs_check_space(cs
, need_dwords
, false))
59 si_flush_gfx_cs(ctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
62 void si_unref_sdma_uploads(struct si_context
*sctx
)
64 for (unsigned i
= 0; i
< sctx
->num_sdma_uploads
; i
++) {
65 si_resource_reference(&sctx
->sdma_uploads
[i
].dst
, NULL
);
66 si_resource_reference(&sctx
->sdma_uploads
[i
].src
, NULL
);
68 sctx
->num_sdma_uploads
= 0;
71 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
, struct pipe_fence_handle
**fence
)
73 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
74 struct radeon_winsys
*ws
= ctx
->ws
;
75 const unsigned wait_ps_cs
= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
76 unsigned wait_flags
= 0;
78 if (ctx
->gfx_flush_in_progress
)
81 /* The amdgpu kernel driver always synchronizes execution for shared DMABUFs
82 * between processes, so we don't have to wait at the end of IBs to make sure
85 * The amdgpu winsys synchronizes execution for buffers shared by different
86 * contexts within the same process.
88 * Interop with AMDVLK, RADV, or OpenCL within the same process requires
89 * explicit fences or glFinish.
91 if (ctx
->screen
->info
.is_amdgpu
)
92 flags
|= RADEON_FLUSH_START_NEXT_GFX_IB_NOW
;
94 if (!ctx
->screen
->info
.kernel_flushes_tc_l2_after_ib
) {
95 wait_flags
|= wait_ps_cs
| SI_CONTEXT_INV_L2
;
96 } else if (ctx
->chip_class
== GFX6
) {
97 /* The kernel flushes L2 before shaders are finished. */
98 wait_flags
|= wait_ps_cs
;
99 } else if (!(flags
& RADEON_FLUSH_START_NEXT_GFX_IB_NOW
)) {
100 wait_flags
|= wait_ps_cs
;
103 /* Drop this flush if it's a no-op. */
104 if (!radeon_emitted(cs
, ctx
->initial_gfx_cs_size
) && (!wait_flags
|| !ctx
->gfx_last_ib_is_busy
))
107 if (ctx
->b
.get_device_reset_status(&ctx
->b
) != PIPE_NO_RESET
)
110 if (ctx
->screen
->debug_flags
& DBG(CHECK_VM
))
111 flags
&= ~PIPE_FLUSH_ASYNC
;
113 ctx
->gfx_flush_in_progress
= true;
115 /* If the gallium frontend is flushing the GFX IB, si_flush_from_st is
116 * responsible for flushing the DMA IB and merging the fences from both.
117 * If the driver flushes the GFX IB internally, and it should never ask
118 * for a fence handle.
120 assert(!radeon_emitted(ctx
->sdma_cs
, 0) || fence
== NULL
);
122 /* Update the sdma_uploads list by flushing the uploader. */
123 u_upload_unmap(ctx
->b
.const_uploader
);
125 /* Execute SDMA uploads. */
126 ctx
->sdma_uploads_in_progress
= true;
127 for (unsigned i
= 0; i
< ctx
->num_sdma_uploads
; i
++) {
128 struct si_sdma_upload
*up
= &ctx
->sdma_uploads
[i
];
130 assert(up
->src_offset
% 4 == 0 && up
->dst_offset
% 4 == 0 && up
->size
% 4 == 0);
132 si_sdma_copy_buffer(ctx
, &up
->dst
->b
.b
, &up
->src
->b
.b
, up
->dst_offset
, up
->src_offset
,
135 ctx
->sdma_uploads_in_progress
= false;
136 si_unref_sdma_uploads(ctx
);
138 /* Flush SDMA (preamble IB). */
139 if (radeon_emitted(ctx
->sdma_cs
, 0))
140 si_flush_dma_cs(ctx
, flags
, NULL
);
142 if (radeon_emitted(ctx
->prim_discard_compute_cs
, 0)) {
143 struct radeon_cmdbuf
*compute_cs
= ctx
->prim_discard_compute_cs
;
144 si_compute_signal_gfx(ctx
);
146 /* Make sure compute shaders are idle before leaving the IB, so that
147 * the next IB doesn't overwrite GDS that might be in use. */
148 radeon_emit(compute_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
149 radeon_emit(compute_cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
151 /* Save the GDS prim restart counter if needed. */
152 if (ctx
->preserve_prim_restart_gds_at_flush
) {
153 si_cp_copy_data(ctx
, compute_cs
, COPY_DATA_DST_MEM
, ctx
->wait_mem_scratch
, 4,
154 COPY_DATA_GDS
, NULL
, 4);
158 if (ctx
->has_graphics
) {
159 if (!list_is_empty(&ctx
->active_queries
))
160 si_suspend_queries(ctx
);
162 ctx
->streamout
.suspended
= false;
163 if (ctx
->streamout
.begin_emitted
) {
164 si_emit_streamout_end(ctx
);
165 ctx
->streamout
.suspended
= true;
167 /* Since NGG streamout uses GDS, we need to make GDS
168 * idle when we leave the IB, otherwise another process
169 * might overwrite it while our shaders are busy.
171 if (ctx
->screen
->use_ngg_streamout
)
172 wait_flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
176 /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
177 * because the kernel doesn't wait for it. */
178 if (ctx
->chip_class
>= GFX7
)
179 si_cp_dma_wait_for_idle(ctx
);
181 /* Wait for draw calls to finish if needed. */
183 ctx
->flags
|= wait_flags
;
184 ctx
->emit_cache_flush(ctx
);
186 ctx
->gfx_last_ib_is_busy
= (wait_flags
& wait_ps_cs
) != wait_ps_cs
;
188 if (ctx
->current_saved_cs
) {
191 /* Save the IB for debug contexts. */
192 si_save_cs(ws
, cs
, &ctx
->current_saved_cs
->gfx
, true);
193 ctx
->current_saved_cs
->flushed
= true;
194 ctx
->current_saved_cs
->time_flush
= os_time_get_nano();
196 si_log_hw_flush(ctx
);
199 if (si_compute_prim_discard_enabled(ctx
)) {
200 /* The compute IB can start after the previous gfx IB starts. */
201 if (radeon_emitted(ctx
->prim_discard_compute_cs
, 0) && ctx
->last_gfx_fence
) {
202 ctx
->ws
->cs_add_fence_dependency(
203 ctx
->gfx_cs
, ctx
->last_gfx_fence
,
204 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
| RADEON_DEPENDENCY_START_FENCE
);
207 /* Remember the last execution barrier. It's in the IB.
208 * It will signal the start of the next compute IB.
210 if (flags
& RADEON_FLUSH_START_NEXT_GFX_IB_NOW
&& ctx
->last_pkt3_write_data
) {
211 *ctx
->last_pkt3_write_data
= PKT3(PKT3_WRITE_DATA
, 3, 0);
212 ctx
->last_pkt3_write_data
= NULL
;
214 si_resource_reference(&ctx
->last_ib_barrier_buf
, ctx
->barrier_buf
);
215 ctx
->last_ib_barrier_buf_offset
= ctx
->barrier_buf_offset
;
216 si_resource_reference(&ctx
->barrier_buf
, NULL
);
218 ws
->fence_reference(&ctx
->last_ib_barrier_fence
, NULL
);
223 ws
->cs_flush(cs
, flags
, &ctx
->last_gfx_fence
);
225 ws
->fence_reference(fence
, ctx
->last_gfx_fence
);
227 ctx
->num_gfx_cs_flushes
++;
229 if (si_compute_prim_discard_enabled(ctx
)) {
230 /* Remember the last execution barrier, which is the last fence
233 if (!(flags
& RADEON_FLUSH_START_NEXT_GFX_IB_NOW
)) {
234 ctx
->last_pkt3_write_data
= NULL
;
235 si_resource_reference(&ctx
->last_ib_barrier_buf
, NULL
);
236 ws
->fence_reference(&ctx
->last_ib_barrier_fence
, ctx
->last_gfx_fence
);
240 /* Check VM faults if needed. */
241 if (ctx
->screen
->debug_flags
& DBG(CHECK_VM
)) {
242 /* Use conservative timeout 800ms, after which we won't wait any
243 * longer and assume the GPU is hung.
245 ctx
->ws
->fence_wait(ctx
->ws
, ctx
->last_gfx_fence
, 800 * 1000 * 1000);
247 si_check_vm_faults(ctx
, &ctx
->current_saved_cs
->gfx
, RING_GFX
);
250 if (ctx
->current_saved_cs
)
251 si_saved_cs_reference(&ctx
->current_saved_cs
, NULL
);
253 si_begin_new_gfx_cs(ctx
);
254 ctx
->gfx_flush_in_progress
= false;
257 static void si_begin_gfx_cs_debug(struct si_context
*ctx
)
259 static const uint32_t zeros
[1];
260 assert(!ctx
->current_saved_cs
);
262 ctx
->current_saved_cs
= calloc(1, sizeof(*ctx
->current_saved_cs
));
263 if (!ctx
->current_saved_cs
)
266 pipe_reference_init(&ctx
->current_saved_cs
->reference
, 1);
268 ctx
->current_saved_cs
->trace_buf
=
269 si_resource(pipe_buffer_create(ctx
->b
.screen
, 0, PIPE_USAGE_STAGING
, 8));
270 if (!ctx
->current_saved_cs
->trace_buf
) {
271 free(ctx
->current_saved_cs
);
272 ctx
->current_saved_cs
= NULL
;
276 pipe_buffer_write_nooverlap(&ctx
->b
, &ctx
->current_saved_cs
->trace_buf
->b
.b
, 0, sizeof(zeros
),
278 ctx
->current_saved_cs
->trace_id
= 0;
282 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, ctx
->current_saved_cs
->trace_buf
,
283 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
286 static void si_add_gds_to_buffer_list(struct si_context
*sctx
)
289 sctx
->ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds
, RADEON_USAGE_READWRITE
, 0, 0);
291 sctx
->ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds_oa
, RADEON_USAGE_READWRITE
, 0, 0);
296 void si_allocate_gds(struct si_context
*sctx
)
298 struct radeon_winsys
*ws
= sctx
->ws
;
303 assert(sctx
->screen
->use_ngg_streamout
);
305 /* 4 streamout GDS counters.
306 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
308 sctx
->gds
= ws
->buffer_create(ws
, 256, 4, RADEON_DOMAIN_GDS
, 0);
309 sctx
->gds_oa
= ws
->buffer_create(ws
, 4, 1, RADEON_DOMAIN_OA
, 0);
311 assert(sctx
->gds
&& sctx
->gds_oa
);
312 si_add_gds_to_buffer_list(sctx
);
315 void si_begin_new_gfx_cs(struct si_context
*ctx
)
318 si_begin_gfx_cs_debug(ctx
);
320 si_add_gds_to_buffer_list(ctx
);
322 /* Always invalidate caches at the beginning of IBs, because external
323 * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
326 * Note that the cache flush done by the kernel at the end of GFX IBs
327 * isn't useful here, because that flush can finish after the following
330 * TODO: Do we also need to invalidate CB & DB caches?
332 ctx
->flags
|= SI_CONTEXT_INV_ICACHE
| SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
|
333 SI_CONTEXT_INV_L2
| SI_CONTEXT_START_PIPELINE_STATS
;
335 ctx
->cs_shader_state
.initialized
= false;
336 si_all_descriptors_begin_new_cs(ctx
);
338 if (!ctx
->has_graphics
) {
339 ctx
->initial_gfx_cs_size
= ctx
->gfx_cs
->current
.cdw
;
343 /* set all valid group as dirty so they get reemited on
346 si_pm4_reset_emitted(ctx
);
348 /* The CS initialization should be emitted before everything else. */
349 si_pm4_emit(ctx
, ctx
->init_config
);
350 if (ctx
->init_config_gs_rings
)
351 si_pm4_emit(ctx
, ctx
->init_config_gs_rings
);
353 if (ctx
->queued
.named
.ls
)
354 ctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
355 if (ctx
->queued
.named
.hs
)
356 ctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
357 if (ctx
->queued
.named
.es
)
358 ctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
359 if (ctx
->queued
.named
.gs
)
360 ctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
361 if (ctx
->queued
.named
.vs
)
362 ctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
363 if (ctx
->queued
.named
.ps
)
364 ctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
365 if (ctx
->vb_descriptors_buffer
&& ctx
->vertex_elements
)
366 ctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
368 /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
369 bool has_clear_state
= ctx
->screen
->info
.has_clear_state
;
370 if (has_clear_state
) {
371 ctx
->framebuffer
.dirty_cbufs
= u_bit_consecutive(0, ctx
->framebuffer
.state
.nr_cbufs
);
372 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
373 ctx
->framebuffer
.dirty_zsbuf
= ctx
->framebuffer
.state
.zsbuf
!= NULL
;
375 ctx
->framebuffer
.dirty_cbufs
= u_bit_consecutive(0, 8);
376 ctx
->framebuffer
.dirty_zsbuf
= true;
378 /* This should always be marked as dirty to set the framebuffer scissor
380 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.framebuffer
);
382 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.clip_regs
);
383 /* CLEAR_STATE sets zeros. */
384 if (!has_clear_state
|| ctx
->clip_state
.any_nonzeros
)
385 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.clip_state
);
386 ctx
->sample_locs_num_samples
= 0;
387 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.msaa_sample_locs
);
388 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.msaa_config
);
389 /* CLEAR_STATE sets 0xffff. */
390 if (!has_clear_state
|| ctx
->sample_mask
!= 0xffff)
391 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.sample_mask
);
392 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.cb_render_state
);
393 /* CLEAR_STATE sets zeros. */
394 if (!has_clear_state
|| ctx
->blend_color
.any_nonzeros
)
395 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.blend_color
);
396 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.db_render_state
);
397 if (ctx
->chip_class
>= GFX9
)
398 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.dpbb_state
);
399 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.stencil_ref
);
400 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.spi_map
);
401 if (!ctx
->screen
->use_ngg_streamout
)
402 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.streamout_enable
);
403 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.render_cond
);
404 /* CLEAR_STATE disables all window rectangles. */
405 if (!has_clear_state
|| ctx
->num_window_rectangles
> 0)
406 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.window_rectangles
);
408 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
409 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
410 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
412 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scratch_state
);
413 if (ctx
->scratch_buffer
) {
414 si_context_add_resource_size(ctx
, &ctx
->scratch_buffer
->b
.b
);
417 if (ctx
->streamout
.suspended
) {
418 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
419 si_streamout_buffers_dirty(ctx
);
422 if (!list_is_empty(&ctx
->active_queries
))
423 si_resume_queries(ctx
);
425 assert(!ctx
->gfx_cs
->prev_dw
);
426 ctx
->initial_gfx_cs_size
= ctx
->gfx_cs
->current
.cdw
;
428 /* Invalidate various draw states so that they are emitted before
429 * the first draw call. */
430 si_invalidate_draw_sh_constants(ctx
);
431 ctx
->last_index_size
= -1;
432 ctx
->last_primitive_restart_en
= -1;
433 ctx
->last_restart_index
= SI_RESTART_INDEX_UNKNOWN
;
435 ctx
->last_multi_vgt_param
= -1;
436 ctx
->last_vs_state
= ~0;
438 ctx
->last_tcs
= NULL
;
439 ctx
->last_tes_sh_base
= -1;
440 ctx
->last_num_tcs_input_cp
= -1;
441 ctx
->last_ls_hs_config
= -1; /* impossible value */
442 ctx
->last_binning_enabled
= -1;
443 ctx
->small_prim_cull_info_dirty
= ctx
->small_prim_cull_info_buf
!= NULL
;
445 ctx
->prim_discard_compute_ib_initialized
= false;
447 /* Compute-based primitive discard:
448 * The index ring is divided into 2 halves. Switch between the halves
449 * in the same fashion as doublebuffering.
451 if (ctx
->index_ring_base
)
452 ctx
->index_ring_base
= 0;
454 ctx
->index_ring_base
= ctx
->index_ring_size_per_ib
;
456 ctx
->index_ring_offset
= 0;
458 STATIC_ASSERT(SI_NUM_TRACKED_REGS
<= sizeof(ctx
->tracked_regs
.reg_saved
) * 8);
460 if (has_clear_state
) {
461 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_RENDER_CONTROL
] = 0x00000000;
462 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_COUNT_CONTROL
] = 0x00000000;
463 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_RENDER_OVERRIDE2
] = 0x00000000;
464 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_SHADER_CONTROL
] = 0x00000000;
465 ctx
->tracked_regs
.reg_value
[SI_TRACKED_CB_TARGET_MASK
] = 0xffffffff;
466 ctx
->tracked_regs
.reg_value
[SI_TRACKED_CB_DCC_CONTROL
] = 0x00000000;
467 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SX_PS_DOWNCONVERT
] = 0x00000000;
468 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SX_BLEND_OPT_EPSILON
] = 0x00000000;
469 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SX_BLEND_OPT_CONTROL
] = 0x00000000;
470 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_LINE_CNTL
] = 0x00001000;
471 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_AA_CONFIG
] = 0x00000000;
472 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_EQAA
] = 0x00000000;
473 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_MODE_CNTL_1
] = 0x00000000;
474 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
] = 0;
475 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
] = 0x00000000;
476 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
] = 0x00000000;
477 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
] = 0x00000000;
478 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_CLIP_CNTL
] = 0x00090000;
479 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_BINNER_CNTL_0
] = 0x00000003;
480 ctx
->tracked_regs
.reg_value
[SI_TRACKED_DB_DFSM_CONTROL
] = 0x00000000;
481 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ
] = 0x3f800000;
482 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ
] = 0x3f800000;
483 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3f800000;
484 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ
] = 0x3f800000;
485 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET
] = 0;
486 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SU_VTX_CNTL
] = 0x00000005;
487 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_CLIPRECT_RULE
] = 0xffff;
488 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_SC_LINE_STIPPLE
] = 0;
489 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
] = 0x00000000;
490 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GSVS_RING_OFFSET_1
] = 0x00000000;
491 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GSVS_RING_OFFSET_2
] = 0x00000000;
492 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GSVS_RING_OFFSET_3
] = 0x00000000;
493 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
] = 0x00000000;
494 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_MAX_VERT_OUT
] = 0x00000000;
495 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_VERT_ITEMSIZE
] = 0x00000000;
496 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1
] = 0x00000000;
497 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2
] = 0x00000000;
498 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3
] = 0x00000000;
499 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_INSTANCE_CNT
] = 0x00000000;
500 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_ONCHIP_CNTL
] = 0x00000000;
501 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
] = 0x00000000;
502 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_GS_MODE
] = 0x00000000;
503 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_PRIMITIVEID_EN
] = 0x00000000;
504 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_REUSE_OFF
] = 0x00000000;
505 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_VS_OUT_CONFIG
] = 0x00000000;
506 ctx
->tracked_regs
.reg_value
[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
] = 0x00000000;
507 ctx
->tracked_regs
.reg_value
[SI_TRACKED_GE_NGG_SUBGRP_CNTL
] = 0x00000000;
508 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_SHADER_IDX_FORMAT
] = 0x00000000;
509 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_SHADER_POS_FORMAT
] = 0x00000000;
510 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_VTE_CNTL
] = 0x00000000;
511 ctx
->tracked_regs
.reg_value
[SI_TRACKED_PA_CL_NGG_CNTL
] = 0x00000000;
512 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_PS_INPUT_ENA
] = 0x00000000;
513 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_PS_INPUT_ADDR
] = 0x00000000;
514 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_BARYC_CNTL
] = 0x00000000;
515 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_PS_IN_CONTROL
] = 0x00000002;
516 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_SHADER_Z_FORMAT
] = 0x00000000;
517 ctx
->tracked_regs
.reg_value
[SI_TRACKED_SPI_SHADER_COL_FORMAT
] = 0x00000000;
518 ctx
->tracked_regs
.reg_value
[SI_TRACKED_CB_SHADER_MASK
] = 0xffffffff;
519 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_TF_PARAM
] = 0x00000000;
520 ctx
->tracked_regs
.reg_value
[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
] =
521 0x0000001e; /* From GFX8 */
523 /* Set all cleared context registers to saved. */
524 ctx
->tracked_regs
.reg_saved
= ~(1ull << SI_TRACKED_GE_PC_ALLOC
); /* uconfig reg */
525 ctx
->last_gs_out_prim
= 0; /* cleared by CLEAR_STATE */
527 /* Set all register values to unknown. */
528 ctx
->tracked_regs
.reg_saved
= 0;
529 ctx
->last_gs_out_prim
= -1; /* unknown */
532 /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
533 memset(ctx
->tracked_regs
.spi_ps_input_cntl
, 0xff, sizeof(uint32_t) * 32);