2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "radeon/r600_cs.h"
27 #include "util/os_time.h"
29 void si_destroy_saved_cs(struct si_saved_cs
*scs
)
31 si_clear_saved_cs(&scs
->gfx
);
32 r600_resource_reference(&scs
->trace_buf
, NULL
);
37 void si_need_cs_space(struct si_context
*ctx
)
39 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
41 /* There is no need to flush the DMA IB here, because
42 * r600_need_dma_space always flushes the GFX IB if there is
43 * a conflict, which means any unflushed DMA commands automatically
44 * precede the GFX IB (= they had no dependency on the GFX IB when
45 * they were submitted).
48 /* There are two memory usage counters in the winsys for all buffers
49 * that have been added (cs_add_buffer) and two counters in the pipe
50 * driver for those that haven't been added yet.
52 if (unlikely(!radeon_cs_memory_below_limit(ctx
->b
.screen
, ctx
->b
.gfx
.cs
,
53 ctx
->b
.vram
, ctx
->b
.gtt
))) {
56 ctx
->b
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
62 /* If the CS is sufficiently large, don't count the space needed
63 * and just flush if there is not enough space left.
65 if (!ctx
->b
.ws
->cs_check_space(cs
, 2048))
66 ctx
->b
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
69 void si_context_gfx_flush(void *context
, unsigned flags
,
70 struct pipe_fence_handle
**fence
)
72 struct si_context
*ctx
= context
;
73 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
74 struct radeon_winsys
*ws
= ctx
->b
.ws
;
76 if (ctx
->gfx_flush_in_progress
)
79 if (!radeon_emitted(cs
, ctx
->b
.initial_gfx_cs_size
))
82 if (si_check_device_reset(&ctx
->b
))
85 if (ctx
->screen
->b
.debug_flags
& DBG(CHECK_VM
))
86 flags
&= ~RADEON_FLUSH_ASYNC
;
88 /* If the state tracker is flushing the GFX IB, r600_flush_from_st is
89 * responsible for flushing the DMA IB and merging the fences from both.
90 * This code is only needed when the driver flushes the GFX IB
91 * internally, and it never asks for a fence handle.
93 if (radeon_emitted(ctx
->b
.dma
.cs
, 0)) {
94 assert(fence
== NULL
); /* internal flushes only */
95 ctx
->b
.dma
.flush(ctx
, flags
, NULL
);
98 ctx
->gfx_flush_in_progress
= true;
100 si_preflush_suspend_features(&ctx
->b
);
102 ctx
->streamout
.suspended
= false;
103 if (ctx
->streamout
.begin_emitted
) {
104 si_emit_streamout_end(ctx
);
105 ctx
->streamout
.suspended
= true;
108 ctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
|
109 SI_CONTEXT_PS_PARTIAL_FLUSH
;
111 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
112 if (ctx
->b
.chip_class
== VI
&& ctx
->b
.screen
->info
.drm_minor
<= 1)
113 ctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
|
114 SI_CONTEXT_INV_VMEM_L1
;
116 si_emit_cache_flush(ctx
);
118 if (ctx
->current_saved_cs
) {
120 si_log_hw_flush(ctx
);
122 /* Save the IB for debug contexts. */
123 si_save_cs(ws
, cs
, &ctx
->current_saved_cs
->gfx
, true);
124 ctx
->current_saved_cs
->flushed
= true;
125 ctx
->current_saved_cs
->time_flush
= os_time_get_nano();
129 ws
->cs_flush(cs
, flags
, &ctx
->b
.last_gfx_fence
);
131 ws
->fence_reference(fence
, ctx
->b
.last_gfx_fence
);
132 ctx
->b
.num_gfx_cs_flushes
++;
134 /* Check VM faults if needed. */
135 if (ctx
->screen
->b
.debug_flags
& DBG(CHECK_VM
)) {
136 /* Use conservative timeout 800ms, after which we won't wait any
137 * longer and assume the GPU is hung.
139 ctx
->b
.ws
->fence_wait(ctx
->b
.ws
, ctx
->b
.last_gfx_fence
, 800*1000*1000);
141 si_check_vm_faults(&ctx
->b
, &ctx
->current_saved_cs
->gfx
, RING_GFX
);
144 if (ctx
->current_saved_cs
)
145 si_saved_cs_reference(&ctx
->current_saved_cs
, NULL
);
147 si_begin_new_cs(ctx
);
148 ctx
->gfx_flush_in_progress
= false;
151 static void si_begin_cs_debug(struct si_context
*ctx
)
153 static const uint32_t zeros
[1];
154 assert(!ctx
->current_saved_cs
);
156 ctx
->current_saved_cs
= calloc(1, sizeof(*ctx
->current_saved_cs
));
157 if (!ctx
->current_saved_cs
)
160 pipe_reference_init(&ctx
->current_saved_cs
->reference
, 1);
162 ctx
->current_saved_cs
->trace_buf
= (struct r600_resource
*)
163 pipe_buffer_create(ctx
->b
.b
.screen
, 0,
164 PIPE_USAGE_STAGING
, 8);
165 if (!ctx
->current_saved_cs
->trace_buf
) {
166 free(ctx
->current_saved_cs
);
167 ctx
->current_saved_cs
= NULL
;
171 pipe_buffer_write_nooverlap(&ctx
->b
.b
, &ctx
->current_saved_cs
->trace_buf
->b
.b
,
172 0, sizeof(zeros
), zeros
);
173 ctx
->current_saved_cs
->trace_id
= 0;
177 radeon_add_to_buffer_list(&ctx
->b
, &ctx
->b
.gfx
, ctx
->current_saved_cs
->trace_buf
,
178 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
181 void si_begin_new_cs(struct si_context
*ctx
)
184 si_begin_cs_debug(ctx
);
186 /* Flush read caches at the beginning of CS not flushed by the kernel. */
187 if (ctx
->b
.chip_class
>= CIK
)
188 ctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
189 SI_CONTEXT_INV_ICACHE
;
191 ctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
193 /* set all valid group as dirty so they get reemited on
196 si_pm4_reset_emitted(ctx
);
198 /* The CS initialization should be emitted before everything else. */
199 si_pm4_emit(ctx
, ctx
->init_config
);
200 if (ctx
->init_config_gs_rings
)
201 si_pm4_emit(ctx
, ctx
->init_config_gs_rings
);
203 if (ctx
->queued
.named
.ls
)
204 ctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
205 if (ctx
->queued
.named
.hs
)
206 ctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
207 if (ctx
->queued
.named
.es
)
208 ctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
209 if (ctx
->queued
.named
.gs
)
210 ctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
211 if (ctx
->queued
.named
.vs
)
212 ctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
213 if (ctx
->queued
.named
.ps
)
214 ctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
215 if (ctx
->vertex_buffers
.buffer
&& ctx
->vertex_elements
)
216 ctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
218 /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
219 bool has_clear_state
= ctx
->screen
->has_clear_state
;
220 if (has_clear_state
) {
221 ctx
->framebuffer
.dirty_cbufs
=
222 u_bit_consecutive(0, ctx
->framebuffer
.state
.nr_cbufs
);
223 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
224 ctx
->framebuffer
.dirty_zsbuf
= ctx
->framebuffer
.state
.zsbuf
!= NULL
;
226 ctx
->framebuffer
.dirty_cbufs
= u_bit_consecutive(0, 8);
227 ctx
->framebuffer
.dirty_zsbuf
= true;
229 /* This should always be marked as dirty to set the framebuffer scissor
231 si_mark_atom_dirty(ctx
, &ctx
->framebuffer
.atom
);
233 si_mark_atom_dirty(ctx
, &ctx
->clip_regs
);
234 /* CLEAR_STATE sets zeros. */
235 if (!has_clear_state
|| ctx
->clip_state
.any_nonzeros
)
236 si_mark_atom_dirty(ctx
, &ctx
->clip_state
.atom
);
237 ctx
->msaa_sample_locs
.nr_samples
= 0;
238 si_mark_atom_dirty(ctx
, &ctx
->msaa_sample_locs
.atom
);
239 si_mark_atom_dirty(ctx
, &ctx
->msaa_config
);
240 /* CLEAR_STATE sets 0xffff. */
241 if (!has_clear_state
|| ctx
->sample_mask
.sample_mask
!= 0xffff)
242 si_mark_atom_dirty(ctx
, &ctx
->sample_mask
.atom
);
243 si_mark_atom_dirty(ctx
, &ctx
->cb_render_state
);
244 /* CLEAR_STATE sets zeros. */
245 if (!has_clear_state
|| ctx
->blend_color
.any_nonzeros
)
246 si_mark_atom_dirty(ctx
, &ctx
->blend_color
.atom
);
247 si_mark_atom_dirty(ctx
, &ctx
->db_render_state
);
248 if (ctx
->b
.chip_class
>= GFX9
)
249 si_mark_atom_dirty(ctx
, &ctx
->dpbb_state
);
250 si_mark_atom_dirty(ctx
, &ctx
->stencil_ref
.atom
);
251 si_mark_atom_dirty(ctx
, &ctx
->spi_map
);
252 si_mark_atom_dirty(ctx
, &ctx
->streamout
.enable_atom
);
253 si_mark_atom_dirty(ctx
, &ctx
->b
.render_cond_atom
);
254 si_all_descriptors_begin_new_cs(ctx
);
255 si_all_resident_buffers_begin_new_cs(ctx
);
257 ctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
258 ctx
->viewports
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
259 ctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
260 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
261 si_mark_atom_dirty(ctx
, &ctx
->viewports
.atom
);
263 si_mark_atom_dirty(ctx
, &ctx
->scratch_state
);
264 if (ctx
->scratch_buffer
) {
265 r600_context_add_resource_size(&ctx
->b
.b
,
266 &ctx
->scratch_buffer
->b
.b
);
269 if (ctx
->streamout
.suspended
) {
270 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
271 si_streamout_buffers_dirty(ctx
);
274 si_postflush_resume_features(&ctx
->b
);
276 assert(!ctx
->b
.gfx
.cs
->prev_dw
);
277 ctx
->b
.initial_gfx_cs_size
= ctx
->b
.gfx
.cs
->current
.cdw
;
279 /* Invalidate various draw states so that they are emitted before
280 * the first draw call. */
281 si_invalidate_draw_sh_constants(ctx
);
282 ctx
->last_index_size
= -1;
283 ctx
->last_primitive_restart_en
= -1;
284 ctx
->last_restart_index
= SI_RESTART_INDEX_UNKNOWN
;
285 ctx
->last_gs_out_prim
= -1;
287 ctx
->last_multi_vgt_param
= -1;
288 ctx
->last_rast_prim
= -1;
289 ctx
->last_sc_line_stipple
= ~0;
290 ctx
->last_vs_state
= ~0;
292 ctx
->last_tcs
= NULL
;
293 ctx
->last_tes_sh_base
= -1;
294 ctx
->last_num_tcs_input_cp
= -1;
296 ctx
->cs_shader_state
.initialized
= false;