src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "si_pipe.h"
  28 #include "radeon/r600_cs.h"
  29
  30 static unsigned si_descriptor_list_cs_space(unsigned count, unsigned element_size)
  31 {
  32         /* Ensure we have enough space to start a new range in a hole */
  33         assert(element_size >= 3);
  34
  35         /* 5 dwords for possible load to reinitialize when we have no preamble
  36          * IB + 5 dwords for write to L2 + 3 bytes for every range written to
  37          * CE RAM.
  38          */
  39         return 5 + 5 + 3 + count * element_size;
  40 }
  41
  42 static unsigned si_ce_needed_cs_space(void)
  43 {
  44         unsigned space = 0;
  45
  46         space += si_descriptor_list_cs_space(SI_NUM_CONST_BUFFERS, 4);
  47         space += si_descriptor_list_cs_space(SI_NUM_SHADER_BUFFERS, 4);
  48         space += si_descriptor_list_cs_space(SI_NUM_SAMPLERS, 16);
  49         space += si_descriptor_list_cs_space(SI_NUM_IMAGES, 8);
  50         space *= SI_NUM_SHADERS;
  51
  52         space += si_descriptor_list_cs_space(SI_NUM_RW_BUFFERS, 4);
  53
  54         /* Increment CE counter packet */
  55         space += 2;
  56
  57         return space;
  58 }
  59
  60 /* initialize */
  61 void si_need_cs_space(struct si_context *ctx)
  62 {
  63         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
  64         struct radeon_winsys_cs *ce_ib = ctx->ce_ib;
  65         struct radeon_winsys_cs *dma = ctx->b.dma.cs;
  66
  67         /* Flush the DMA IB if it's not empty. */
  68         if (radeon_emitted(dma, 0))
  69                 ctx->b.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  70
  71         /* There are two memory usage counters in the winsys for all buffers
  72          * that have been added (cs_add_buffer) and two counters in the pipe
  73          * driver for those that haven't been added yet.
  74          */
  75         if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
  76                                                    ctx->b.vram, ctx->b.gtt))) {
  77                 ctx->b.gtt = 0;
  78                 ctx->b.vram = 0;
  79                 ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                 return;
  81         }
  82         ctx->b.gtt = 0;
  83         ctx->b.vram = 0;
  84
  85         /* If the CS is sufficiently large, don't count the space needed
  86          * and just flush if there is not enough space left.
  87          */
  88         if (!ctx->b.ws->cs_check_space(cs, 2048) ||
  89             (ce_ib && !ctx->b.ws->cs_check_space(ce_ib, si_ce_needed_cs_space())))
  90                 ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  91 }
  92
  93 void si_context_gfx_flush(void *context, unsigned flags,
  94                           struct pipe_fence_handle **fence)
  95 {
  96         struct si_context *ctx = context;
  97         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
  98         struct radeon_winsys *ws = ctx->b.ws;
  99
 100         if (ctx->gfx_flush_in_progress)
 101                 return;
 102
 103         if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
 104                 return;
 105
 106         ctx->gfx_flush_in_progress = true;
 107
 108         r600_preflush_suspend_features(&ctx->b);
 109
 110         ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 111                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 112
 113         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 114         if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
 115                 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 116                                 SI_CONTEXT_INV_VMEM_L1;
 117
 118         si_emit_cache_flush(ctx, NULL);
 119
 120         if (ctx->trace_buf)
 121                 si_trace_emit(ctx);
 122
 123         if (ctx->is_debug) {
 124                 /* Save the IB for debug contexts. */
 125                 radeon_clear_saved_cs(&ctx->last_gfx);
 126                 radeon_save_cs(ws, cs, &ctx->last_gfx);
 127                 r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
 128                 r600_resource_reference(&ctx->trace_buf, NULL);
 129         }
 130
 131         /* Flush the CS. */
 132         ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
 133         if (fence)
 134                 ws->fence_reference(fence, ctx->b.last_gfx_fence);
 135         ctx->b.num_gfx_cs_flushes++;
 136
 137         /* Check VM faults if needed. */
 138         if (ctx->screen->b.debug_flags & DBG_CHECK_VM) {
 139                 /* Use conservative timeout 800ms, after which we won't wait any
 140                  * longer and assume the GPU is hung.
 141                  */
 142                 ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
 143
 144                 si_check_vm_faults(&ctx->b, &ctx->last_gfx, RING_GFX);
 145         }
 146
 147         si_begin_new_cs(ctx);
 148         ctx->gfx_flush_in_progress = false;
 149 }
 150
 151 void si_begin_new_cs(struct si_context *ctx)
 152 {
 153         if (ctx->is_debug) {
 154                 uint32_t zero = 0;
 155
 156                 /* Create a buffer used for writing trace IDs and initialize it to 0. */
 157                 assert(!ctx->trace_buf);
 158                 ctx->trace_buf = (struct r600_resource*)
 159                                  pipe_buffer_create(ctx->b.b.screen, PIPE_BIND_CUSTOM,
 160                                                     PIPE_USAGE_STAGING, 4);
 161                 if (ctx->trace_buf)
 162                         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
 163                                                     0, sizeof(zero), &zero);
 164                 ctx->trace_id = 0;
 165         }
 166
 167         if (ctx->trace_buf)
 168                 si_trace_emit(ctx);
 169
 170         /* Flush read caches at the beginning of CS not flushed by the kernel. */
 171         if (ctx->b.chip_class >= CIK)
 172                 ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
 173                                 SI_CONTEXT_INV_ICACHE;
 174
 175         ctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
 176
 177         /* set all valid group as dirty so they get reemited on
 178          * next draw command
 179          */
 180         si_pm4_reset_emitted(ctx);
 181
 182         /* The CS initialization should be emitted before everything else. */
 183         si_pm4_emit(ctx, ctx->init_config);
 184         if (ctx->init_config_gs_rings)
 185                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 186
 187         if (ctx->ce_preamble_ib)
 188                 si_ce_enable_loads(ctx->ce_preamble_ib);
 189         else if (ctx->ce_ib)
 190                 si_ce_enable_loads(ctx->ce_ib);
 191
 192         if (ctx->ce_preamble_ib)
 193                 si_ce_reinitialize_all_descriptors(ctx);
 194
 195         ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
 196         ctx->framebuffer.dirty_zsbuf = true;
 197         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 198
 199         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 200         si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 201         ctx->msaa_sample_locs.nr_samples = 0;
 202         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 203         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 204         si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 205         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 206         si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 207         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 208         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 209         si_mark_atom_dirty(ctx, &ctx->spi_map);
 210         si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
 211         si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
 212         si_all_descriptors_begin_new_cs(ctx);
 213
 214         ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 215         ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 216         ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 217         si_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
 218         si_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
 219
 220         r600_postflush_resume_features(&ctx->b);
 221
 222         assert(!ctx->b.gfx.cs->prev_dw);
 223         ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
 224
 225         /* Invalidate various draw states so that they are emitted before
 226          * the first draw call. */
 227         si_invalidate_draw_sh_constants(ctx);
 228         ctx->last_index_size = -1;
 229         ctx->last_primitive_restart_en = -1;
 230         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 231         ctx->last_gs_out_prim = -1;
 232         ctx->last_prim = -1;
 233         ctx->last_multi_vgt_param = -1;
 234         ctx->last_ls_hs_config = -1;
 235         ctx->last_rast_prim = -1;
 236         ctx->last_sc_line_stipple = ~0;
 237         ctx->last_vtx_reuse_depth = -1;
 238         ctx->emit_scratch_reloc = true;
 239         ctx->last_ls = NULL;
 240         ctx->last_tcs = NULL;
 241         ctx->last_tes_sh_base = -1;
 242         ctx->last_num_tcs_input_cp = -1;
 243
 244         ctx->cs_shader_state.initialized = false;
 245 }