2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 void si_need_cs_space(struct si_context
*ctx
, unsigned num_dw
,
31 boolean count_draw_in
)
35 /* The number of dwords we already used in the CS so far. */
36 num_dw
+= ctx
->b
.rings
.gfx
.cs
->cdw
;
38 for (i
= 0; i
< SI_NUM_ATOMS(ctx
); i
++) {
39 if (ctx
->atoms
.array
[i
]->dirty
) {
40 num_dw
+= ctx
->atoms
.array
[i
]->num_dw
;
45 /* The number of dwords all the dirty states would take. */
46 num_dw
+= ctx
->pm4_dirty_cdwords
;
48 /* The upper-bound of how much a draw command would take. */
49 num_dw
+= SI_MAX_DRAW_CS_DWORDS
;
52 /* Count in queries_suspend. */
53 num_dw
+= ctx
->b
.num_cs_dw_nontimer_queries_suspend
;
55 /* Count in streamout_end at the end of CS. */
56 if (ctx
->b
.streamout
.begin_emitted
) {
57 num_dw
+= ctx
->b
.streamout
.num_dw_for_end
;
60 /* Count in render_condition(NULL) at the end of CS. */
61 if (ctx
->b
.predicate_drawing
) {
65 /* Count in framebuffer cache flushes at the end of CS. */
66 num_dw
+= ctx
->atoms
.cache_flush
->num_dw
;
69 if (ctx
->screen
->b
.trace_bo
) {
70 num_dw
+= SI_TRACE_CS_DWORDS
;
74 /* Flush if there's not enough space. */
75 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
76 si_flush(&ctx
->b
.b
, NULL
, RADEON_FLUSH_ASYNC
);
80 void si_context_flush(struct si_context
*ctx
, unsigned flags
)
82 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
84 if (cs
->cdw
== ctx
->b
.initial_gfx_cs_size
)
88 ctx
->b
.nontimer_queries_suspended
= false;
89 if (ctx
->b
.num_cs_dw_nontimer_queries_suspend
) {
90 r600_suspend_nontimer_queries(&ctx
->b
);
91 ctx
->b
.nontimer_queries_suspended
= true;
94 ctx
->b
.streamout
.suspended
= false;
96 if (ctx
->b
.streamout
.begin_emitted
) {
97 r600_emit_streamout_end(&ctx
->b
);
98 ctx
->b
.streamout
.suspended
= true;
101 ctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
102 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
103 R600_CONTEXT_FLUSH_AND_INV_DB
|
104 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
105 R600_CONTEXT_INV_TEX_CACHE
|
106 /* this is probably not needed anymore */
107 R600_CONTEXT_PS_PARTIAL_FLUSH
;
108 si_emit_cache_flush(&ctx
->b
, NULL
);
110 /* force to keep tiling flags */
111 flags
|= RADEON_FLUSH_KEEP_TILING_FLAGS
;
114 if (ctx
->screen
->b
.trace_bo
) {
115 struct si_screen
*sscreen
= ctx
->screen
;
118 for (i
= 0; i
< cs
->cdw
; i
++) {
119 fprintf(stderr
, "[%4d] [%5d] 0x%08x\n", sscreen
->b
.cs_count
, i
, cs
->buf
[i
]);
121 sscreen
->b
.cs_count
++;
126 ctx
->b
.ws
->cs_flush(ctx
->b
.rings
.gfx
.cs
, flags
, 0);
129 if (ctx
->screen
->b
.trace_bo
) {
130 struct si_screen
*sscreen
= ctx
->screen
;
133 for (i
= 0; i
< 10; i
++) {
135 if (!ctx
->ws
->buffer_is_busy(sscreen
->b
.trace_bo
->buf
, RADEON_USAGE_READWRITE
)) {
140 fprintf(stderr
, "timeout on cs lockup likely happen at cs %d dw %d\n",
141 sscreen
->b
.trace_ptr
[1], sscreen
->b
.trace_ptr
[0]);
143 fprintf(stderr
, "cs %d executed in %dms\n", sscreen
->b
.trace_ptr
[1], i
* 5);
148 si_begin_new_cs(ctx
);
151 void si_begin_new_cs(struct si_context
*ctx
)
153 ctx
->pm4_dirty_cdwords
= 0;
155 /* Flush read caches at the beginning of CS. */
156 ctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
157 R600_CONTEXT_INV_CONST_CACHE
|
158 R600_CONTEXT_INV_SHADER_CACHE
;
160 /* set all valid group as dirty so they get reemited on
163 si_pm4_reset_emitted(ctx
);
165 /* The CS initialization should be emitted before everything else. */
166 si_pm4_emit(ctx
, ctx
->queued
.named
.init
);
167 ctx
->emitted
.named
.init
= ctx
->queued
.named
.init
;
169 if (ctx
->b
.streamout
.suspended
) {
170 ctx
->b
.streamout
.append_bitmask
= ctx
->b
.streamout
.enabled_mask
;
171 r600_streamout_buffers_dirty(&ctx
->b
);
175 if (ctx
->b
.nontimer_queries_suspended
) {
176 r600_resume_nontimer_queries(&ctx
->b
);
179 si_all_descriptors_begin_new_cs(ctx
);
181 ctx
->b
.initial_gfx_cs_size
= ctx
->b
.rings
.gfx
.cs
->cdw
;
185 void si_trace_emit(struct si_context
*sctx
)
187 struct si_screen
*sscreen
= sctx
->screen
;
188 struct radeon_winsys_cs
*cs
= sctx
->cs
;
191 va
= r600_resource_va(&sscreen
->screen
, (void*)sscreen
->b
.trace_bo
);
192 r600_context_bo_reloc(sctx
, sscreen
->b
.trace_bo
, RADEON_USAGE_READWRITE
);
193 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_WRITE_DATA
, 4, 0);
194 cs
->buf
[cs
->cdw
++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC
) |
195 PKT3_WRITE_DATA_WR_CONFIRM
|
196 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME
);
197 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
;
198 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFFFFFFFUL
;
199 cs
->buf
[cs
->cdw
++] = cs
->cdw
;
200 cs
->buf
[cs
->cdw
++] = sscreen
->b
.cs_count
;