src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "../radeon/r600_cs.h"
  27 #include "sid.h"
  28 #include "si_pm4.h"
  29 #include "si_pipe.h"
  30 #include "util/u_memory.h"
  31 #include <errno.h>
  32
  33
  34 /* initialize */
  35 void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
  36                         boolean count_draw_in)
  37 {
  38         int i;
  39
  40         /* The number of dwords we already used in the CS so far. */
  41         num_dw += ctx->b.rings.gfx.cs->cdw;
  42
  43         for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
  44                 if (ctx->atoms.array[i]->dirty) {
  45                         num_dw += ctx->atoms.array[i]->num_dw;
  46                 }
  47         }
  48
  49         if (count_draw_in) {
  50                 /* The number of dwords all the dirty states would take. */
  51                 num_dw += ctx->pm4_dirty_cdwords;
  52
  53                 /* The upper-bound of how much a draw command would take. */
  54                 num_dw += SI_MAX_DRAW_CS_DWORDS;
  55         }
  56
  57         /* Count in queries_suspend. */
  58         num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend;
  59
  60         /* Count in streamout_end at the end of CS. */
  61         if (ctx->b.streamout.begin_emitted) {
  62                 num_dw += ctx->b.streamout.num_dw_for_end;
  63         }
  64
  65         /* Count in render_condition(NULL) at the end of CS. */
  66         if (ctx->b.predicate_drawing) {
  67                 num_dw += 3;
  68         }
  69
  70         /* Count in framebuffer cache flushes at the end of CS. */
  71         num_dw += ctx->atoms.cache_flush->num_dw;
  72
  73 #if SI_TRACE_CS
  74         if (ctx->screen->b.trace_bo) {
  75                 num_dw += SI_TRACE_CS_DWORDS;
  76         }
  77 #endif
  78
  79         /* Flush if there's not enough space. */
  80         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  81                 si_flush(&ctx->b.b, NULL, RADEON_FLUSH_ASYNC);
  82         }
  83 }
  84
  85 void si_context_flush(struct si_context *ctx, unsigned flags)
  86 {
  87         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  88
  89         if (!cs->cdw)
  90                 return;
  91
  92         /* suspend queries */
  93         ctx->b.nontimer_queries_suspended = false;
  94         if (ctx->b.num_cs_dw_nontimer_queries_suspend) {
  95                 r600_suspend_nontimer_queries(&ctx->b);
  96                 ctx->b.nontimer_queries_suspended = true;
  97         }
  98
  99         ctx->b.streamout.suspended = false;
 100
 101         if (ctx->b.streamout.begin_emitted) {
 102                 r600_emit_streamout_end(&ctx->b);
 103                 ctx->b.streamout.suspended = true;
 104         }
 105
 106         ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
 107                         R600_CONTEXT_FLUSH_AND_INV_CB_META |
 108                         R600_CONTEXT_FLUSH_AND_INV_DB |
 109                         R600_CONTEXT_FLUSH_AND_INV_DB_META |
 110                         R600_CONTEXT_INV_TEX_CACHE;
 111         si_emit_cache_flush(&ctx->b, NULL);
 112
 113         /* this is probably not needed anymore */
 114         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 115         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 116
 117         /* force to keep tiling flags */
 118         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 119
 120 #if SI_TRACE_CS
 121         if (ctx->screen->b.trace_bo) {
 122                 struct si_screen *sscreen = ctx->screen;
 123                 unsigned i;
 124
 125                 for (i = 0; i < cs->cdw; i++) {
 126                         fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]);
 127                 }
 128                 sscreen->b.cs_count++;
 129         }
 130 #endif
 131
 132         /* Flush the CS. */
 133         ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, 0);
 134
 135 #if SI_TRACE_CS
 136         if (ctx->screen->b.trace_bo) {
 137                 struct si_screen *sscreen = ctx->screen;
 138                 unsigned i;
 139
 140                 for (i = 0; i < 10; i++) {
 141                         usleep(5);
 142                         if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
 143                                 break;
 144                         }
 145                 }
 146                 if (i == 10) {
 147                         fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
 148                                 sscreen->b.trace_ptr[1], sscreen->b.trace_ptr[0]);
 149                 } else {
 150                         fprintf(stderr, "cs %d executed in %dms\n", sscreen->b.trace_ptr[1], i * 5);
 151                 }
 152         }
 153 #endif
 154
 155         si_begin_new_cs(ctx);
 156 }
 157
 158 void si_begin_new_cs(struct si_context *ctx)
 159 {
 160         ctx->pm4_dirty_cdwords = 0;
 161
 162         /* Flush read caches at the beginning of CS. */
 163         ctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
 164                         R600_CONTEXT_INV_CONST_CACHE |
 165                         R600_CONTEXT_INV_SHADER_CACHE;
 166
 167         /* set all valid group as dirty so they get reemited on
 168          * next draw command
 169          */
 170         si_pm4_reset_emitted(ctx);
 171
 172         /* The CS initialization should be emitted before everything else. */
 173         si_pm4_emit(ctx, ctx->queued.named.init);
 174         ctx->emitted.named.init = ctx->queued.named.init;
 175
 176         if (ctx->b.streamout.suspended) {
 177                 ctx->b.streamout.append_bitmask = ctx->b.streamout.enabled_mask;
 178                 r600_streamout_buffers_dirty(&ctx->b);
 179         }
 180
 181         /* resume queries */
 182         if (ctx->b.nontimer_queries_suspended) {
 183                 r600_resume_nontimer_queries(&ctx->b);
 184         }
 185
 186         si_all_descriptors_begin_new_cs(ctx);
 187 }
 188
 189 #if SI_TRACE_CS
 190 void si_trace_emit(struct si_context *sctx)
 191 {
 192         struct si_screen *sscreen = sctx->screen;
 193         struct radeon_winsys_cs *cs = sctx->cs;
 194         uint64_t va;
 195
 196         va = r600_resource_va(&sscreen->screen, (void*)sscreen->b.trace_bo);
 197         r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE);
 198         cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
 199         cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
 200                                 PKT3_WRITE_DATA_WR_CONFIRM |
 201                                 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME);
 202         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
 203         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
 204         cs->buf[cs->cdw++] = cs->cdw;
 205         cs->buf[cs->cdw++] = sscreen->b.cs_count;
 206 }
 207 #endif