2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 void si_need_cs_space(struct si_context
*ctx
)
32 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
34 /* There are two memory usage counters in the winsys for all buffers
35 * that have been added (cs_add_reloc) and two counters in the pipe
36 * driver for those that haven't been added yet.
38 if (unlikely(!ctx
->b
.ws
->cs_memory_below_limit(ctx
->b
.rings
.gfx
.cs
,
39 ctx
->b
.vram
, ctx
->b
.gtt
))) {
42 ctx
->b
.rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
48 /* If the CS is sufficiently large, don't count the space needed
49 * and just flush if there is not enough space left.
51 if (unlikely(cs
->cdw
> cs
->max_dw
- 2048))
52 ctx
->b
.rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
55 void si_context_gfx_flush(void *context
, unsigned flags
,
56 struct pipe_fence_handle
**fence
)
58 struct si_context
*ctx
= context
;
59 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
60 struct radeon_winsys
*ws
= ctx
->b
.ws
;
62 if (cs
->cdw
== ctx
->b
.initial_gfx_cs_size
&&
63 (!fence
|| ctx
->last_gfx_fence
)) {
65 ws
->fence_reference(fence
, ctx
->last_gfx_fence
);
66 if (!(flags
& RADEON_FLUSH_ASYNC
))
67 ws
->cs_sync_flush(cs
);
71 ctx
->b
.rings
.gfx
.flushing
= true;
73 r600_preflush_suspend_features(&ctx
->b
);
75 ctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
|
76 SI_CONTEXT_INV_TC_L1
|
77 SI_CONTEXT_INV_TC_L2
|
78 /* this is probably not needed anymore */
79 SI_CONTEXT_PS_PARTIAL_FLUSH
;
80 si_emit_cache_flush(ctx
, NULL
);
82 /* force to keep tiling flags */
83 flags
|= RADEON_FLUSH_KEEP_TILING_FLAGS
;
88 /* Save the IB for debug contexts. */
91 ctx
->last_ib_dw_size
= cs
->cdw
;
92 ctx
->last_ib
= malloc(cs
->cdw
* 4);
93 memcpy(ctx
->last_ib
, cs
->buf
, cs
->cdw
* 4);
94 r600_resource_reference(&ctx
->last_trace_buf
, ctx
->trace_buf
);
95 r600_resource_reference(&ctx
->trace_buf
, NULL
);
99 ws
->cs_flush(cs
, flags
, &ctx
->last_gfx_fence
,
100 ctx
->screen
->b
.cs_count
++);
101 ctx
->b
.rings
.gfx
.flushing
= false;
104 ws
->fence_reference(fence
, ctx
->last_gfx_fence
);
106 si_begin_new_cs(ctx
);
109 void si_begin_new_cs(struct si_context
*ctx
)
114 /* Create a buffer used for writing trace IDs and initialize it to 0. */
115 assert(!ctx
->trace_buf
);
116 ctx
->trace_buf
= (struct r600_resource
*)
117 pipe_buffer_create(ctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
118 PIPE_USAGE_STAGING
, 4);
120 pipe_buffer_write_nooverlap(&ctx
->b
.b
, &ctx
->trace_buf
->b
.b
,
121 0, sizeof(zero
), &zero
);
128 /* Flush read caches at the beginning of CS. */
129 ctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
|
130 SI_CONTEXT_INV_TC_L1
|
131 SI_CONTEXT_INV_TC_L2
|
132 SI_CONTEXT_INV_KCACHE
|
133 SI_CONTEXT_INV_ICACHE
;
135 /* set all valid group as dirty so they get reemited on
138 si_pm4_reset_emitted(ctx
);
140 /* The CS initialization should be emitted before everything else. */
141 si_pm4_emit(ctx
, ctx
->init_config
);
143 ctx
->framebuffer
.dirty_cbufs
= (1 << 8) - 1;
144 ctx
->framebuffer
.dirty_zsbuf
= true;
145 si_mark_atom_dirty(ctx
, &ctx
->framebuffer
.atom
);
147 si_mark_atom_dirty(ctx
, &ctx
->clip_regs
);
148 si_mark_atom_dirty(ctx
, &ctx
->clip_state
.atom
);
149 si_mark_atom_dirty(ctx
, &ctx
->msaa_sample_locs
);
150 si_mark_atom_dirty(ctx
, &ctx
->msaa_config
);
151 si_mark_atom_dirty(ctx
, &ctx
->sample_mask
.atom
);
152 si_mark_atom_dirty(ctx
, &ctx
->cb_target_mask
);
153 si_mark_atom_dirty(ctx
, &ctx
->blend_color
.atom
);
154 si_mark_atom_dirty(ctx
, &ctx
->db_render_state
);
155 si_mark_atom_dirty(ctx
, &ctx
->stencil_ref
.atom
);
156 si_mark_atom_dirty(ctx
, &ctx
->spi_map
);
157 si_mark_atom_dirty(ctx
, &ctx
->b
.streamout
.enable_atom
);
158 si_all_descriptors_begin_new_cs(ctx
);
160 ctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
161 ctx
->viewports
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
162 si_mark_atom_dirty(ctx
, &ctx
->scissors
.atom
);
163 si_mark_atom_dirty(ctx
, &ctx
->viewports
.atom
);
165 r600_postflush_resume_features(&ctx
->b
);
167 ctx
->b
.initial_gfx_cs_size
= ctx
->b
.rings
.gfx
.cs
->cdw
;
169 /* Invalidate various draw states so that they are emitted before
170 * the first draw call. */
171 si_invalidate_draw_sh_constants(ctx
);
172 ctx
->last_primitive_restart_en
= -1;
173 ctx
->last_restart_index
= SI_RESTART_INDEX_UNKNOWN
;
174 ctx
->last_gs_out_prim
= -1;
176 ctx
->last_multi_vgt_param
= -1;
177 ctx
->last_ls_hs_config
= -1;
178 ctx
->last_rast_prim
= -1;
179 ctx
->last_sc_line_stipple
= ~0;
180 ctx
->emit_scratch_reloc
= true;
182 ctx
->last_tcs
= NULL
;
183 ctx
->last_tes_sh_base
= -1;
184 ctx
->last_num_tcs_input_cp
= -1;