src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "si_pipe.h"
  28
  29 /* initialize */
  30 void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
  31                         boolean count_draw_in)
  32 {
  33         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  34
  35         /* There are two memory usage counters in the winsys for all buffers
  36          * that have been added (cs_add_reloc) and two counters in the pipe
  37          * driver for those that haven't been added yet.
  38          * */
  39         if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) {
  40                 ctx->b.gtt = 0;
  41                 ctx->b.vram = 0;
  42                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  43                 return;
  44         }
  45         ctx->b.gtt = 0;
  46         ctx->b.vram = 0;
  47
  48         /* If the CS is sufficiently large, don't count the space needed
  49          * and just flush if there is less than 8096 dwords left.
  50          */
  51         if (cs->max_dw >= 24 * 1024) {
  52                 if (cs->cdw > cs->max_dw - 8 * 1024)
  53                         ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  54                 return;
  55         }
  56
  57         /* The number of dwords we already used in the CS so far. */
  58         num_dw += cs->cdw;
  59
  60         if (count_draw_in) {
  61                 unsigned mask = ctx->dirty_atoms;
  62
  63                 while (mask)
  64                         num_dw += ctx->atoms.array[u_bit_scan(&mask)]->num_dw;
  65
  66                 /* The number of dwords all the dirty states would take. */
  67                 num_dw += si_pm4_dirty_dw(ctx);
  68
  69                 /* The upper-bound of how much a draw command would take. */
  70                 num_dw += SI_MAX_DRAW_CS_DWORDS;
  71         }
  72
  73         /* Count in queries_suspend. */
  74         num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend +
  75                   ctx->b.num_cs_dw_timer_queries_suspend;
  76
  77         /* Count in streamout_end at the end of CS. */
  78         if (ctx->b.streamout.begin_emitted) {
  79                 num_dw += ctx->b.streamout.num_dw_for_end;
  80         }
  81
  82         /* Count in render_condition(NULL) at the end of CS. */
  83         if (ctx->b.predicate_drawing) {
  84                 num_dw += 3;
  85         }
  86
  87         /* Count in framebuffer cache flushes at the end of CS. */
  88         num_dw += ctx->atoms.s.cache_flush->num_dw;
  89
  90         if (ctx->screen->b.trace_bo)
  91                 num_dw += SI_TRACE_CS_DWORDS * 2;
  92
  93         /* Flush if there's not enough space. */
  94         if (num_dw > cs->max_dw) {
  95                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  96         }
  97 }
  98
  99 void si_context_gfx_flush(void *context, unsigned flags,
 100                           struct pipe_fence_handle **fence)
 101 {
 102         struct si_context *ctx = context;
 103         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
 104         struct radeon_winsys *ws = ctx->b.ws;
 105
 106         if (cs->cdw == ctx->b.initial_gfx_cs_size &&
 107             (!fence || ctx->last_gfx_fence)) {
 108                 if (fence)
 109                         ws->fence_reference(fence, ctx->last_gfx_fence);
 110                 if (!(flags & RADEON_FLUSH_ASYNC))
 111                         ws->cs_sync_flush(cs);
 112                 return;
 113         }
 114
 115         ctx->b.rings.gfx.flushing = true;
 116
 117         r600_preflush_suspend_features(&ctx->b);
 118
 119         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
 120                         SI_CONTEXT_INV_TC_L1 |
 121                         SI_CONTEXT_INV_TC_L2 |
 122                         /* this is probably not needed anymore */
 123                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 124         si_emit_cache_flush(ctx, NULL);
 125
 126         /* force to keep tiling flags */
 127         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 128
 129         if (ctx->trace_buf)
 130                 si_trace_emit(ctx);
 131
 132         /* Save the IB for debug contexts. */
 133         if (ctx->is_debug) {
 134                 free(ctx->last_ib);
 135                 ctx->last_ib_dw_size = cs->cdw;
 136                 ctx->last_ib = malloc(cs->cdw * 4);
 137                 memcpy(ctx->last_ib, cs->buf, cs->cdw * 4);
 138                 r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
 139                 r600_resource_reference(&ctx->trace_buf, NULL);
 140         }
 141
 142         /* Flush the CS. */
 143         ws->cs_flush(cs, flags, &ctx->last_gfx_fence,
 144                      ctx->screen->b.cs_count++);
 145         ctx->b.rings.gfx.flushing = false;
 146
 147         if (fence)
 148                 ws->fence_reference(fence, ctx->last_gfx_fence);
 149
 150         si_begin_new_cs(ctx);
 151 }
 152
 153 void si_begin_new_cs(struct si_context *ctx)
 154 {
 155         if (ctx->is_debug) {
 156                 uint32_t zero = 0;
 157
 158                 /* Create a buffer used for writing trace IDs and initialize it to 0. */
 159                 assert(!ctx->trace_buf);
 160                 ctx->trace_buf = (struct r600_resource*)
 161                                  pipe_buffer_create(ctx->b.b.screen, PIPE_BIND_CUSTOM,
 162                                                     PIPE_USAGE_STAGING, 4);
 163                 if (ctx->trace_buf)
 164                         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
 165                                                     0, sizeof(zero), &zero);
 166                 ctx->trace_id = 0;
 167         }
 168
 169         if (ctx->trace_buf)
 170                 si_trace_emit(ctx);
 171
 172         /* Flush read caches at the beginning of CS. */
 173         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
 174                         SI_CONTEXT_INV_TC_L1 |
 175                         SI_CONTEXT_INV_TC_L2 |
 176                         SI_CONTEXT_INV_KCACHE |
 177                         SI_CONTEXT_INV_ICACHE;
 178
 179         /* set all valid group as dirty so they get reemited on
 180          * next draw command
 181          */
 182         si_pm4_reset_emitted(ctx);
 183
 184         /* The CS initialization should be emitted before everything else. */
 185         si_pm4_emit(ctx, ctx->init_config);
 186
 187         ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
 188         ctx->framebuffer.dirty_zsbuf = true;
 189         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 190
 191         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 192         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs);
 193         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 194         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 195         si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
 196         si_all_descriptors_begin_new_cs(ctx);
 197
 198         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 199         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 200         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 201         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 202
 203         r600_postflush_resume_features(&ctx->b);
 204
 205         ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 206
 207         /* Invalidate various draw states so that they are emitted before
 208          * the first draw call. */
 209         si_invalidate_draw_sh_constants(ctx);
 210         ctx->last_primitive_restart_en = -1;
 211         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 212         ctx->last_gs_out_prim = -1;
 213         ctx->last_prim = -1;
 214         ctx->last_multi_vgt_param = -1;
 215         ctx->last_ls_hs_config = -1;
 216         ctx->last_rast_prim = -1;
 217         ctx->last_sc_line_stipple = ~0;
 218         ctx->emit_scratch_reloc = true;
 219         ctx->last_ls = NULL;
 220         ctx->last_tcs = NULL;
 221         ctx->last_tes_sh_base = -1;
 222         ctx->last_num_tcs_input_cp = -1;
 223 }