src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "si_pipe.h"
  28
  29 /* initialize */
  30 void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
  31                         boolean count_draw_in)
  32 {
  33         int i;
  34
  35         /* The number of dwords we already used in the CS so far. */
  36         num_dw += ctx->b.rings.gfx.cs->cdw;
  37
  38         for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
  39                 if (ctx->atoms.array[i]->dirty) {
  40                         num_dw += ctx->atoms.array[i]->num_dw;
  41                 }
  42         }
  43
  44         if (count_draw_in) {
  45                 /* The number of dwords all the dirty states would take. */
  46                 num_dw += ctx->pm4_dirty_cdwords;
  47
  48                 /* The upper-bound of how much a draw command would take. */
  49                 num_dw += SI_MAX_DRAW_CS_DWORDS;
  50         }
  51
  52         /* Count in queries_suspend. */
  53         num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend;
  54
  55         /* Count in streamout_end at the end of CS. */
  56         if (ctx->b.streamout.begin_emitted) {
  57                 num_dw += ctx->b.streamout.num_dw_for_end;
  58         }
  59
  60         /* Count in render_condition(NULL) at the end of CS. */
  61         if (ctx->b.predicate_drawing) {
  62                 num_dw += 3;
  63         }
  64
  65         /* Count in framebuffer cache flushes at the end of CS. */
  66         num_dw += ctx->atoms.s.cache_flush->num_dw;
  67
  68 #if SI_TRACE_CS
  69         if (ctx->screen->b.trace_bo) {
  70                 num_dw += SI_TRACE_CS_DWORDS;
  71         }
  72 #endif
  73
  74         /* Flush if there's not enough space. */
  75         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  76                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  77         }
  78 }
  79
  80 void si_context_gfx_flush(void *context, unsigned flags,
  81                           struct pipe_fence_handle **fence)
  82 {
  83         struct si_context *ctx = context;
  84         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  85
  86         if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence)
  87                 return;
  88
  89         ctx->b.rings.gfx.flushing = true;
  90
  91         r600_preflush_suspend_features(&ctx->b);
  92
  93         ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
  94                         R600_CONTEXT_FLUSH_AND_INV_CB_META |
  95                         R600_CONTEXT_FLUSH_AND_INV_DB |
  96                         R600_CONTEXT_FLUSH_AND_INV_DB_META |
  97                         R600_CONTEXT_INV_TEX_CACHE |
  98                         /* this is probably not needed anymore */
  99                         R600_CONTEXT_PS_PARTIAL_FLUSH;
 100         si_emit_cache_flush(&ctx->b, NULL);
 101
 102         /* force to keep tiling flags */
 103         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 104
 105 #if SI_TRACE_CS
 106         if (ctx->screen->b.trace_bo) {
 107                 struct si_screen *sscreen = ctx->screen;
 108                 unsigned i;
 109
 110                 for (i = 0; i < cs->cdw; i++) {
 111                         fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]);
 112                 }
 113                 sscreen->b.cs_count++;
 114         }
 115 #endif
 116
 117         /* Flush the CS. */
 118         ctx->b.ws->cs_flush(cs, flags, fence, 0);
 119         ctx->b.rings.gfx.flushing = false;
 120
 121 #if SI_TRACE_CS
 122         if (ctx->screen->b.trace_bo) {
 123                 struct si_screen *sscreen = ctx->screen;
 124                 unsigned i;
 125
 126                 for (i = 0; i < 10; i++) {
 127                         usleep(5);
 128                         if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) {
 129                                 break;
 130                         }
 131                 }
 132                 if (i == 10) {
 133                         fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
 134                                 sscreen->b.trace_ptr[1], sscreen->b.trace_ptr[0]);
 135                 } else {
 136                         fprintf(stderr, "cs %d executed in %dms\n", sscreen->b.trace_ptr[1], i * 5);
 137                 }
 138         }
 139 #endif
 140
 141         si_begin_new_cs(ctx);
 142 }
 143
 144 void si_begin_new_cs(struct si_context *ctx)
 145 {
 146         ctx->pm4_dirty_cdwords = 0;
 147
 148         /* Flush read caches at the beginning of CS. */
 149         ctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
 150                         R600_CONTEXT_INV_CONST_CACHE |
 151                         R600_CONTEXT_INV_SHADER_CACHE;
 152
 153         /* set all valid group as dirty so they get reemited on
 154          * next draw command
 155          */
 156         si_pm4_reset_emitted(ctx);
 157
 158         /* The CS initialization should be emitted before everything else. */
 159         si_pm4_emit(ctx, ctx->queued.named.init);
 160         ctx->emitted.named.init = ctx->queued.named.init;
 161
 162         ctx->framebuffer.atom.dirty = true;
 163         ctx->b.streamout.enable_atom.dirty = true;
 164         si_all_descriptors_begin_new_cs(ctx);
 165
 166         r600_postflush_resume_features(&ctx->b);
 167
 168         ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 169 }
 170
 171 #if SI_TRACE_CS
 172 void si_trace_emit(struct si_context *sctx)
 173 {
 174         struct si_screen *sscreen = sctx->screen;
 175         struct radeon_winsys_cs *cs = sctx->cs;
 176         uint64_t va;
 177
 178         va = r600_resource_va(&sscreen->screen, (void*)sscreen->b.trace_bo);
 179         r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE);
 180         cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
 181         cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
 182                                 PKT3_WRITE_DATA_WR_CONFIRM |
 183                                 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME);
 184         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
 185         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
 186         cs->buf[cs->cdw++] = cs->cdw;
 187         cs->buf[cs->cdw++] = sscreen->b.cs_count;
 188 }
 189 #endif