2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 void si_need_cs_space(struct si_context
*ctx
, unsigned num_dw
,
31 boolean count_draw_in
)
35 /* The number of dwords we already used in the CS so far. */
36 num_dw
+= ctx
->b
.rings
.gfx
.cs
->cdw
;
39 for (i
= 0; i
< SI_NUM_ATOMS(ctx
); i
++) {
40 if (ctx
->atoms
.array
[i
]->dirty
) {
41 num_dw
+= ctx
->atoms
.array
[i
]->num_dw
;
45 /* The number of dwords all the dirty states would take. */
46 num_dw
+= si_pm4_dirty_dw(ctx
);
48 /* The upper-bound of how much a draw command would take. */
49 num_dw
+= SI_MAX_DRAW_CS_DWORDS
;
52 /* Count in queries_suspend. */
53 num_dw
+= ctx
->b
.num_cs_dw_nontimer_queries_suspend
;
55 /* Count in streamout_end at the end of CS. */
56 if (ctx
->b
.streamout
.begin_emitted
) {
57 num_dw
+= ctx
->b
.streamout
.num_dw_for_end
;
60 /* Count in render_condition(NULL) at the end of CS. */
61 if (ctx
->b
.predicate_drawing
) {
65 /* Count in framebuffer cache flushes at the end of CS. */
66 num_dw
+= ctx
->atoms
.s
.cache_flush
->num_dw
;
69 if (ctx
->screen
->b
.trace_bo
) {
70 num_dw
+= SI_TRACE_CS_DWORDS
;
74 /* Flush if there's not enough space. */
75 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
76 ctx
->b
.rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
80 void si_context_gfx_flush(void *context
, unsigned flags
,
81 struct pipe_fence_handle
**fence
)
83 struct si_context
*ctx
= context
;
84 struct radeon_winsys_cs
*cs
= ctx
->b
.rings
.gfx
.cs
;
85 struct radeon_winsys
*ws
= ctx
->b
.ws
;
87 if (cs
->cdw
== ctx
->b
.initial_gfx_cs_size
&&
88 (!fence
|| ctx
->last_gfx_fence
)) {
90 ws
->fence_reference(fence
, ctx
->last_gfx_fence
);
91 if (!(flags
& RADEON_FLUSH_ASYNC
))
92 ws
->cs_sync_flush(cs
);
96 ctx
->b
.rings
.gfx
.flushing
= true;
98 r600_preflush_suspend_features(&ctx
->b
);
100 ctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
|
101 SI_CONTEXT_INV_TC_L1
|
102 SI_CONTEXT_INV_TC_L2
|
103 /* this is probably not needed anymore */
104 SI_CONTEXT_PS_PARTIAL_FLUSH
;
105 si_emit_cache_flush(&ctx
->b
, NULL
);
107 /* force to keep tiling flags */
108 flags
|= RADEON_FLUSH_KEEP_TILING_FLAGS
;
111 ws
->cs_flush(cs
, flags
, &ctx
->last_gfx_fence
,
112 ctx
->screen
->b
.cs_count
++);
113 ctx
->b
.rings
.gfx
.flushing
= false;
116 ws
->fence_reference(fence
, ctx
->last_gfx_fence
);
119 if (ctx
->screen
->b
.trace_bo
) {
120 struct si_screen
*sscreen
= ctx
->screen
;
123 for (i
= 0; i
< 10; i
++) {
125 if (!ws
->buffer_is_busy(sscreen
->b
.trace_bo
->buf
, RADEON_USAGE_READWRITE
)) {
130 fprintf(stderr
, "timeout on cs lockup likely happen at cs %d dw %d\n",
131 sscreen
->b
.trace_ptr
[1], sscreen
->b
.trace_ptr
[0]);
133 fprintf(stderr
, "cs %d executed in %dms\n", sscreen
->b
.trace_ptr
[1], i
* 5);
138 si_begin_new_cs(ctx
);
141 void si_begin_new_cs(struct si_context
*ctx
)
143 /* Flush read caches at the beginning of CS. */
144 ctx
->b
.flags
|= SI_CONTEXT_INV_TC_L1
|
145 SI_CONTEXT_INV_TC_L2
|
146 SI_CONTEXT_INV_KCACHE
|
147 SI_CONTEXT_INV_ICACHE
;
149 /* set all valid group as dirty so they get reemited on
152 si_pm4_reset_emitted(ctx
);
154 /* The CS initialization should be emitted before everything else. */
155 si_pm4_emit(ctx
, ctx
->init_config
);
157 ctx
->clip_regs
.dirty
= true;
158 ctx
->framebuffer
.atom
.dirty
= true;
159 ctx
->msaa_sample_locs
.dirty
= true;
160 ctx
->msaa_config
.dirty
= true;
161 ctx
->db_render_state
.dirty
= true;
162 ctx
->b
.streamout
.enable_atom
.dirty
= true;
163 si_all_descriptors_begin_new_cs(ctx
);
165 r600_postflush_resume_features(&ctx
->b
);
167 ctx
->b
.initial_gfx_cs_size
= ctx
->b
.rings
.gfx
.cs
->cdw
;
168 si_invalidate_draw_sh_constants(ctx
);
169 ctx
->last_primitive_restart_en
= -1;
170 ctx
->last_restart_index
= SI_RESTART_INDEX_UNKNOWN
;
171 ctx
->last_gs_out_prim
= -1;
173 ctx
->last_multi_vgt_param
= -1;
174 ctx
->last_rast_prim
= -1;
175 ctx
->last_sc_line_stipple
= ~0;
176 ctx
->emit_scratch_reloc
= true;