src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "si_pipe.h"
  28
  29 /* initialize */
  30 void si_need_cs_space(struct si_context *ctx)
  31 {
  32         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  33         struct radeon_winsys_cs *dma = ctx->b.rings.dma.cs;
  34
  35         /* Flush the DMA IB if it's not empty. */
  36         if (dma && dma->cdw)
  37                 ctx->b.rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  38
  39         /* There are two memory usage counters in the winsys for all buffers
  40          * that have been added (cs_add_buffer) and two counters in the pipe
  41          * driver for those that haven't been added yet.
  42          */
  43         if (unlikely(!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs,
  44                                                        ctx->b.vram, ctx->b.gtt))) {
  45                 ctx->b.gtt = 0;
  46                 ctx->b.vram = 0;
  47                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  48                 return;
  49         }
  50         ctx->b.gtt = 0;
  51         ctx->b.vram = 0;
  52
  53         /* If the CS is sufficiently large, don't count the space needed
  54          * and just flush if there is not enough space left.
  55          */
  56         if (unlikely(cs->cdw > cs->max_dw - 2048))
  57                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  58 }
  59
  60 void si_context_gfx_flush(void *context, unsigned flags,
  61                           struct pipe_fence_handle **fence)
  62 {
  63         struct si_context *ctx = context;
  64         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  65         struct radeon_winsys *ws = ctx->b.ws;
  66
  67         if (cs->cdw == ctx->b.initial_gfx_cs_size &&
  68             (!fence || ctx->last_gfx_fence)) {
  69                 if (fence)
  70                         ws->fence_reference(fence, ctx->last_gfx_fence);
  71                 if (!(flags & RADEON_FLUSH_ASYNC))
  72                         ws->cs_sync_flush(cs);
  73                 return;
  74         }
  75
  76         ctx->b.rings.gfx.flushing = true;
  77
  78         r600_preflush_suspend_features(&ctx->b);
  79
  80         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
  81                         SI_CONTEXT_INV_VMEM_L1 |
  82                         SI_CONTEXT_INV_GLOBAL_L2 |
  83                         /* this is probably not needed anymore */
  84                         SI_CONTEXT_PS_PARTIAL_FLUSH;
  85         si_emit_cache_flush(ctx, NULL);
  86
  87         /* force to keep tiling flags */
  88         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
  89
  90         if (ctx->trace_buf)
  91                 si_trace_emit(ctx);
  92
  93         if (ctx->is_debug) {
  94                 unsigned i;
  95
  96                 /* Save the IB for debug contexts. */
  97                 free(ctx->last_ib);
  98                 ctx->last_ib_dw_size = cs->cdw;
  99                 ctx->last_ib = malloc(cs->cdw * 4);
 100                 memcpy(ctx->last_ib, cs->buf, cs->cdw * 4);
 101                 r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
 102                 r600_resource_reference(&ctx->trace_buf, NULL);
 103
 104                 /* Save the buffer list. */
 105                 if (ctx->last_bo_list) {
 106                         for (i = 0; i < ctx->last_bo_count; i++)
 107                                 pb_reference(&ctx->last_bo_list[i].buf, NULL);
 108                         free(ctx->last_bo_list);
 109                 }
 110                 ctx->last_bo_count = ws->cs_get_buffer_list(cs, NULL);
 111                 ctx->last_bo_list = calloc(ctx->last_bo_count,
 112                                            sizeof(ctx->last_bo_list[0]));
 113                 ws->cs_get_buffer_list(cs, ctx->last_bo_list);
 114         }
 115
 116         /* Flush the CS. */
 117         ws->cs_flush(cs, flags, &ctx->last_gfx_fence,
 118                      ctx->screen->b.cs_count++);
 119         ctx->b.rings.gfx.flushing = false;
 120
 121         if (fence)
 122                 ws->fence_reference(fence, ctx->last_gfx_fence);
 123
 124         /* Check VM faults if needed. */
 125         if (ctx->screen->b.debug_flags & DBG_CHECK_VM)
 126                 si_check_vm_faults(ctx);
 127
 128         si_begin_new_cs(ctx);
 129 }
 130
 131 void si_begin_new_cs(struct si_context *ctx)
 132 {
 133         if (ctx->is_debug) {
 134                 uint32_t zero = 0;
 135
 136                 /* Create a buffer used for writing trace IDs and initialize it to 0. */
 137                 assert(!ctx->trace_buf);
 138                 ctx->trace_buf = (struct r600_resource*)
 139                                  pipe_buffer_create(ctx->b.b.screen, PIPE_BIND_CUSTOM,
 140                                                     PIPE_USAGE_STAGING, 4);
 141                 if (ctx->trace_buf)
 142                         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
 143                                                     0, sizeof(zero), &zero);
 144                 ctx->trace_id = 0;
 145         }
 146
 147         if (ctx->trace_buf)
 148                 si_trace_emit(ctx);
 149
 150         /* Flush read caches at the beginning of CS. */
 151         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
 152                         SI_CONTEXT_INV_VMEM_L1 |
 153                         SI_CONTEXT_INV_GLOBAL_L2 |
 154                         SI_CONTEXT_INV_SMEM_L1 |
 155                         SI_CONTEXT_INV_ICACHE;
 156
 157         /* set all valid group as dirty so they get reemited on
 158          * next draw command
 159          */
 160         si_pm4_reset_emitted(ctx);
 161
 162         /* The CS initialization should be emitted before everything else. */
 163         si_pm4_emit(ctx, ctx->init_config);
 164
 165         ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
 166         ctx->framebuffer.dirty_zsbuf = true;
 167         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 168
 169         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 170         si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 171         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs);
 172         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 173         si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 174         si_mark_atom_dirty(ctx, &ctx->cb_target_mask);
 175         si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 176         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 177         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 178         si_mark_atom_dirty(ctx, &ctx->spi_map);
 179         si_mark_atom_dirty(ctx, &ctx->spi_ps_input);
 180         si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
 181         si_all_descriptors_begin_new_cs(ctx);
 182
 183         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 184         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 185         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 186         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 187
 188         r600_postflush_resume_features(&ctx->b);
 189
 190         ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 191
 192         /* Invalidate various draw states so that they are emitted before
 193          * the first draw call. */
 194         si_invalidate_draw_sh_constants(ctx);
 195         ctx->last_primitive_restart_en = -1;
 196         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 197         ctx->last_gs_out_prim = -1;
 198         ctx->last_prim = -1;
 199         ctx->last_multi_vgt_param = -1;
 200         ctx->last_ls_hs_config = -1;
 201         ctx->last_rast_prim = -1;
 202         ctx->last_sc_line_stipple = ~0;
 203         ctx->emit_scratch_reloc = true;
 204         ctx->last_ls = NULL;
 205         ctx->last_tcs = NULL;
 206         ctx->last_tes_sh_base = -1;
 207         ctx->last_num_tcs_input_cp = -1;
 208 }