src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "si_pipe.h"
  28
  29 /* initialize */
  30 void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
  31                         boolean count_draw_in)
  32 {
  33         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
  34         int i;
  35
  36         /* There are two memory usage counters in the winsys for all buffers
  37          * that have been added (cs_add_reloc) and two counters in the pipe
  38          * driver for those that haven't been added yet.
  39          * */
  40         if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) {
  41                 ctx->b.gtt = 0;
  42                 ctx->b.vram = 0;
  43                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  44                 return;
  45         }
  46         ctx->b.gtt = 0;
  47         ctx->b.vram = 0;
  48
  49         /* If the CS is sufficiently large, don't count the space needed
  50          * and just flush if there is less than 8096 dwords left.
  51          */
  52         if (cs->max_dw >= 24 * 1024) {
  53                 if (cs->cdw > cs->max_dw - 8 * 1024)
  54                         ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  55                 return;
  56         }
  57
  58         /* The number of dwords we already used in the CS so far. */
  59         num_dw += cs->cdw;
  60
  61         if (count_draw_in) {
  62                 for (i = 0; i < SI_NUM_ATOMS(ctx); i++) {
  63                         if (ctx->atoms.array[i]->dirty) {
  64                                 num_dw += ctx->atoms.array[i]->num_dw;
  65                         }
  66                 }
  67
  68                 /* The number of dwords all the dirty states would take. */
  69                 num_dw += si_pm4_dirty_dw(ctx);
  70
  71                 /* The upper-bound of how much a draw command would take. */
  72                 num_dw += SI_MAX_DRAW_CS_DWORDS;
  73         }
  74
  75         /* Count in queries_suspend. */
  76         num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend +
  77                   ctx->b.num_cs_dw_timer_queries_suspend;
  78
  79         /* Count in streamout_end at the end of CS. */
  80         if (ctx->b.streamout.begin_emitted) {
  81                 num_dw += ctx->b.streamout.num_dw_for_end;
  82         }
  83
  84         /* Count in render_condition(NULL) at the end of CS. */
  85         if (ctx->b.predicate_drawing) {
  86                 num_dw += 3;
  87         }
  88
  89         /* Count in framebuffer cache flushes at the end of CS. */
  90         num_dw += ctx->atoms.s.cache_flush->num_dw;
  91
  92         if (ctx->screen->b.trace_bo)
  93                 num_dw += SI_TRACE_CS_DWORDS * 2;
  94
  95         /* Flush if there's not enough space. */
  96         if (num_dw > cs->max_dw) {
  97                 ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  98         }
  99 }
 100
 101 void si_context_gfx_flush(void *context, unsigned flags,
 102                           struct pipe_fence_handle **fence)
 103 {
 104         struct si_context *ctx = context;
 105         struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
 106         struct radeon_winsys *ws = ctx->b.ws;
 107
 108         if (cs->cdw == ctx->b.initial_gfx_cs_size &&
 109             (!fence || ctx->last_gfx_fence)) {
 110                 if (fence)
 111                         ws->fence_reference(fence, ctx->last_gfx_fence);
 112                 if (!(flags & RADEON_FLUSH_ASYNC))
 113                         ws->cs_sync_flush(cs);
 114                 return;
 115         }
 116
 117         ctx->b.rings.gfx.flushing = true;
 118
 119         r600_preflush_suspend_features(&ctx->b);
 120
 121         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
 122                         SI_CONTEXT_INV_TC_L1 |
 123                         SI_CONTEXT_INV_TC_L2 |
 124                         /* this is probably not needed anymore */
 125                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 126         si_emit_cache_flush(&ctx->b, NULL);
 127
 128         /* force to keep tiling flags */
 129         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 130
 131         if (ctx->trace_buf)
 132                 si_trace_emit(ctx);
 133
 134         /* Save the IB for debug contexts. */
 135         if (ctx->is_debug) {
 136                 free(ctx->last_ib);
 137                 ctx->last_ib_dw_size = cs->cdw;
 138                 ctx->last_ib = malloc(cs->cdw * 4);
 139                 memcpy(ctx->last_ib, cs->buf, cs->cdw * 4);
 140                 r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
 141                 r600_resource_reference(&ctx->trace_buf, NULL);
 142         }
 143
 144         /* Flush the CS. */
 145         ws->cs_flush(cs, flags, &ctx->last_gfx_fence,
 146                      ctx->screen->b.cs_count++);
 147         ctx->b.rings.gfx.flushing = false;
 148
 149         if (fence)
 150                 ws->fence_reference(fence, ctx->last_gfx_fence);
 151
 152         si_begin_new_cs(ctx);
 153 }
 154
 155 void si_begin_new_cs(struct si_context *ctx)
 156 {
 157         if (ctx->is_debug) {
 158                 uint32_t zero = 0;
 159
 160                 /* Create a buffer used for writing trace IDs and initialize it to 0. */
 161                 assert(!ctx->trace_buf);
 162                 ctx->trace_buf = (struct r600_resource*)
 163                                  pipe_buffer_create(ctx->b.b.screen, PIPE_BIND_CUSTOM,
 164                                                     PIPE_USAGE_STAGING, 4);
 165                 if (ctx->trace_buf)
 166                         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
 167                                                     0, sizeof(zero), &zero);
 168                 ctx->trace_id = 0;
 169         }
 170
 171         if (ctx->trace_buf)
 172                 si_trace_emit(ctx);
 173
 174         /* Flush read caches at the beginning of CS. */
 175         ctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
 176                         SI_CONTEXT_INV_TC_L1 |
 177                         SI_CONTEXT_INV_TC_L2 |
 178                         SI_CONTEXT_INV_KCACHE |
 179                         SI_CONTEXT_INV_ICACHE;
 180
 181         /* set all valid group as dirty so they get reemited on
 182          * next draw command
 183          */
 184         si_pm4_reset_emitted(ctx);
 185
 186         /* The CS initialization should be emitted before everything else. */
 187         si_pm4_emit(ctx, ctx->init_config);
 188
 189         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 190         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 191         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs);
 192         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 193         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 194         si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
 195         si_all_descriptors_begin_new_cs(ctx);
 196
 197         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 198         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 199         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 200         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 201
 202         r600_postflush_resume_features(&ctx->b);
 203
 204         ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 205
 206         /* Invalidate various draw states so that they are emitted before
 207          * the first draw call. */
 208         si_invalidate_draw_sh_constants(ctx);
 209         ctx->last_primitive_restart_en = -1;
 210         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 211         ctx->last_gs_out_prim = -1;
 212         ctx->last_prim = -1;
 213         ctx->last_multi_vgt_param = -1;
 214         ctx->last_ls_hs_config = -1;
 215         ctx->last_rast_prim = -1;
 216         ctx->last_sc_line_stipple = ~0;
 217         ctx->emit_scratch_reloc = true;
 218         ctx->last_ls = NULL;
 219         ctx->last_tcs = NULL;
 220         ctx->last_tes_sh_base = -1;
 221         ctx->last_num_tcs_input_cp = -1;
 222 }