2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Nicolai Hähnle <nicolai.haehnle@amd.com>
28 #include "radeon/r600_cs.h"
29 #include "radeon/r600_query.h"
30 #include "radeon/r600_pipe_common.h"
31 #include "util/u_memory.h"
36 enum si_pc_reg_layout
{
37 /* All secondary selector dwords follow as one block after the primary
38 * selector dwords for the counters that have secondary selectors.
40 SI_PC_MULTI_BLOCK
= 0,
42 /* Each secondary selector dword follows immediately afters the
43 * corresponding primary.
45 SI_PC_MULTI_ALTERNATE
= 1,
47 /* All secondary selector dwords follow as one block after all primary
52 /* Free-form arrangement of selector registers. */
53 SI_PC_MULTI_CUSTOM
= 3,
57 /* Registers are laid out in decreasing rather than increasing order. */
58 SI_PC_REG_REVERSE
= 4,
63 struct si_pc_block_base
{
65 unsigned num_counters
;
79 struct si_pc_block_base
*b
;
84 /* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
85 * performance counter group IDs.
87 static const char * const si_pc_shader_type_suffixes
[] = {
88 "", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
91 static const unsigned si_pc_shader_type_bits
[] = {
102 static struct si_pc_block_base cik_CB
= {
105 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
,
107 .select0
= R_037000_CB_PERFCOUNTER_FILTER
,
108 .counter0_lo
= R_035018_CB_PERFCOUNTER0_LO
,
111 .layout
= SI_PC_MULTI_ALTERNATE
,
114 static unsigned cik_CPC_select
[] = {
115 R_036024_CPC_PERFCOUNTER0_SELECT
,
116 R_036010_CPC_PERFCOUNTER0_SELECT1
,
117 R_03600C_CPC_PERFCOUNTER1_SELECT
,
119 static struct si_pc_block_base cik_CPC
= {
123 .select
= cik_CPC_select
,
124 .counter0_lo
= R_034018_CPC_PERFCOUNTER0_LO
,
126 .layout
= SI_PC_MULTI_CUSTOM
| SI_PC_REG_REVERSE
,
129 static struct si_pc_block_base cik_CPF
= {
133 .select0
= R_03601C_CPF_PERFCOUNTER0_SELECT
,
134 .counter0_lo
= R_034028_CPF_PERFCOUNTER0_LO
,
136 .layout
= SI_PC_MULTI_ALTERNATE
| SI_PC_REG_REVERSE
,
139 static struct si_pc_block_base cik_CPG
= {
143 .select0
= R_036008_CPG_PERFCOUNTER0_SELECT
,
144 .counter0_lo
= R_034008_CPG_PERFCOUNTER0_LO
,
146 .layout
= SI_PC_MULTI_ALTERNATE
| SI_PC_REG_REVERSE
,
149 static struct si_pc_block_base cik_DB
= {
152 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
,
154 .select0
= R_037100_DB_PERFCOUNTER0_SELECT
,
155 .counter0_lo
= R_035100_DB_PERFCOUNTER0_LO
,
156 .num_multi
= 3, // really only 2, but there's a gap between registers
157 .layout
= SI_PC_MULTI_ALTERNATE
,
160 static struct si_pc_block_base cik_GDS
= {
164 .select0
= R_036A00_GDS_PERFCOUNTER0_SELECT
,
165 .counter0_lo
= R_034A00_GDS_PERFCOUNTER0_LO
,
167 .layout
= SI_PC_MULTI_TAIL
,
170 static unsigned cik_GRBM_counters
[] = {
171 R_034100_GRBM_PERFCOUNTER0_LO
,
172 R_03410C_GRBM_PERFCOUNTER1_LO
,
174 static struct si_pc_block_base cik_GRBM
= {
178 .select0
= R_036100_GRBM_PERFCOUNTER0_SELECT
,
179 .counters
= cik_GRBM_counters
,
182 static struct si_pc_block_base cik_GRBMSE
= {
186 .select0
= R_036108_GRBM_SE0_PERFCOUNTER_SELECT
,
187 .counter0_lo
= R_034114_GRBM_SE0_PERFCOUNTER_LO
,
190 static struct si_pc_block_base cik_IA
= {
194 .select0
= R_036210_IA_PERFCOUNTER0_SELECT
,
195 .counter0_lo
= R_034220_IA_PERFCOUNTER0_LO
,
197 .layout
= SI_PC_MULTI_TAIL
,
200 static struct si_pc_block_base cik_PA_SC
= {
203 .flags
= R600_PC_BLOCK_SE
,
205 .select0
= R_036500_PA_SC_PERFCOUNTER0_SELECT
,
206 .counter0_lo
= R_034500_PA_SC_PERFCOUNTER0_LO
,
208 .layout
= SI_PC_MULTI_ALTERNATE
,
211 static struct si_pc_block_base cik_PA_SU
= {
214 .flags
= R600_PC_BLOCK_SE
,
216 .select0
= R_036400_PA_SU_PERFCOUNTER0_SELECT
,
217 .counter0_lo
= R_034400_PA_SU_PERFCOUNTER0_LO
,
219 .layout
= SI_PC_MULTI_ALTERNATE
,
222 static struct si_pc_block_base cik_SPI
= {
225 .flags
= R600_PC_BLOCK_SE
,
227 .select0
= R_036600_SPI_PERFCOUNTER0_SELECT
,
228 .counter0_lo
= R_034604_SPI_PERFCOUNTER0_LO
,
230 .layout
= SI_PC_MULTI_BLOCK
,
233 static struct si_pc_block_base cik_SQ
= {
236 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_SHADER
,
238 .select0
= R_036700_SQ_PERFCOUNTER0_SELECT
,
239 .select_or
= S_036700_SQC_BANK_MASK(15) |
240 S_036700_SQC_CLIENT_MASK(15) |
241 S_036700_SIMD_MASK(15),
242 .counter0_lo
= R_034700_SQ_PERFCOUNTER0_LO
,
245 static struct si_pc_block_base cik_SX
= {
248 .flags
= R600_PC_BLOCK_SE
,
250 .select0
= R_036900_SX_PERFCOUNTER0_SELECT
,
251 .counter0_lo
= R_034900_SX_PERFCOUNTER0_LO
,
253 .layout
= SI_PC_MULTI_TAIL
,
256 static struct si_pc_block_base cik_TA
= {
259 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
261 .select0
= R_036B00_TA_PERFCOUNTER0_SELECT
,
262 .counter0_lo
= R_034B00_TA_PERFCOUNTER0_LO
,
264 .layout
= SI_PC_MULTI_ALTERNATE
,
267 static struct si_pc_block_base cik_TD
= {
270 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
272 .select0
= R_036C00_TD_PERFCOUNTER0_SELECT
,
273 .counter0_lo
= R_034C00_TD_PERFCOUNTER0_LO
,
275 .layout
= SI_PC_MULTI_ALTERNATE
,
278 static struct si_pc_block_base cik_TCA
= {
281 .flags
= R600_PC_BLOCK_INSTANCE_GROUPS
,
283 .select0
= R_036E40_TCA_PERFCOUNTER0_SELECT
,
284 .counter0_lo
= R_034E40_TCA_PERFCOUNTER0_LO
,
286 .layout
= SI_PC_MULTI_ALTERNATE
,
289 static struct si_pc_block_base cik_TCC
= {
292 .flags
= R600_PC_BLOCK_INSTANCE_GROUPS
,
294 .select0
= R_036E00_TCC_PERFCOUNTER0_SELECT
,
295 .counter0_lo
= R_034E00_TCC_PERFCOUNTER0_LO
,
297 .layout
= SI_PC_MULTI_ALTERNATE
,
300 static struct si_pc_block_base cik_TCP
= {
303 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
305 .select0
= R_036D00_TCP_PERFCOUNTER0_SELECT
,
306 .counter0_lo
= R_034D00_TCP_PERFCOUNTER0_LO
,
308 .layout
= SI_PC_MULTI_ALTERNATE
,
311 static struct si_pc_block_base cik_VGT
= {
314 .flags
= R600_PC_BLOCK_SE
,
316 .select0
= R_036230_VGT_PERFCOUNTER0_SELECT
,
317 .counter0_lo
= R_034240_VGT_PERFCOUNTER0_LO
,
319 .layout
= SI_PC_MULTI_TAIL
,
322 static struct si_pc_block_base cik_WD
= {
326 .select0
= R_036200_WD_PERFCOUNTER0_SELECT
,
327 .counter0_lo
= R_034200_WD_PERFCOUNTER0_LO
,
330 static struct si_pc_block_base cik_MC
= {
334 .layout
= SI_PC_FAKE
,
337 static struct si_pc_block_base cik_SRBM
= {
341 .layout
= SI_PC_FAKE
,
344 /* Both the number of instances and selectors varies between chips of the same
345 * class. We only differentiate by class here and simply expose the maximum
346 * number over all chips in a class.
348 * Unfortunately, GPUPerfStudio uses the order of performance counter groups
349 * blindly once it believes it has identified the hardware, so the order of
350 * blocks here matters.
352 static struct si_pc_block groups_CIK
[] = {
363 { &cik_TA
, 111, 11 },
365 { &cik_TCC
, 160, 16 },
367 { &cik_TCP
, 154, 11 },
379 static struct si_pc_block groups_VI
[] = {
390 { &cik_TA
, 119, 16 },
392 { &cik_TCC
, 192, 16 },
394 { &cik_TCP
, 180, 16 },
406 static void si_pc_get_size(struct r600_perfcounter_block
*group
,
407 unsigned count
, unsigned *selectors
,
408 unsigned *num_select_dw
, unsigned *num_read_dw
)
410 struct si_pc_block
*sigroup
= (struct si_pc_block
*)group
->data
;
411 struct si_pc_block_base
*regs
= sigroup
->b
;
412 unsigned layout_multi
= regs
->layout
& SI_PC_MULTI_MASK
;
414 if (regs
->layout
& SI_PC_FAKE
) {
416 } else if (layout_multi
== SI_PC_MULTI_BLOCK
) {
417 if (count
< regs
->num_multi
)
418 *num_select_dw
= 2 * (count
+ 2) + regs
->num_prelude
;
420 *num_select_dw
= 2 + count
+ regs
->num_multi
+ regs
->num_prelude
;
421 } else if (layout_multi
== SI_PC_MULTI_TAIL
) {
422 *num_select_dw
= 4 + count
+ MIN2(count
, regs
->num_multi
) + regs
->num_prelude
;
423 } else if (layout_multi
== SI_PC_MULTI_CUSTOM
) {
424 assert(regs
->num_prelude
== 0);
425 *num_select_dw
= 3 * (count
+ MIN2(count
, regs
->num_multi
));
427 assert(layout_multi
== SI_PC_MULTI_ALTERNATE
);
429 *num_select_dw
= 2 + count
+ MIN2(count
, regs
->num_multi
) + regs
->num_prelude
;
432 *num_read_dw
= 6 * count
;
435 static void si_pc_emit_instance(struct r600_common_context
*ctx
,
436 int se
, int instance
)
438 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
439 unsigned value
= S_030800_SH_BROADCAST_WRITES(1);
442 value
|= S_030800_SE_INDEX(se
);
444 value
|= S_030800_SE_BROADCAST_WRITES(1);
448 value
|= S_030800_INSTANCE_INDEX(instance
);
450 value
|= S_030800_INSTANCE_BROADCAST_WRITES(1);
453 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
, value
);
456 static void si_pc_emit_shaders(struct r600_common_context
*ctx
,
459 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
461 radeon_set_uconfig_reg_seq(cs
, R_036780_SQ_PERFCOUNTER_CTRL
, 2);
462 radeon_emit(cs
, shaders
& 0x7f);
463 radeon_emit(cs
, 0xffffffff);
466 static void si_pc_emit_select(struct r600_common_context
*ctx
,
467 struct r600_perfcounter_block
*group
,
468 unsigned count
, unsigned *selectors
)
470 struct si_pc_block
*sigroup
= (struct si_pc_block
*)group
->data
;
471 struct si_pc_block_base
*regs
= sigroup
->b
;
472 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
474 unsigned layout_multi
= regs
->layout
& SI_PC_MULTI_MASK
;
477 assert(count
<= regs
->num_counters
);
479 if (regs
->layout
& SI_PC_FAKE
)
482 if (layout_multi
== SI_PC_MULTI_BLOCK
) {
483 assert(!(regs
->layout
& SI_PC_REG_REVERSE
));
485 dw
= count
+ regs
->num_prelude
;
486 if (count
>= regs
->num_multi
)
487 dw
+= regs
->num_multi
;
488 radeon_set_uconfig_reg_seq(cs
, regs
->select0
, dw
);
489 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
491 for (idx
= 0; idx
< MIN2(count
, regs
->num_multi
); ++idx
)
492 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
494 if (count
< regs
->num_multi
) {
496 regs
->select0
+ 4 * regs
->num_multi
;
497 radeon_set_uconfig_reg_seq(cs
, select1
, count
);
500 for (idx
= 0; idx
< MIN2(count
, regs
->num_multi
); ++idx
)
503 if (count
> regs
->num_multi
) {
504 for (idx
= regs
->num_multi
; idx
< count
; ++idx
)
505 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
507 } else if (layout_multi
== SI_PC_MULTI_TAIL
) {
508 unsigned select1
, select1_count
;
510 assert(!(regs
->layout
& SI_PC_REG_REVERSE
));
512 radeon_set_uconfig_reg_seq(cs
, regs
->select0
, count
+ regs
->num_prelude
);
513 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
515 for (idx
= 0; idx
< count
; ++idx
)
516 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
518 select1
= regs
->select0
+ 4 * regs
->num_counters
;
519 select1_count
= MIN2(count
, regs
->num_multi
);
520 radeon_set_uconfig_reg_seq(cs
, select1
, select1_count
);
521 for (idx
= 0; idx
< select1_count
; ++idx
)
523 } else if (layout_multi
== SI_PC_MULTI_CUSTOM
) {
524 unsigned *reg
= regs
->select
;
525 for (idx
= 0; idx
< count
; ++idx
) {
526 radeon_set_uconfig_reg(cs
, *reg
++, selectors
[idx
] | regs
->select_or
);
527 if (idx
< regs
->num_multi
)
528 radeon_set_uconfig_reg(cs
, *reg
++, 0);
531 assert(layout_multi
== SI_PC_MULTI_ALTERNATE
);
533 unsigned reg_base
= regs
->select0
;
534 unsigned reg_count
= count
+ MIN2(count
, regs
->num_multi
);
535 reg_count
+= regs
->num_prelude
;
537 if (!(regs
->layout
& SI_PC_REG_REVERSE
)) {
538 radeon_set_uconfig_reg_seq(cs
, reg_base
, reg_count
);
540 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
542 for (idx
= 0; idx
< count
; ++idx
) {
543 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
544 if (idx
< regs
->num_multi
)
548 reg_base
-= (reg_count
- 1) * 4;
549 radeon_set_uconfig_reg_seq(cs
, reg_base
, reg_count
);
551 for (idx
= count
; idx
> 0; --idx
) {
552 if (idx
<= regs
->num_multi
)
554 radeon_emit(cs
, selectors
[idx
- 1] | regs
->select_or
);
556 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
562 static void si_pc_emit_start(struct r600_common_context
*ctx
,
563 struct r600_resource
*buffer
, uint64_t va
)
565 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
567 radeon_add_to_buffer_list(ctx
, &ctx
->gfx
, buffer
,
568 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
570 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
571 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
572 COPY_DATA_DST_SEL(COPY_DATA_MEM
));
573 radeon_emit(cs
, 1); /* immediate */
574 radeon_emit(cs
, 0); /* unused */
576 radeon_emit(cs
, va
>> 32);
578 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
579 S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET
));
580 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
581 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_START
) | EVENT_INDEX(0));
582 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
583 S_036020_PERFMON_STATE(V_036020_START_COUNTING
));
586 /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
587 * do it again in here. */
588 static void si_pc_emit_stop(struct r600_common_context
*ctx
,
589 struct r600_resource
*buffer
, uint64_t va
)
591 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
593 if (ctx
->screen
->chip_class
== CIK
) {
594 /* Workaround for cache flush problems: send two EOP events. */
595 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
596 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) |
599 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
600 radeon_emit(cs
, 0); /* immediate data */
601 radeon_emit(cs
, 0); /* unused */
604 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
605 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) |
608 radeon_emit(cs
, (va
>> 32) | EOP_DATA_SEL(1));
609 radeon_emit(cs
, 0); /* immediate data */
610 radeon_emit(cs
, 0); /* unused */
612 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
613 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
615 radeon_emit(cs
, va
>> 32);
616 radeon_emit(cs
, 0); /* reference value */
617 radeon_emit(cs
, 0xffffffff); /* mask */
618 radeon_emit(cs
, 4); /* poll interval */
620 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
621 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE
) | EVENT_INDEX(0));
622 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
623 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP
) | EVENT_INDEX(0));
624 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
625 S_036020_PERFMON_STATE(V_036020_STOP_COUNTING
) |
626 S_036020_PERFMON_SAMPLE_ENABLE(1));
629 static void si_pc_emit_read(struct r600_common_context
*ctx
,
630 struct r600_perfcounter_block
*group
,
631 unsigned count
, unsigned *selectors
,
632 struct r600_resource
*buffer
, uint64_t va
)
634 struct si_pc_block
*sigroup
= (struct si_pc_block
*)group
->data
;
635 struct si_pc_block_base
*regs
= sigroup
->b
;
636 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
638 unsigned reg
= regs
->counter0_lo
;
639 unsigned reg_delta
= 8;
641 if (!(regs
->layout
& SI_PC_FAKE
)) {
642 if (regs
->layout
& SI_PC_REG_REVERSE
)
643 reg_delta
= -reg_delta
;
645 for (idx
= 0; idx
< count
; ++idx
) {
647 reg
= regs
->counters
[idx
];
649 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
650 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_PERF
) |
651 COPY_DATA_DST_SEL(COPY_DATA_MEM
));
652 radeon_emit(cs
, reg
>> 2);
653 radeon_emit(cs
, 0); /* unused */
655 radeon_emit(cs
, va
>> 32);
660 for (idx
= 0; idx
< count
; ++idx
) {
661 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
662 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
663 COPY_DATA_DST_SEL(COPY_DATA_MEM
));
664 radeon_emit(cs
, 0); /* immediate */
665 radeon_emit(cs
, 0); /* unused */
667 radeon_emit(cs
, va
>> 32);
673 static void si_pc_cleanup(struct r600_common_screen
*rscreen
)
675 r600_perfcounters_do_destroy(rscreen
->perfcounters
);
676 rscreen
->perfcounters
= NULL
;
679 void si_init_perfcounters(struct si_screen
*screen
)
681 struct r600_perfcounters
*pc
;
682 struct si_pc_block
*blocks
;
686 switch (screen
->b
.chip_class
) {
689 num_blocks
= ARRAY_SIZE(groups_CIK
);
693 num_blocks
= ARRAY_SIZE(groups_VI
);
697 return; /* not implemented */
700 if (screen
->b
.info
.max_sh_per_se
!= 1) {
701 /* This should not happen on non-SI chips. */
702 fprintf(stderr
, "si_init_perfcounters: max_sh_per_se = %d not "
703 "supported (inaccurate performance counters)\n",
704 screen
->b
.info
.max_sh_per_se
);
707 pc
= CALLOC_STRUCT(r600_perfcounters
);
711 pc
->num_start_cs_dwords
= 14;
712 pc
->num_stop_cs_dwords
= 20;
713 pc
->num_instance_cs_dwords
= 3;
714 pc
->num_shaders_cs_dwords
= 4;
716 if (screen
->b
.chip_class
== CIK
) {
717 pc
->num_stop_cs_dwords
+= 6;
720 pc
->num_shader_types
= ARRAY_SIZE(si_pc_shader_type_bits
);
721 pc
->shader_type_suffixes
= si_pc_shader_type_suffixes
;
722 pc
->shader_type_bits
= si_pc_shader_type_bits
;
724 pc
->get_size
= si_pc_get_size
;
725 pc
->emit_instance
= si_pc_emit_instance
;
726 pc
->emit_shaders
= si_pc_emit_shaders
;
727 pc
->emit_select
= si_pc_emit_select
;
728 pc
->emit_start
= si_pc_emit_start
;
729 pc
->emit_stop
= si_pc_emit_stop
;
730 pc
->emit_read
= si_pc_emit_read
;
731 pc
->cleanup
= si_pc_cleanup
;
733 if (!r600_perfcounters_init(pc
, num_blocks
))
736 for (i
= 0; i
< num_blocks
; ++i
) {
737 struct si_pc_block
*block
= &blocks
[i
];
738 unsigned instances
= block
->instances
;
740 if (!strcmp(block
->b
->name
, "IA")) {
741 if (screen
->b
.info
.max_se
> 2)
745 r600_perfcounters_add_block(&screen
->b
, pc
,
748 block
->b
->num_counters
,
754 screen
->b
.perfcounters
= pc
;
758 r600_perfcounters_do_destroy(pc
);