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[mesa.git] / src / gallium / drivers / radeonsi / si_perfcounter.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Nicolai Hähnle <nicolai.haehnle@amd.com>
25 *
26 */
27
28 #include "radeon/r600_cs.h"
29 #include "radeon/r600_query.h"
30 #include "util/u_memory.h"
31
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 enum si_pc_reg_layout {
36 /* All secondary selector dwords follow as one block after the primary
37 * selector dwords for the counters that have secondary selectors.
38 */
39 SI_PC_MULTI_BLOCK = 0,
40
41 /* Each secondary selector dword follows immediately afters the
42 * corresponding primary.
43 */
44 SI_PC_MULTI_ALTERNATE = 1,
45
46 /* All secondary selector dwords follow as one block after all primary
47 * selector dwords.
48 */
49 SI_PC_MULTI_TAIL = 2,
50
51 /* Free-form arrangement of selector registers. */
52 SI_PC_MULTI_CUSTOM = 3,
53
54 SI_PC_MULTI_MASK = 3,
55
56 /* Registers are laid out in decreasing rather than increasing order. */
57 SI_PC_REG_REVERSE = 4,
58
59 SI_PC_FAKE = 8,
60 };
61
62 struct si_pc_block_base {
63 const char *name;
64 unsigned num_counters;
65 unsigned flags;
66
67 unsigned select_or;
68 unsigned select0;
69 unsigned counter0_lo;
70 unsigned *select;
71 unsigned *counters;
72 unsigned num_multi;
73 unsigned num_prelude;
74 unsigned layout;
75 };
76
77 struct si_pc_block {
78 struct si_pc_block_base *b;
79 unsigned selectors;
80 unsigned instances;
81 };
82
83 /* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
84 * performance counter group IDs.
85 */
86 static const char * const si_pc_shader_type_suffixes[] = {
87 "", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
88 };
89
90 static const unsigned si_pc_shader_type_bits[] = {
91 0x7f,
92 S_036780_ES_EN(1),
93 S_036780_GS_EN(1),
94 S_036780_VS_EN(1),
95 S_036780_PS_EN(1),
96 S_036780_LS_EN(1),
97 S_036780_HS_EN(1),
98 S_036780_CS_EN(1),
99 };
100
101 static struct si_pc_block_base cik_CB = {
102 .name = "CB",
103 .num_counters = 4,
104 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
105
106 .select0 = R_037000_CB_PERFCOUNTER_FILTER,
107 .counter0_lo = R_035018_CB_PERFCOUNTER0_LO,
108 .num_multi = 1,
109 .num_prelude = 1,
110 .layout = SI_PC_MULTI_ALTERNATE,
111 };
112
113 static unsigned cik_CPC_select[] = {
114 R_036024_CPC_PERFCOUNTER0_SELECT,
115 R_036010_CPC_PERFCOUNTER0_SELECT1,
116 R_03600C_CPC_PERFCOUNTER1_SELECT,
117 };
118 static struct si_pc_block_base cik_CPC = {
119 .name = "CPC",
120 .num_counters = 2,
121
122 .select = cik_CPC_select,
123 .counter0_lo = R_034018_CPC_PERFCOUNTER0_LO,
124 .num_multi = 1,
125 .layout = SI_PC_MULTI_CUSTOM | SI_PC_REG_REVERSE,
126 };
127
128 static struct si_pc_block_base cik_CPF = {
129 .name = "CPF",
130 .num_counters = 2,
131
132 .select0 = R_03601C_CPF_PERFCOUNTER0_SELECT,
133 .counter0_lo = R_034028_CPF_PERFCOUNTER0_LO,
134 .num_multi = 1,
135 .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
136 };
137
138 static struct si_pc_block_base cik_CPG = {
139 .name = "CPG",
140 .num_counters = 2,
141
142 .select0 = R_036008_CPG_PERFCOUNTER0_SELECT,
143 .counter0_lo = R_034008_CPG_PERFCOUNTER0_LO,
144 .num_multi = 1,
145 .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
146 };
147
148 static struct si_pc_block_base cik_DB = {
149 .name = "DB",
150 .num_counters = 4,
151 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
152
153 .select0 = R_037100_DB_PERFCOUNTER0_SELECT,
154 .counter0_lo = R_035100_DB_PERFCOUNTER0_LO,
155 .num_multi = 3, // really only 2, but there's a gap between registers
156 .layout = SI_PC_MULTI_ALTERNATE,
157 };
158
159 static struct si_pc_block_base cik_GDS = {
160 .name = "GDS",
161 .num_counters = 4,
162
163 .select0 = R_036A00_GDS_PERFCOUNTER0_SELECT,
164 .counter0_lo = R_034A00_GDS_PERFCOUNTER0_LO,
165 .num_multi = 1,
166 .layout = SI_PC_MULTI_TAIL,
167 };
168
169 static unsigned cik_GRBM_counters[] = {
170 R_034100_GRBM_PERFCOUNTER0_LO,
171 R_03410C_GRBM_PERFCOUNTER1_LO,
172 };
173 static struct si_pc_block_base cik_GRBM = {
174 .name = "GRBM",
175 .num_counters = 2,
176
177 .select0 = R_036100_GRBM_PERFCOUNTER0_SELECT,
178 .counters = cik_GRBM_counters,
179 };
180
181 static struct si_pc_block_base cik_GRBMSE = {
182 .name = "GRBMSE",
183 .num_counters = 4,
184
185 .select0 = R_036108_GRBM_SE0_PERFCOUNTER_SELECT,
186 .counter0_lo = R_034114_GRBM_SE0_PERFCOUNTER_LO,
187 };
188
189 static struct si_pc_block_base cik_IA = {
190 .name = "IA",
191 .num_counters = 4,
192
193 .select0 = R_036210_IA_PERFCOUNTER0_SELECT,
194 .counter0_lo = R_034220_IA_PERFCOUNTER0_LO,
195 .num_multi = 1,
196 .layout = SI_PC_MULTI_TAIL,
197 };
198
199 static struct si_pc_block_base cik_PA_SC = {
200 .name = "PA_SC",
201 .num_counters = 8,
202 .flags = R600_PC_BLOCK_SE,
203
204 .select0 = R_036500_PA_SC_PERFCOUNTER0_SELECT,
205 .counter0_lo = R_034500_PA_SC_PERFCOUNTER0_LO,
206 .num_multi = 1,
207 .layout = SI_PC_MULTI_ALTERNATE,
208 };
209
210 /* According to docs, PA_SU counters are only 48 bits wide. */
211 static struct si_pc_block_base cik_PA_SU = {
212 .name = "PA_SU",
213 .num_counters = 4,
214 .flags = R600_PC_BLOCK_SE,
215
216 .select0 = R_036400_PA_SU_PERFCOUNTER0_SELECT,
217 .counter0_lo = R_034400_PA_SU_PERFCOUNTER0_LO,
218 .num_multi = 2,
219 .layout = SI_PC_MULTI_ALTERNATE,
220 };
221
222 static struct si_pc_block_base cik_SPI = {
223 .name = "SPI",
224 .num_counters = 6,
225 .flags = R600_PC_BLOCK_SE,
226
227 .select0 = R_036600_SPI_PERFCOUNTER0_SELECT,
228 .counter0_lo = R_034604_SPI_PERFCOUNTER0_LO,
229 .num_multi = 4,
230 .layout = SI_PC_MULTI_BLOCK,
231 };
232
233 static struct si_pc_block_base cik_SQ = {
234 .name = "SQ",
235 .num_counters = 16,
236 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_SHADER,
237
238 .select0 = R_036700_SQ_PERFCOUNTER0_SELECT,
239 .select_or = S_036700_SQC_BANK_MASK(15) |
240 S_036700_SQC_CLIENT_MASK(15) |
241 S_036700_SIMD_MASK(15),
242 .counter0_lo = R_034700_SQ_PERFCOUNTER0_LO,
243 };
244
245 static struct si_pc_block_base cik_SX = {
246 .name = "SX",
247 .num_counters = 4,
248 .flags = R600_PC_BLOCK_SE,
249
250 .select0 = R_036900_SX_PERFCOUNTER0_SELECT,
251 .counter0_lo = R_034900_SX_PERFCOUNTER0_LO,
252 .num_multi = 2,
253 .layout = SI_PC_MULTI_TAIL,
254 };
255
256 static struct si_pc_block_base cik_TA = {
257 .name = "TA",
258 .num_counters = 2,
259 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
260
261 .select0 = R_036B00_TA_PERFCOUNTER0_SELECT,
262 .counter0_lo = R_034B00_TA_PERFCOUNTER0_LO,
263 .num_multi = 1,
264 .layout = SI_PC_MULTI_ALTERNATE,
265 };
266
267 static struct si_pc_block_base cik_TD = {
268 .name = "TD",
269 .num_counters = 2,
270 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
271
272 .select0 = R_036C00_TD_PERFCOUNTER0_SELECT,
273 .counter0_lo = R_034C00_TD_PERFCOUNTER0_LO,
274 .num_multi = 1,
275 .layout = SI_PC_MULTI_ALTERNATE,
276 };
277
278 static struct si_pc_block_base cik_TCA = {
279 .name = "TCA",
280 .num_counters = 4,
281 .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
282
283 .select0 = R_036E40_TCA_PERFCOUNTER0_SELECT,
284 .counter0_lo = R_034E40_TCA_PERFCOUNTER0_LO,
285 .num_multi = 2,
286 .layout = SI_PC_MULTI_ALTERNATE,
287 };
288
289 static struct si_pc_block_base cik_TCC = {
290 .name = "TCC",
291 .num_counters = 4,
292 .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
293
294 .select0 = R_036E00_TCC_PERFCOUNTER0_SELECT,
295 .counter0_lo = R_034E00_TCC_PERFCOUNTER0_LO,
296 .num_multi = 2,
297 .layout = SI_PC_MULTI_ALTERNATE,
298 };
299
300 static struct si_pc_block_base cik_TCP = {
301 .name = "TCP",
302 .num_counters = 4,
303 .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
304
305 .select0 = R_036D00_TCP_PERFCOUNTER0_SELECT,
306 .counter0_lo = R_034D00_TCP_PERFCOUNTER0_LO,
307 .num_multi = 2,
308 .layout = SI_PC_MULTI_ALTERNATE,
309 };
310
311 static struct si_pc_block_base cik_VGT = {
312 .name = "VGT",
313 .num_counters = 4,
314 .flags = R600_PC_BLOCK_SE,
315
316 .select0 = R_036230_VGT_PERFCOUNTER0_SELECT,
317 .counter0_lo = R_034240_VGT_PERFCOUNTER0_LO,
318 .num_multi = 1,
319 .layout = SI_PC_MULTI_TAIL,
320 };
321
322 static struct si_pc_block_base cik_WD = {
323 .name = "WD",
324 .num_counters = 4,
325
326 .select0 = R_036200_WD_PERFCOUNTER0_SELECT,
327 .counter0_lo = R_034200_WD_PERFCOUNTER0_LO,
328 };
329
330 static struct si_pc_block_base cik_MC = {
331 .name = "MC",
332 .num_counters = 4,
333
334 .layout = SI_PC_FAKE,
335 };
336
337 static struct si_pc_block_base cik_SRBM = {
338 .name = "SRBM",
339 .num_counters = 2,
340
341 .layout = SI_PC_FAKE,
342 };
343
344 /* Both the number of instances and selectors varies between chips of the same
345 * class. We only differentiate by class here and simply expose the maximum
346 * number over all chips in a class.
347 *
348 * Unfortunately, GPUPerfStudio uses the order of performance counter groups
349 * blindly once it believes it has identified the hardware, so the order of
350 * blocks here matters.
351 */
352 static struct si_pc_block groups_CIK[] = {
353 { &cik_CB, 226, 4 },
354 { &cik_CPF, 17 },
355 { &cik_DB, 257, 4 },
356 { &cik_GRBM, 34 },
357 { &cik_GRBMSE, 15 },
358 { &cik_PA_SU, 153 },
359 { &cik_PA_SC, 395 },
360 { &cik_SPI, 186 },
361 { &cik_SQ, 252 },
362 { &cik_SX, 32 },
363 { &cik_TA, 111, 11 },
364 { &cik_TCA, 39, 2 },
365 { &cik_TCC, 160, 16 },
366 { &cik_TD, 55, 11 },
367 { &cik_TCP, 154, 11 },
368 { &cik_GDS, 121 },
369 { &cik_VGT, 140 },
370 { &cik_IA, 22 },
371 { &cik_MC, 22 },
372 { &cik_SRBM, 19 },
373 { &cik_WD, 22 },
374 { &cik_CPG, 46 },
375 { &cik_CPC, 22 },
376
377 };
378
379 static struct si_pc_block groups_VI[] = {
380 { &cik_CB, 396, 4 },
381 { &cik_CPF, 19 },
382 { &cik_DB, 257, 4 },
383 { &cik_GRBM, 34 },
384 { &cik_GRBMSE, 15 },
385 { &cik_PA_SU, 153 },
386 { &cik_PA_SC, 397 },
387 { &cik_SPI, 197 },
388 { &cik_SQ, 273 },
389 { &cik_SX, 34 },
390 { &cik_TA, 119, 16 },
391 { &cik_TCA, 35, 2 },
392 { &cik_TCC, 192, 16 },
393 { &cik_TD, 55, 16 },
394 { &cik_TCP, 180, 16 },
395 { &cik_GDS, 121 },
396 { &cik_VGT, 147 },
397 { &cik_IA, 24 },
398 { &cik_MC, 22 },
399 { &cik_SRBM, 27 },
400 { &cik_WD, 37 },
401 { &cik_CPG, 48 },
402 { &cik_CPC, 24 },
403
404 };
405
406 static struct si_pc_block groups_gfx9[] = {
407 { &cik_CB, 438, 4 },
408 { &cik_CPF, 32 },
409 { &cik_DB, 328, 4 },
410 { &cik_GRBM, 38 },
411 { &cik_GRBMSE, 16 },
412 { &cik_PA_SU, 292 },
413 { &cik_PA_SC, 491 },
414 { &cik_SPI, 196 },
415 { &cik_SQ, 374 },
416 { &cik_SX, 208 },
417 { &cik_TA, 119, 16 },
418 { &cik_TCA, 35, 2 },
419 { &cik_TCC, 256, 16 },
420 { &cik_TD, 57, 16 },
421 { &cik_TCP, 85, 16 },
422 { &cik_GDS, 121 },
423 { &cik_VGT, 148 },
424 { &cik_IA, 32 },
425 { &cik_WD, 58 },
426 { &cik_CPG, 59 },
427 { &cik_CPC, 35 },
428 };
429
430 static void si_pc_get_size(struct r600_perfcounter_block *group,
431 unsigned count, unsigned *selectors,
432 unsigned *num_select_dw, unsigned *num_read_dw)
433 {
434 struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
435 struct si_pc_block_base *regs = sigroup->b;
436 unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
437
438 if (regs->layout & SI_PC_FAKE) {
439 *num_select_dw = 0;
440 } else if (layout_multi == SI_PC_MULTI_BLOCK) {
441 if (count < regs->num_multi)
442 *num_select_dw = 2 * (count + 2) + regs->num_prelude;
443 else
444 *num_select_dw = 2 + count + regs->num_multi + regs->num_prelude;
445 } else if (layout_multi == SI_PC_MULTI_TAIL) {
446 *num_select_dw = 4 + count + MIN2(count, regs->num_multi) + regs->num_prelude;
447 } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
448 assert(regs->num_prelude == 0);
449 *num_select_dw = 3 * (count + MIN2(count, regs->num_multi));
450 } else {
451 assert(layout_multi == SI_PC_MULTI_ALTERNATE);
452
453 *num_select_dw = 2 + count + MIN2(count, regs->num_multi) + regs->num_prelude;
454 }
455
456 *num_read_dw = 6 * count;
457 }
458
459 static void si_pc_emit_instance(struct r600_common_context *ctx,
460 int se, int instance)
461 {
462 struct radeon_winsys_cs *cs = ctx->gfx.cs;
463 unsigned value = S_030800_SH_BROADCAST_WRITES(1);
464
465 if (se >= 0) {
466 value |= S_030800_SE_INDEX(se);
467 } else {
468 value |= S_030800_SE_BROADCAST_WRITES(1);
469 }
470
471 if (instance >= 0) {
472 value |= S_030800_INSTANCE_INDEX(instance);
473 } else {
474 value |= S_030800_INSTANCE_BROADCAST_WRITES(1);
475 }
476
477 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value);
478 }
479
480 static void si_pc_emit_shaders(struct r600_common_context *ctx,
481 unsigned shaders)
482 {
483 struct radeon_winsys_cs *cs = ctx->gfx.cs;
484
485 radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
486 radeon_emit(cs, shaders & 0x7f);
487 radeon_emit(cs, 0xffffffff);
488 }
489
490 static void si_pc_emit_select(struct r600_common_context *ctx,
491 struct r600_perfcounter_block *group,
492 unsigned count, unsigned *selectors)
493 {
494 struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
495 struct si_pc_block_base *regs = sigroup->b;
496 struct radeon_winsys_cs *cs = ctx->gfx.cs;
497 unsigned idx;
498 unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
499 unsigned dw;
500
501 assert(count <= regs->num_counters);
502
503 if (regs->layout & SI_PC_FAKE)
504 return;
505
506 if (layout_multi == SI_PC_MULTI_BLOCK) {
507 assert(!(regs->layout & SI_PC_REG_REVERSE));
508
509 dw = count + regs->num_prelude;
510 if (count >= regs->num_multi)
511 dw += regs->num_multi;
512 radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
513 for (idx = 0; idx < regs->num_prelude; ++idx)
514 radeon_emit(cs, 0);
515 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
516 radeon_emit(cs, selectors[idx] | regs->select_or);
517
518 if (count < regs->num_multi) {
519 unsigned select1 =
520 regs->select0 + 4 * regs->num_multi;
521 radeon_set_uconfig_reg_seq(cs, select1, count);
522 }
523
524 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
525 radeon_emit(cs, 0);
526
527 if (count > regs->num_multi) {
528 for (idx = regs->num_multi; idx < count; ++idx)
529 radeon_emit(cs, selectors[idx] | regs->select_or);
530 }
531 } else if (layout_multi == SI_PC_MULTI_TAIL) {
532 unsigned select1, select1_count;
533
534 assert(!(regs->layout & SI_PC_REG_REVERSE));
535
536 radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
537 for (idx = 0; idx < regs->num_prelude; ++idx)
538 radeon_emit(cs, 0);
539 for (idx = 0; idx < count; ++idx)
540 radeon_emit(cs, selectors[idx] | regs->select_or);
541
542 select1 = regs->select0 + 4 * regs->num_counters;
543 select1_count = MIN2(count, regs->num_multi);
544 radeon_set_uconfig_reg_seq(cs, select1, select1_count);
545 for (idx = 0; idx < select1_count; ++idx)
546 radeon_emit(cs, 0);
547 } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
548 unsigned *reg = regs->select;
549 for (idx = 0; idx < count; ++idx) {
550 radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
551 if (idx < regs->num_multi)
552 radeon_set_uconfig_reg(cs, *reg++, 0);
553 }
554 } else {
555 assert(layout_multi == SI_PC_MULTI_ALTERNATE);
556
557 unsigned reg_base = regs->select0;
558 unsigned reg_count = count + MIN2(count, regs->num_multi);
559 reg_count += regs->num_prelude;
560
561 if (!(regs->layout & SI_PC_REG_REVERSE)) {
562 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
563
564 for (idx = 0; idx < regs->num_prelude; ++idx)
565 radeon_emit(cs, 0);
566 for (idx = 0; idx < count; ++idx) {
567 radeon_emit(cs, selectors[idx] | regs->select_or);
568 if (idx < regs->num_multi)
569 radeon_emit(cs, 0);
570 }
571 } else {
572 reg_base -= (reg_count - 1) * 4;
573 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
574
575 for (idx = count; idx > 0; --idx) {
576 if (idx <= regs->num_multi)
577 radeon_emit(cs, 0);
578 radeon_emit(cs, selectors[idx - 1] | regs->select_or);
579 }
580 for (idx = 0; idx < regs->num_prelude; ++idx)
581 radeon_emit(cs, 0);
582 }
583 }
584 }
585
586 static void si_pc_emit_start(struct r600_common_context *ctx,
587 struct r600_resource *buffer, uint64_t va)
588 {
589 struct radeon_winsys_cs *cs = ctx->gfx.cs;
590
591 radeon_add_to_buffer_list(ctx, &ctx->gfx, buffer,
592 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
593
594 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
595 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
596 COPY_DATA_DST_SEL(COPY_DATA_MEM));
597 radeon_emit(cs, 1); /* immediate */
598 radeon_emit(cs, 0); /* unused */
599 radeon_emit(cs, va);
600 radeon_emit(cs, va >> 32);
601
602 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
603 S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET));
604 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
605 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_START) | EVENT_INDEX(0));
606 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
607 S_036020_PERFMON_STATE(V_036020_START_COUNTING));
608 }
609
610 /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
611 * do it again in here. */
612 static void si_pc_emit_stop(struct r600_common_context *ctx,
613 struct r600_resource *buffer, uint64_t va)
614 {
615 struct radeon_winsys_cs *cs = ctx->gfx.cs;
616
617 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
618 EOP_DATA_SEL_VALUE_32BIT,
619 buffer, va, 0, R600_NOT_QUERY);
620 r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
621
622 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
623 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
624 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
625 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP) | EVENT_INDEX(0));
626 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
627 S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
628 S_036020_PERFMON_SAMPLE_ENABLE(1));
629 }
630
631 static void si_pc_emit_read(struct r600_common_context *ctx,
632 struct r600_perfcounter_block *group,
633 unsigned count, unsigned *selectors,
634 struct r600_resource *buffer, uint64_t va)
635 {
636 struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
637 struct si_pc_block_base *regs = sigroup->b;
638 struct radeon_winsys_cs *cs = ctx->gfx.cs;
639 unsigned idx;
640 unsigned reg = regs->counter0_lo;
641 unsigned reg_delta = 8;
642
643 if (!(regs->layout & SI_PC_FAKE)) {
644 if (regs->layout & SI_PC_REG_REVERSE)
645 reg_delta = -reg_delta;
646
647 for (idx = 0; idx < count; ++idx) {
648 if (regs->counters)
649 reg = regs->counters[idx];
650
651 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
652 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) |
653 COPY_DATA_DST_SEL(COPY_DATA_MEM) |
654 COPY_DATA_COUNT_SEL); /* 64 bits */
655 radeon_emit(cs, reg >> 2);
656 radeon_emit(cs, 0); /* unused */
657 radeon_emit(cs, va);
658 radeon_emit(cs, va >> 32);
659 va += sizeof(uint64_t);
660 reg += reg_delta;
661 }
662 } else {
663 for (idx = 0; idx < count; ++idx) {
664 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
665 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
666 COPY_DATA_DST_SEL(COPY_DATA_MEM) |
667 COPY_DATA_COUNT_SEL);
668 radeon_emit(cs, 0); /* immediate */
669 radeon_emit(cs, 0);
670 radeon_emit(cs, va);
671 radeon_emit(cs, va >> 32);
672 va += sizeof(uint64_t);
673 }
674 }
675 }
676
677 static void si_pc_cleanup(struct r600_common_screen *rscreen)
678 {
679 r600_perfcounters_do_destroy(rscreen->perfcounters);
680 rscreen->perfcounters = NULL;
681 }
682
683 void si_init_perfcounters(struct si_screen *screen)
684 {
685 struct r600_perfcounters *pc;
686 struct si_pc_block *blocks;
687 unsigned num_blocks;
688 unsigned i;
689
690 switch (screen->b.chip_class) {
691 case CIK:
692 blocks = groups_CIK;
693 num_blocks = ARRAY_SIZE(groups_CIK);
694 break;
695 case VI:
696 blocks = groups_VI;
697 num_blocks = ARRAY_SIZE(groups_VI);
698 break;
699 case GFX9:
700 blocks = groups_gfx9;
701 num_blocks = ARRAY_SIZE(groups_gfx9);
702 break;
703 case SI:
704 default:
705 return; /* not implemented */
706 }
707
708 if (screen->b.info.max_sh_per_se != 1) {
709 /* This should not happen on non-SI chips. */
710 fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
711 "supported (inaccurate performance counters)\n",
712 screen->b.info.max_sh_per_se);
713 }
714
715 pc = CALLOC_STRUCT(r600_perfcounters);
716 if (!pc)
717 return;
718
719 pc->num_start_cs_dwords = 14;
720 pc->num_stop_cs_dwords = 14 + r600_gfx_write_fence_dwords(&screen->b);
721 pc->num_instance_cs_dwords = 3;
722 pc->num_shaders_cs_dwords = 4;
723
724 pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
725 pc->shader_type_suffixes = si_pc_shader_type_suffixes;
726 pc->shader_type_bits = si_pc_shader_type_bits;
727
728 pc->get_size = si_pc_get_size;
729 pc->emit_instance = si_pc_emit_instance;
730 pc->emit_shaders = si_pc_emit_shaders;
731 pc->emit_select = si_pc_emit_select;
732 pc->emit_start = si_pc_emit_start;
733 pc->emit_stop = si_pc_emit_stop;
734 pc->emit_read = si_pc_emit_read;
735 pc->cleanup = si_pc_cleanup;
736
737 if (!r600_perfcounters_init(pc, num_blocks))
738 goto error;
739
740 for (i = 0; i < num_blocks; ++i) {
741 struct si_pc_block *block = &blocks[i];
742 unsigned instances = block->instances;
743
744 if (!strcmp(block->b->name, "IA")) {
745 if (screen->b.info.max_se > 2)
746 instances = 2;
747 }
748
749 r600_perfcounters_add_block(&screen->b, pc,
750 block->b->name,
751 block->b->flags,
752 block->b->num_counters,
753 block->selectors,
754 instances,
755 block);
756 }
757
758 screen->b.perfcounters = pc;
759 return;
760
761 error:
762 r600_perfcounters_do_destroy(pc);
763 }