2 * Copyright 2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "radeon/r600_cs.h"
26 #include "radeon/r600_query.h"
27 #include "util/u_memory.h"
32 enum si_pc_reg_layout
{
33 /* All secondary selector dwords follow as one block after the primary
34 * selector dwords for the counters that have secondary selectors.
36 SI_PC_MULTI_BLOCK
= 0,
38 /* Each secondary selector dword follows immediately afters the
39 * corresponding primary.
41 SI_PC_MULTI_ALTERNATE
= 1,
43 /* All secondary selector dwords follow as one block after all primary
48 /* Free-form arrangement of selector registers. */
49 SI_PC_MULTI_CUSTOM
= 3,
53 /* Registers are laid out in decreasing rather than increasing order. */
54 SI_PC_REG_REVERSE
= 4,
59 struct si_pc_block_base
{
61 unsigned num_counters
;
75 struct si_pc_block_base
*b
;
80 /* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
81 * performance counter group IDs.
83 static const char * const si_pc_shader_type_suffixes
[] = {
84 "", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
87 static const unsigned si_pc_shader_type_bits
[] = {
98 static struct si_pc_block_base cik_CB
= {
101 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
,
103 .select0
= R_037000_CB_PERFCOUNTER_FILTER
,
104 .counter0_lo
= R_035018_CB_PERFCOUNTER0_LO
,
107 .layout
= SI_PC_MULTI_ALTERNATE
,
110 static unsigned cik_CPC_select
[] = {
111 R_036024_CPC_PERFCOUNTER0_SELECT
,
112 R_036010_CPC_PERFCOUNTER0_SELECT1
,
113 R_03600C_CPC_PERFCOUNTER1_SELECT
,
115 static struct si_pc_block_base cik_CPC
= {
119 .select
= cik_CPC_select
,
120 .counter0_lo
= R_034018_CPC_PERFCOUNTER0_LO
,
122 .layout
= SI_PC_MULTI_CUSTOM
| SI_PC_REG_REVERSE
,
125 static struct si_pc_block_base cik_CPF
= {
129 .select0
= R_03601C_CPF_PERFCOUNTER0_SELECT
,
130 .counter0_lo
= R_034028_CPF_PERFCOUNTER0_LO
,
132 .layout
= SI_PC_MULTI_ALTERNATE
| SI_PC_REG_REVERSE
,
135 static struct si_pc_block_base cik_CPG
= {
139 .select0
= R_036008_CPG_PERFCOUNTER0_SELECT
,
140 .counter0_lo
= R_034008_CPG_PERFCOUNTER0_LO
,
142 .layout
= SI_PC_MULTI_ALTERNATE
| SI_PC_REG_REVERSE
,
145 static struct si_pc_block_base cik_DB
= {
148 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
,
150 .select0
= R_037100_DB_PERFCOUNTER0_SELECT
,
151 .counter0_lo
= R_035100_DB_PERFCOUNTER0_LO
,
152 .num_multi
= 3, // really only 2, but there's a gap between registers
153 .layout
= SI_PC_MULTI_ALTERNATE
,
156 static struct si_pc_block_base cik_GDS
= {
160 .select0
= R_036A00_GDS_PERFCOUNTER0_SELECT
,
161 .counter0_lo
= R_034A00_GDS_PERFCOUNTER0_LO
,
163 .layout
= SI_PC_MULTI_TAIL
,
166 static unsigned cik_GRBM_counters
[] = {
167 R_034100_GRBM_PERFCOUNTER0_LO
,
168 R_03410C_GRBM_PERFCOUNTER1_LO
,
170 static struct si_pc_block_base cik_GRBM
= {
174 .select0
= R_036100_GRBM_PERFCOUNTER0_SELECT
,
175 .counters
= cik_GRBM_counters
,
178 static struct si_pc_block_base cik_GRBMSE
= {
182 .select0
= R_036108_GRBM_SE0_PERFCOUNTER_SELECT
,
183 .counter0_lo
= R_034114_GRBM_SE0_PERFCOUNTER_LO
,
186 static struct si_pc_block_base cik_IA
= {
190 .select0
= R_036210_IA_PERFCOUNTER0_SELECT
,
191 .counter0_lo
= R_034220_IA_PERFCOUNTER0_LO
,
193 .layout
= SI_PC_MULTI_TAIL
,
196 static struct si_pc_block_base cik_PA_SC
= {
199 .flags
= R600_PC_BLOCK_SE
,
201 .select0
= R_036500_PA_SC_PERFCOUNTER0_SELECT
,
202 .counter0_lo
= R_034500_PA_SC_PERFCOUNTER0_LO
,
204 .layout
= SI_PC_MULTI_ALTERNATE
,
207 /* According to docs, PA_SU counters are only 48 bits wide. */
208 static struct si_pc_block_base cik_PA_SU
= {
211 .flags
= R600_PC_BLOCK_SE
,
213 .select0
= R_036400_PA_SU_PERFCOUNTER0_SELECT
,
214 .counter0_lo
= R_034400_PA_SU_PERFCOUNTER0_LO
,
216 .layout
= SI_PC_MULTI_ALTERNATE
,
219 static struct si_pc_block_base cik_SPI
= {
222 .flags
= R600_PC_BLOCK_SE
,
224 .select0
= R_036600_SPI_PERFCOUNTER0_SELECT
,
225 .counter0_lo
= R_034604_SPI_PERFCOUNTER0_LO
,
227 .layout
= SI_PC_MULTI_BLOCK
,
230 static struct si_pc_block_base cik_SQ
= {
233 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_SHADER
,
235 .select0
= R_036700_SQ_PERFCOUNTER0_SELECT
,
236 .select_or
= S_036700_SQC_BANK_MASK(15) |
237 S_036700_SQC_CLIENT_MASK(15) |
238 S_036700_SIMD_MASK(15),
239 .counter0_lo
= R_034700_SQ_PERFCOUNTER0_LO
,
242 static struct si_pc_block_base cik_SX
= {
245 .flags
= R600_PC_BLOCK_SE
,
247 .select0
= R_036900_SX_PERFCOUNTER0_SELECT
,
248 .counter0_lo
= R_034900_SX_PERFCOUNTER0_LO
,
250 .layout
= SI_PC_MULTI_TAIL
,
253 static struct si_pc_block_base cik_TA
= {
256 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
258 .select0
= R_036B00_TA_PERFCOUNTER0_SELECT
,
259 .counter0_lo
= R_034B00_TA_PERFCOUNTER0_LO
,
261 .layout
= SI_PC_MULTI_ALTERNATE
,
264 static struct si_pc_block_base cik_TD
= {
267 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
269 .select0
= R_036C00_TD_PERFCOUNTER0_SELECT
,
270 .counter0_lo
= R_034C00_TD_PERFCOUNTER0_LO
,
272 .layout
= SI_PC_MULTI_ALTERNATE
,
275 static struct si_pc_block_base cik_TCA
= {
278 .flags
= R600_PC_BLOCK_INSTANCE_GROUPS
,
280 .select0
= R_036E40_TCA_PERFCOUNTER0_SELECT
,
281 .counter0_lo
= R_034E40_TCA_PERFCOUNTER0_LO
,
283 .layout
= SI_PC_MULTI_ALTERNATE
,
286 static struct si_pc_block_base cik_TCC
= {
289 .flags
= R600_PC_BLOCK_INSTANCE_GROUPS
,
291 .select0
= R_036E00_TCC_PERFCOUNTER0_SELECT
,
292 .counter0_lo
= R_034E00_TCC_PERFCOUNTER0_LO
,
294 .layout
= SI_PC_MULTI_ALTERNATE
,
297 static struct si_pc_block_base cik_TCP
= {
300 .flags
= R600_PC_BLOCK_SE
| R600_PC_BLOCK_INSTANCE_GROUPS
| R600_PC_BLOCK_SHADER_WINDOWED
,
302 .select0
= R_036D00_TCP_PERFCOUNTER0_SELECT
,
303 .counter0_lo
= R_034D00_TCP_PERFCOUNTER0_LO
,
305 .layout
= SI_PC_MULTI_ALTERNATE
,
308 static struct si_pc_block_base cik_VGT
= {
311 .flags
= R600_PC_BLOCK_SE
,
313 .select0
= R_036230_VGT_PERFCOUNTER0_SELECT
,
314 .counter0_lo
= R_034240_VGT_PERFCOUNTER0_LO
,
316 .layout
= SI_PC_MULTI_TAIL
,
319 static struct si_pc_block_base cik_WD
= {
323 .select0
= R_036200_WD_PERFCOUNTER0_SELECT
,
324 .counter0_lo
= R_034200_WD_PERFCOUNTER0_LO
,
327 static struct si_pc_block_base cik_MC
= {
331 .layout
= SI_PC_FAKE
,
334 static struct si_pc_block_base cik_SRBM
= {
338 .layout
= SI_PC_FAKE
,
341 /* Both the number of instances and selectors varies between chips of the same
342 * class. We only differentiate by class here and simply expose the maximum
343 * number over all chips in a class.
345 * Unfortunately, GPUPerfStudio uses the order of performance counter groups
346 * blindly once it believes it has identified the hardware, so the order of
347 * blocks here matters.
349 static struct si_pc_block groups_CIK
[] = {
360 { &cik_TA
, 111, 11 },
362 { &cik_TCC
, 160, 16 },
364 { &cik_TCP
, 154, 11 },
376 static struct si_pc_block groups_VI
[] = {
387 { &cik_TA
, 119, 16 },
389 { &cik_TCC
, 192, 16 },
391 { &cik_TCP
, 180, 16 },
403 static struct si_pc_block groups_gfx9
[] = {
414 { &cik_TA
, 119, 16 },
416 { &cik_TCC
, 256, 16 },
418 { &cik_TCP
, 85, 16 },
427 static void si_pc_emit_instance(struct si_context
*sctx
,
428 int se
, int instance
)
430 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
431 unsigned value
= S_030800_SH_BROADCAST_WRITES(1);
434 value
|= S_030800_SE_INDEX(se
);
436 value
|= S_030800_SE_BROADCAST_WRITES(1);
440 value
|= S_030800_INSTANCE_INDEX(instance
);
442 value
|= S_030800_INSTANCE_BROADCAST_WRITES(1);
445 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
, value
);
448 static void si_pc_emit_shaders(struct si_context
*sctx
,
451 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
453 radeon_set_uconfig_reg_seq(cs
, R_036780_SQ_PERFCOUNTER_CTRL
, 2);
454 radeon_emit(cs
, shaders
& 0x7f);
455 radeon_emit(cs
, 0xffffffff);
458 static void si_pc_emit_select(struct si_context
*sctx
,
459 struct si_perfcounter_block
*group
,
460 unsigned count
, unsigned *selectors
)
462 struct si_pc_block
*sigroup
= (struct si_pc_block
*)group
->data
;
463 struct si_pc_block_base
*regs
= sigroup
->b
;
464 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
466 unsigned layout_multi
= regs
->layout
& SI_PC_MULTI_MASK
;
469 assert(count
<= regs
->num_counters
);
471 if (regs
->layout
& SI_PC_FAKE
)
474 if (layout_multi
== SI_PC_MULTI_BLOCK
) {
475 assert(!(regs
->layout
& SI_PC_REG_REVERSE
));
477 dw
= count
+ regs
->num_prelude
;
478 if (count
>= regs
->num_multi
)
479 dw
+= regs
->num_multi
;
480 radeon_set_uconfig_reg_seq(cs
, regs
->select0
, dw
);
481 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
483 for (idx
= 0; idx
< MIN2(count
, regs
->num_multi
); ++idx
)
484 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
486 if (count
< regs
->num_multi
) {
488 regs
->select0
+ 4 * regs
->num_multi
;
489 radeon_set_uconfig_reg_seq(cs
, select1
, count
);
492 for (idx
= 0; idx
< MIN2(count
, regs
->num_multi
); ++idx
)
495 if (count
> regs
->num_multi
) {
496 for (idx
= regs
->num_multi
; idx
< count
; ++idx
)
497 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
499 } else if (layout_multi
== SI_PC_MULTI_TAIL
) {
500 unsigned select1
, select1_count
;
502 assert(!(regs
->layout
& SI_PC_REG_REVERSE
));
504 radeon_set_uconfig_reg_seq(cs
, regs
->select0
, count
+ regs
->num_prelude
);
505 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
507 for (idx
= 0; idx
< count
; ++idx
)
508 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
510 select1
= regs
->select0
+ 4 * regs
->num_counters
;
511 select1_count
= MIN2(count
, regs
->num_multi
);
512 radeon_set_uconfig_reg_seq(cs
, select1
, select1_count
);
513 for (idx
= 0; idx
< select1_count
; ++idx
)
515 } else if (layout_multi
== SI_PC_MULTI_CUSTOM
) {
516 unsigned *reg
= regs
->select
;
517 for (idx
= 0; idx
< count
; ++idx
) {
518 radeon_set_uconfig_reg(cs
, *reg
++, selectors
[idx
] | regs
->select_or
);
519 if (idx
< regs
->num_multi
)
520 radeon_set_uconfig_reg(cs
, *reg
++, 0);
523 assert(layout_multi
== SI_PC_MULTI_ALTERNATE
);
525 unsigned reg_base
= regs
->select0
;
526 unsigned reg_count
= count
+ MIN2(count
, regs
->num_multi
);
527 reg_count
+= regs
->num_prelude
;
529 if (!(regs
->layout
& SI_PC_REG_REVERSE
)) {
530 radeon_set_uconfig_reg_seq(cs
, reg_base
, reg_count
);
532 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
534 for (idx
= 0; idx
< count
; ++idx
) {
535 radeon_emit(cs
, selectors
[idx
] | regs
->select_or
);
536 if (idx
< regs
->num_multi
)
540 reg_base
-= (reg_count
- 1) * 4;
541 radeon_set_uconfig_reg_seq(cs
, reg_base
, reg_count
);
543 for (idx
= count
; idx
> 0; --idx
) {
544 if (idx
<= regs
->num_multi
)
546 radeon_emit(cs
, selectors
[idx
- 1] | regs
->select_or
);
548 for (idx
= 0; idx
< regs
->num_prelude
; ++idx
)
554 static void si_pc_emit_start(struct si_context
*sctx
,
555 struct r600_resource
*buffer
, uint64_t va
)
557 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
559 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, buffer
,
560 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
562 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
563 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
564 COPY_DATA_DST_SEL(COPY_DATA_MEM
));
565 radeon_emit(cs
, 1); /* immediate */
566 radeon_emit(cs
, 0); /* unused */
568 radeon_emit(cs
, va
>> 32);
570 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
571 S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET
));
572 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
573 radeon_emit(cs
, EVENT_TYPE(V_028A90_PERFCOUNTER_START
) | EVENT_INDEX(0));
574 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
575 S_036020_PERFMON_STATE(V_036020_START_COUNTING
));
578 /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
579 * do it again in here. */
580 static void si_pc_emit_stop(struct si_context
*sctx
,
581 struct r600_resource
*buffer
, uint64_t va
)
583 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
585 si_gfx_write_event_eop(sctx
, V_028A90_BOTTOM_OF_PIPE_TS
, 0,
586 EOP_DATA_SEL_VALUE_32BIT
,
587 buffer
, va
, 0, SI_NOT_QUERY
);
588 si_gfx_wait_fence(sctx
, va
, 0, 0xffffffff);
590 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
591 radeon_emit(cs
, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE
) | EVENT_INDEX(0));
592 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
593 radeon_emit(cs
, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP
) | EVENT_INDEX(0));
594 radeon_set_uconfig_reg(cs
, R_036020_CP_PERFMON_CNTL
,
595 S_036020_PERFMON_STATE(V_036020_STOP_COUNTING
) |
596 S_036020_PERFMON_SAMPLE_ENABLE(1));
599 static void si_pc_emit_read(struct si_context
*sctx
,
600 struct si_perfcounter_block
*group
,
601 unsigned count
, unsigned *selectors
,
602 struct r600_resource
*buffer
, uint64_t va
)
604 struct si_pc_block
*sigroup
= (struct si_pc_block
*)group
->data
;
605 struct si_pc_block_base
*regs
= sigroup
->b
;
606 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
608 unsigned reg
= regs
->counter0_lo
;
609 unsigned reg_delta
= 8;
611 if (!(regs
->layout
& SI_PC_FAKE
)) {
612 if (regs
->layout
& SI_PC_REG_REVERSE
)
613 reg_delta
= -reg_delta
;
615 for (idx
= 0; idx
< count
; ++idx
) {
617 reg
= regs
->counters
[idx
];
619 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
620 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_PERF
) |
621 COPY_DATA_DST_SEL(COPY_DATA_MEM
) |
622 COPY_DATA_COUNT_SEL
); /* 64 bits */
623 radeon_emit(cs
, reg
>> 2);
624 radeon_emit(cs
, 0); /* unused */
626 radeon_emit(cs
, va
>> 32);
627 va
+= sizeof(uint64_t);
631 for (idx
= 0; idx
< count
; ++idx
) {
632 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
633 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
634 COPY_DATA_DST_SEL(COPY_DATA_MEM
) |
635 COPY_DATA_COUNT_SEL
);
636 radeon_emit(cs
, 0); /* immediate */
639 radeon_emit(cs
, va
>> 32);
640 va
+= sizeof(uint64_t);
645 static void si_pc_cleanup(struct si_screen
*sscreen
)
647 si_perfcounters_do_destroy(sscreen
->perfcounters
);
648 sscreen
->perfcounters
= NULL
;
651 void si_init_perfcounters(struct si_screen
*screen
)
653 struct si_perfcounters
*pc
;
654 struct si_pc_block
*blocks
;
658 switch (screen
->info
.chip_class
) {
661 num_blocks
= ARRAY_SIZE(groups_CIK
);
665 num_blocks
= ARRAY_SIZE(groups_VI
);
668 blocks
= groups_gfx9
;
669 num_blocks
= ARRAY_SIZE(groups_gfx9
);
673 return; /* not implemented */
676 if (screen
->info
.max_sh_per_se
!= 1) {
677 /* This should not happen on non-SI chips. */
678 fprintf(stderr
, "si_init_perfcounters: max_sh_per_se = %d not "
679 "supported (inaccurate performance counters)\n",
680 screen
->info
.max_sh_per_se
);
683 pc
= CALLOC_STRUCT(si_perfcounters
);
687 pc
->num_stop_cs_dwords
= 14 + si_gfx_write_fence_dwords(screen
);
688 pc
->num_instance_cs_dwords
= 3;
690 pc
->num_shader_types
= ARRAY_SIZE(si_pc_shader_type_bits
);
691 pc
->shader_type_suffixes
= si_pc_shader_type_suffixes
;
692 pc
->shader_type_bits
= si_pc_shader_type_bits
;
694 pc
->emit_instance
= si_pc_emit_instance
;
695 pc
->emit_shaders
= si_pc_emit_shaders
;
696 pc
->emit_select
= si_pc_emit_select
;
697 pc
->emit_start
= si_pc_emit_start
;
698 pc
->emit_stop
= si_pc_emit_stop
;
699 pc
->emit_read
= si_pc_emit_read
;
700 pc
->cleanup
= si_pc_cleanup
;
702 if (!si_perfcounters_init(pc
, num_blocks
))
705 for (i
= 0; i
< num_blocks
; ++i
) {
706 struct si_pc_block
*block
= &blocks
[i
];
707 unsigned instances
= block
->instances
;
709 if (!strcmp(block
->b
->name
, "IA")) {
710 if (screen
->info
.max_se
> 2)
714 si_perfcounters_add_block(screen
, pc
,
717 block
->b
->num_counters
,
723 screen
->perfcounters
= pc
;
727 si_perfcounters_do_destroy(pc
);