src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_buffer, NULL);
  48         free(sctx->border_color_table);
  49         r600_resource_reference(&sctx->scratch_buffer, NULL);
  50         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  51
  52         si_pm4_free_state(sctx, sctx->init_config, ~0);
  53         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  54                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  55
  56         if (sctx->pstipple_sampler_state)
  57                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  58         if (sctx->dummy_pixel_shader)
  59                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  60         if (sctx->fixed_func_tcs_shader)
  61                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  62         if (sctx->custom_dsa_flush)
  63                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  64         if (sctx->custom_blend_resolve)
  65                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  66         if (sctx->custom_blend_decompress)
  67                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  68         if (sctx->custom_blend_fastclear)
  69                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  70         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  71
  72         if (sctx->blitter)
  73                 util_blitter_destroy(sctx->blitter);
  74
  75         r600_common_context_cleanup(&sctx->b);
  76
  77 #if HAVE_LLVM >= 0x0306
  78         LLVMDisposeTargetMachine(sctx->tm);
  79 #endif
  80
  81         r600_resource_reference(&sctx->trace_buf, NULL);
  82         r600_resource_reference(&sctx->last_trace_buf, NULL);
  83         free(sctx->last_ib);
  84         FREE(sctx);
  85 }
  86
  87 static enum pipe_reset_status
  88 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  89 {
  90         struct si_context *sctx = (struct si_context *)ctx;
  91
  92         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  93 }
  94
  95 static struct pipe_context *si_create_context(struct pipe_screen *screen,
  96                                               void *priv, unsigned flags)
  97 {
  98         struct si_context *sctx = CALLOC_STRUCT(si_context);
  99         struct si_screen* sscreen = (struct si_screen *)screen;
 100         struct radeon_winsys *ws = sscreen->b.ws;
 101         LLVMTargetRef r600_target;
 102 #if HAVE_LLVM >= 0x0306
 103         const char *triple = "amdgcn--";
 104 #endif
 105         int shader, i;
 106
 107         if (sctx == NULL)
 108                 return NULL;
 109
 110         sctx->b.b.screen = screen; /* this must be set first */
 111         sctx->b.b.priv = priv;
 112         sctx->b.b.destroy = si_destroy_context;
 113         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 114         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 115         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 116
 117         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 118                 goto fail;
 119
 120         if (sscreen->b.info.drm_major == 3)
 121                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 122
 123         si_init_blit_functions(sctx);
 124         si_init_compute_functions(sctx);
 125         si_init_cp_dma_functions(sctx);
 126         si_init_debug_functions(sctx);
 127
 128         if (sscreen->b.info.has_uvd) {
 129                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 130                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 131         } else {
 132                 sctx->b.b.create_video_codec = vl_create_decoder;
 133                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 134         }
 135
 136         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 137                                              sctx, sscreen->b.trace_bo ?
 138                                                 sscreen->b.trace_bo->cs_buf : NULL);
 139         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 140
 141         /* Border colors. */
 142         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 143                                           sizeof(*sctx->border_color_table));
 144         if (!sctx->border_color_table)
 145                 goto fail;
 146
 147         sctx->border_color_buffer = (struct r600_resource*)
 148                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 149                                    SI_MAX_BORDER_COLORS *
 150                                    sizeof(*sctx->border_color_table));
 151         if (!sctx->border_color_buffer)
 152                 goto fail;
 153
 154         sctx->border_color_map =
 155                 ws->buffer_map(sctx->border_color_buffer->cs_buf,
 156                                NULL, PIPE_TRANSFER_WRITE);
 157         if (!sctx->border_color_map)
 158                 goto fail;
 159
 160         si_init_all_descriptors(sctx);
 161         si_init_state_functions(sctx);
 162         si_init_shader_functions(sctx);
 163
 164         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 165                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 166
 167         sctx->blitter = util_blitter_create(&sctx->b.b);
 168         if (sctx->blitter == NULL)
 169                 goto fail;
 170         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 171
 172         sctx->sample_mask.sample_mask = 0xffff;
 173
 174         /* these must be last */
 175         si_begin_new_cs(sctx);
 176         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 177
 178         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 179          * with a NULL buffer). We need to use a dummy buffer instead. */
 180         if (sctx->b.chip_class == CIK) {
 181                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 182                                                                  PIPE_USAGE_DEFAULT, 16);
 183                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 184
 185                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 186                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 187                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 188                                                               &sctx->null_const_buf);
 189                         }
 190                 }
 191
 192                 /* Clear the NULL constant buffer, because loads should return zeros. */
 193                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 194                                      sctx->null_const_buf.buffer->width0, 0, false);
 195         }
 196
 197         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 198          * this for non-cs shaders.  Using the wrong value here can result in
 199          * GPU lockups, but the maximum value seems to always work.
 200          */
 201         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 202
 203 #if HAVE_LLVM >= 0x0306
 204         /* Initialize LLVM TargetMachine */
 205         r600_target = radeon_llvm_get_r600_target(triple);
 206         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 207                                            r600_get_llvm_processor_name(sscreen->b.family),
 208                                            "+DumpCode,+vgpr-spilling",
 209                                            LLVMCodeGenLevelDefault,
 210                                            LLVMRelocDefault,
 211                                            LLVMCodeModelDefault);
 212 #endif
 213
 214         return &sctx->b.b;
 215 fail:
 216         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 217         si_destroy_context(&sctx->b.b);
 218         return NULL;
 219 }
 220
 221 /*
 222  * pipe_screen
 223  */
 224
 225 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 226 {
 227         struct si_screen *sscreen = (struct si_screen *)pscreen;
 228
 229         switch (param) {
 230         /* Supported features (boolean caps). */
 231         case PIPE_CAP_TWO_SIDED_STENCIL:
 232         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 233         case PIPE_CAP_ANISOTROPIC_FILTER:
 234         case PIPE_CAP_POINT_SPRITE:
 235         case PIPE_CAP_OCCLUSION_QUERY:
 236         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 237         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 238         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 239         case PIPE_CAP_TEXTURE_SWIZZLE:
 240         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 241         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 242         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 243         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 244         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 245         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 246         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 247         case PIPE_CAP_SM3:
 248         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 249         case PIPE_CAP_PRIMITIVE_RESTART:
 250         case PIPE_CAP_CONDITIONAL_RENDER:
 251         case PIPE_CAP_TEXTURE_BARRIER:
 252         case PIPE_CAP_INDEP_BLEND_ENABLE:
 253         case PIPE_CAP_INDEP_BLEND_FUNC:
 254         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 255         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 256         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 257         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 258         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 259         case PIPE_CAP_USER_INDEX_BUFFERS:
 260         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 261         case PIPE_CAP_START_INSTANCE:
 262         case PIPE_CAP_NPOT_TEXTURES:
 263         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 264         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 265         case PIPE_CAP_TGSI_INSTANCEID:
 266         case PIPE_CAP_COMPUTE:
 267         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 268         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 269         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 270         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 271         case PIPE_CAP_CUBE_MAP_ARRAY:
 272         case PIPE_CAP_SAMPLE_SHADING:
 273         case PIPE_CAP_DRAW_INDIRECT:
 274         case PIPE_CAP_CLIP_HALFZ:
 275         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 276         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 277         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 278         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 279         case PIPE_CAP_TGSI_TEXCOORD:
 280         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 281         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 282         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 283         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 284         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 285         case PIPE_CAP_TEXTURE_QUERY_LOD:
 286         case PIPE_CAP_TEXTURE_GATHER_SM5:
 287         case PIPE_CAP_TGSI_TXQS:
 288                 return 1;
 289
 290         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 291                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 292
 293         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 294                 return (sscreen->b.info.drm_major == 2 &&
 295                         sscreen->b.info.drm_minor >= 43) ||
 296                        sscreen->b.info.drm_major == 3;
 297
 298         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 299                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 300                 return sscreen->b.chip_class < CIK ||
 301                        (sscreen->b.info.drm_major == 2 &&
 302                         sscreen->b.info.drm_minor >= 35) ||
 303                        sscreen->b.info.drm_major == 3;
 304
 305         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 306                 return R600_MAP_BUFFER_ALIGNMENT;
 307
 308         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 309         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 310         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 311                 return 4;
 312
 313         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 314                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 315
 316         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 317                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 318
 319         /* Unsupported features. */
 320         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 321         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 322         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 323         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 324         case PIPE_CAP_USER_VERTEX_BUFFERS:
 325         case PIPE_CAP_FAKE_SW_MSAA:
 326         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 327         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 328         case PIPE_CAP_VERTEXID_NOBASE:
 329                 return 0;
 330
 331         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 332                 return 30;
 333
 334         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 335                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 336
 337         /* Stream output. */
 338         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 339                 return sscreen->b.has_streamout ? 4 : 0;
 340         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 341                 return sscreen->b.has_streamout ? 1 : 0;
 342         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 343         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 344                 return sscreen->b.has_streamout ? 32*4 : 0;
 345
 346         /* Geometry shader output. */
 347         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 348                 return 1024;
 349         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 350                 return 4095;
 351         case PIPE_CAP_MAX_VERTEX_STREAMS:
 352                 return 4;
 353
 354         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 355                 return 2048;
 356
 357         /* Texturing. */
 358         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 359         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 360                 return 15; /* 16384 */
 361         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 362                 /* textures support 8192, but layered rendering supports 2048 */
 363                 return 12;
 364         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 365                 /* textures support 8192, but layered rendering supports 2048 */
 366                 return 2048;
 367
 368         /* Render targets. */
 369         case PIPE_CAP_MAX_RENDER_TARGETS:
 370                 return 8;
 371
 372         case PIPE_CAP_MAX_VIEWPORTS:
 373                 return SI_MAX_VIEWPORTS;
 374
 375         /* Timer queries, present when the clock frequency is non zero. */
 376         case PIPE_CAP_QUERY_TIMESTAMP:
 377         case PIPE_CAP_QUERY_TIME_ELAPSED:
 378                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 379
 380         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 381         case PIPE_CAP_MIN_TEXEL_OFFSET:
 382                 return -32;
 383
 384         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 385         case PIPE_CAP_MAX_TEXEL_OFFSET:
 386                 return 31;
 387
 388         case PIPE_CAP_ENDIANNESS:
 389                 return PIPE_ENDIAN_LITTLE;
 390
 391         case PIPE_CAP_VENDOR_ID:
 392                 return 0x1002;
 393         case PIPE_CAP_DEVICE_ID:
 394                 return sscreen->b.info.pci_id;
 395         case PIPE_CAP_ACCELERATED:
 396                 return 1;
 397         case PIPE_CAP_VIDEO_MEMORY:
 398                 return sscreen->b.info.vram_size >> 20;
 399         case PIPE_CAP_UMA:
 400                 return 0;
 401         }
 402         return 0;
 403 }
 404
 405 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 406 {
 407         switch(shader)
 408         {
 409         case PIPE_SHADER_FRAGMENT:
 410         case PIPE_SHADER_VERTEX:
 411         case PIPE_SHADER_GEOMETRY:
 412                 break;
 413         case PIPE_SHADER_TESS_CTRL:
 414         case PIPE_SHADER_TESS_EVAL:
 415                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 416                 if (HAVE_LLVM < 0x0306 ||
 417                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 418                         return 0;
 419                 break;
 420         case PIPE_SHADER_COMPUTE:
 421                 switch (param) {
 422                 case PIPE_SHADER_CAP_PREFERRED_IR:
 423 #if HAVE_LLVM < 0x0306
 424                         return PIPE_SHADER_IR_LLVM;
 425 #else
 426                         return PIPE_SHADER_IR_NATIVE;
 427 #endif
 428                 case PIPE_SHADER_CAP_DOUBLES:
 429                         return HAVE_LLVM >= 0x0307;
 430
 431                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 432                         uint64_t max_const_buffer_size;
 433                         pscreen->get_compute_param(pscreen,
 434                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 435                                 &max_const_buffer_size);
 436                         return max_const_buffer_size;
 437                 }
 438                 default:
 439                         /* If compute shaders don't require a special value
 440                          * for this cap, we can return the same value we
 441                          * do for other shader types. */
 442                         break;
 443                 }
 444                 break;
 445         default:
 446                 return 0;
 447         }
 448
 449         switch (param) {
 450         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 451         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 452         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 453         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 454                 return 16384;
 455         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 456                 return 32;
 457         case PIPE_SHADER_CAP_MAX_INPUTS:
 458                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 459         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 460                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 461         case PIPE_SHADER_CAP_MAX_TEMPS:
 462                 return 256; /* Max native temporaries. */
 463         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 464                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 465         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 466                 return SI_NUM_USER_CONST_BUFFERS;
 467         case PIPE_SHADER_CAP_MAX_PREDS:
 468                 return 0; /* FIXME */
 469         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 470                 return 1;
 471         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 472                 return 1;
 473         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 474                 /* Indirection of geometry shader input dimension is not
 475                  * handled yet
 476                  */
 477                 return shader != PIPE_SHADER_GEOMETRY;
 478         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 479         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 480         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 481                 return 1;
 482         case PIPE_SHADER_CAP_INTEGERS:
 483                 return 1;
 484         case PIPE_SHADER_CAP_SUBROUTINES:
 485                 return 0;
 486         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 487         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 488                 return 16;
 489         case PIPE_SHADER_CAP_PREFERRED_IR:
 490                 return PIPE_SHADER_IR_TGSI;
 491         case PIPE_SHADER_CAP_DOUBLES:
 492                 return HAVE_LLVM >= 0x0307;
 493         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 494         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 495                 return 0;
 496         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 497         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 498                 return 1;
 499         }
 500         return 0;
 501 }
 502
 503 static void si_destroy_screen(struct pipe_screen* pscreen)
 504 {
 505         struct si_screen *sscreen = (struct si_screen *)pscreen;
 506
 507         if (sscreen == NULL)
 508                 return;
 509
 510         if (!sscreen->b.ws->unref(sscreen->b.ws))
 511                 return;
 512
 513         r600_destroy_common_screen(&sscreen->b);
 514 }
 515
 516 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 517
 518 /* Initialize pipe config. This is especially important for GPUs
 519  * with 16 pipes and more where it's initialized incorrectly by
 520  * the TILING_CONFIG ioctl. */
 521 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 522 {
 523         unsigned mode2d;
 524
 525         /* This is okay, because there can be no 2D tiling without
 526          * the tile mode array, so we won't need the pipe config.
 527          * Return "success".
 528          */
 529         if (!sscreen->b.info.si_tile_mode_array_valid)
 530                 return true;
 531
 532         /* The same index is used for the 2D mode on CIK too. */
 533         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 534
 535         switch (G_009910_PIPE_CONFIG(mode2d)) {
 536         case V_02803C_ADDR_SURF_P2:
 537                 sscreen->b.tiling_info.num_channels = 2;
 538                 break;
 539         case V_02803C_X_ADDR_SURF_P4_8X16:
 540         case V_02803C_X_ADDR_SURF_P4_16X16:
 541         case V_02803C_X_ADDR_SURF_P4_16X32:
 542         case V_02803C_X_ADDR_SURF_P4_32X32:
 543                 sscreen->b.tiling_info.num_channels = 4;
 544                 break;
 545         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 546         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 547         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 548         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 549         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 550         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 551         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 552                 sscreen->b.tiling_info.num_channels = 8;
 553                 break;
 554         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 555         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 556                 sscreen->b.tiling_info.num_channels = 16;
 557                 break;
 558         default:
 559                 assert(0);
 560                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 561                         G_009910_PIPE_CONFIG(mode2d));
 562                 return false;
 563         }
 564         return true;
 565 }
 566
 567 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 568 {
 569         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 570
 571         if (sscreen == NULL) {
 572                 return NULL;
 573         }
 574
 575         /* Set functions first. */
 576         sscreen->b.b.context_create = si_create_context;
 577         sscreen->b.b.destroy = si_destroy_screen;
 578         sscreen->b.b.get_param = si_get_param;
 579         sscreen->b.b.get_shader_param = si_get_shader_param;
 580         sscreen->b.b.is_format_supported = si_is_format_supported;
 581         sscreen->b.b.resource_create = r600_resource_create_common;
 582
 583         if (!r600_common_screen_init(&sscreen->b, ws) ||
 584             !si_initialize_pipe_config(sscreen)) {
 585                 FREE(sscreen);
 586                 return NULL;
 587         }
 588
 589         sscreen->b.has_cp_dma = true;
 590         sscreen->b.has_streamout = true;
 591
 592         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 593                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 594
 595         /* Create the auxiliary context. This must be done last. */
 596         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 597
 598         return &sscreen->b.b;
 599 }