src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39
  40         si_release_all_descriptors(sctx);
  41
  42         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  43         r600_resource_reference(&sctx->border_color_table, NULL);
  44
  45         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  46         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  47         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  48
  49         if (sctx->dummy_pixel_shader) {
  50                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  51         }
  52         for (int i = 0; i < 8; i++) {
  53                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  54                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  55                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  56         }
  57         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  58         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  59         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  60         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  61         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  62
  63         util_blitter_destroy(sctx->blitter);
  64
  65         si_pm4_cleanup(sctx);
  66
  67         r600_common_context_cleanup(&sctx->b);
  68         FREE(sctx);
  69 }
  70
  71 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  72 {
  73         struct si_context *sctx = CALLOC_STRUCT(si_context);
  74         struct si_screen* sscreen = (struct si_screen *)screen;
  75         struct radeon_winsys *ws = sscreen->b.ws;
  76         int shader, i;
  77
  78         if (sctx == NULL)
  79                 return NULL;
  80
  81         sctx->b.b.screen = screen; /* this must be set first */
  82         sctx->b.b.priv = priv;
  83         sctx->b.b.destroy = si_destroy_context;
  84         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  85
  86         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  87                 goto fail;
  88
  89         si_init_blit_functions(sctx);
  90         si_init_compute_functions(sctx);
  91
  92         if (sscreen->b.info.has_uvd) {
  93                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  94                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  95         } else {
  96                 sctx->b.b.create_video_codec = vl_create_decoder;
  97                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
  98         }
  99
 100         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 101                                              sctx, NULL);
 102         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 103
 104         si_init_all_descriptors(sctx);
 105
 106         /* Initialize cache_flush. */
 107         sctx->cache_flush = si_atom_cache_flush;
 108         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 109
 110         sctx->msaa_config = si_atom_msaa_config;
 111         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 112
 113         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 114         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 115
 116         switch (sctx->b.chip_class) {
 117         case SI:
 118         case CIK:
 119                 si_init_state_functions(sctx);
 120                 si_init_config(sctx);
 121                 break;
 122         default:
 123                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 124                 goto fail;
 125         }
 126
 127         sctx->blitter = util_blitter_create(&sctx->b.b);
 128         if (sctx->blitter == NULL)
 129                 goto fail;
 130
 131         sctx->dummy_pixel_shader =
 132                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 133                                                      TGSI_SEMANTIC_GENERIC,
 134                                                      TGSI_INTERPOLATE_CONSTANT);
 135         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 136
 137         /* these must be last */
 138         si_begin_new_cs(sctx);
 139         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 140
 141         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 142          * with a NULL buffer). We need to use a dummy buffer instead. */
 143         if (sctx->b.chip_class == CIK) {
 144                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 145                                                                  PIPE_USAGE_DEFAULT, 16);
 146                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 147
 148                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 149                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 150                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 151                                                               &sctx->null_const_buf);
 152                         }
 153                 }
 154
 155                 /* Clear the NULL constant buffer, because loads should return zeros. */
 156                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 157                                      sctx->null_const_buf.buffer->width0, 0);
 158         }
 159
 160         return &sctx->b.b;
 161 fail:
 162         si_destroy_context(&sctx->b.b);
 163         return NULL;
 164 }
 165
 166 /*
 167  * pipe_screen
 168  */
 169
 170 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 171 {
 172         struct si_screen *sscreen = (struct si_screen *)pscreen;
 173
 174         switch (param) {
 175         /* Supported features (boolean caps). */
 176         case PIPE_CAP_TWO_SIDED_STENCIL:
 177         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 178         case PIPE_CAP_ANISOTROPIC_FILTER:
 179         case PIPE_CAP_POINT_SPRITE:
 180         case PIPE_CAP_OCCLUSION_QUERY:
 181         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 182         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 183         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 184         case PIPE_CAP_TEXTURE_SWIZZLE:
 185         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 186         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 187         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 188         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 189         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 190         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 191         case PIPE_CAP_SM3:
 192         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 193         case PIPE_CAP_PRIMITIVE_RESTART:
 194         case PIPE_CAP_CONDITIONAL_RENDER:
 195         case PIPE_CAP_TEXTURE_BARRIER:
 196         case PIPE_CAP_INDEP_BLEND_ENABLE:
 197         case PIPE_CAP_INDEP_BLEND_FUNC:
 198         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 199         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 200         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 201         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 202         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 203         case PIPE_CAP_USER_INDEX_BUFFERS:
 204         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 205         case PIPE_CAP_START_INSTANCE:
 206         case PIPE_CAP_NPOT_TEXTURES:
 207         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 208         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 209         case PIPE_CAP_TGSI_INSTANCEID:
 210         case PIPE_CAP_COMPUTE:
 211         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 212         case PIPE_CAP_TGSI_VS_LAYER:
 213         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 214         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 215         case PIPE_CAP_CUBE_MAP_ARRAY:
 216         case PIPE_CAP_SAMPLE_SHADING:
 217                 return 1;
 218
 219         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 220                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 221                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 222                                                sscreen->b.info.drm_minor >= 35);
 223
 224         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 225                 return R600_MAP_BUFFER_ALIGNMENT;
 226
 227         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 228         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 229                 return 4;
 230
 231         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 232                 return (LLVM_SUPPORTS_GEOM_SHADERS) ? 330 : 140;
 233
 234         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 235                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 236
 237         case PIPE_CAP_TEXTURE_QUERY_LOD:
 238         case PIPE_CAP_TEXTURE_GATHER_SM5:
 239                 return HAVE_LLVM >= 0x0305;
 240         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 241                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 242
 243         /* Unsupported features. */
 244         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 245         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 246         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 247         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 248         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 249         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 250         case PIPE_CAP_USER_VERTEX_BUFFERS:
 251         case PIPE_CAP_TGSI_TEXCOORD:
 252         case PIPE_CAP_FAKE_SW_MSAA:
 253         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 254         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 255                 return 0;
 256
 257         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 258                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 259
 260         /* Stream output. */
 261         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 262                 return sscreen->b.has_streamout ? 4 : 0;
 263         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 264                 return sscreen->b.has_streamout ? 1 : 0;
 265         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 266         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 267                 return sscreen->b.has_streamout ? 32*4 : 0;
 268
 269         /* Geometry shader output. */
 270         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 271                 return 1024;
 272         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 273                 return 4095;
 274
 275         /* Texturing. */
 276         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 277         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 278                 return 15; /* 16384 */
 279         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 280                 /* textures support 8192, but layered rendering supports 2048 */
 281                 return 12;
 282         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 283                 /* textures support 8192, but layered rendering supports 2048 */
 284                 return 2048;
 285
 286         /* Render targets. */
 287         case PIPE_CAP_MAX_RENDER_TARGETS:
 288                 return 8;
 289
 290         case PIPE_CAP_MAX_VIEWPORTS:
 291                 return 1;
 292
 293         /* Timer queries, present when the clock frequency is non zero. */
 294         case PIPE_CAP_QUERY_TIMESTAMP:
 295         case PIPE_CAP_QUERY_TIME_ELAPSED:
 296                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 297
 298         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 299         case PIPE_CAP_MIN_TEXEL_OFFSET:
 300                 return -32;
 301
 302         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 303         case PIPE_CAP_MAX_TEXEL_OFFSET:
 304                 return 31;
 305
 306         case PIPE_CAP_ENDIANNESS:
 307                 return PIPE_ENDIAN_LITTLE;
 308         }
 309         return 0;
 310 }
 311
 312 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 313 {
 314         switch(shader)
 315         {
 316         case PIPE_SHADER_FRAGMENT:
 317         case PIPE_SHADER_VERTEX:
 318                 break;
 319         case PIPE_SHADER_GEOMETRY:
 320 #if !(LLVM_SUPPORTS_GEOM_SHADERS)
 321                 return 0;
 322 #endif
 323                 break;
 324         case PIPE_SHADER_COMPUTE:
 325                 switch (param) {
 326                 case PIPE_SHADER_CAP_PREFERRED_IR:
 327                         return PIPE_SHADER_IR_LLVM;
 328                 default:
 329                         return 0;
 330                 }
 331         default:
 332                 /* TODO: support tessellation */
 333                 return 0;
 334         }
 335
 336         switch (param) {
 337         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 338         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 339         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 340         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 341                 return 16384;
 342         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 343                 return 32;
 344         case PIPE_SHADER_CAP_MAX_INPUTS:
 345                 return 32;
 346         case PIPE_SHADER_CAP_MAX_TEMPS:
 347                 return 256; /* Max native temporaries. */
 348         case PIPE_SHADER_CAP_MAX_ADDRS:
 349                 /* FIXME Isn't this equal to TEMPS? */
 350                 return 1; /* Max native address registers */
 351         case PIPE_SHADER_CAP_MAX_CONSTS:
 352                 return 4096; /* actually only memory limits this */
 353         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 354                 return NUM_PIPE_CONST_BUFFERS;
 355         case PIPE_SHADER_CAP_MAX_PREDS:
 356                 return 0; /* FIXME */
 357         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 358                 return 1;
 359         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 360                 return 0;
 361         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 362                 /* Indirection of geometry shader input dimension is not
 363                  * handled yet
 364                  */
 365                 return shader < PIPE_SHADER_GEOMETRY;
 366         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 367         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 368         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 369                 return 1;
 370         case PIPE_SHADER_CAP_INTEGERS:
 371                 return 1;
 372         case PIPE_SHADER_CAP_SUBROUTINES:
 373                 return 0;
 374         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 375         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 376                 return 16;
 377         case PIPE_SHADER_CAP_PREFERRED_IR:
 378                 return PIPE_SHADER_IR_TGSI;
 379         }
 380         return 0;
 381 }
 382
 383 static void si_destroy_screen(struct pipe_screen* pscreen)
 384 {
 385         struct si_screen *sscreen = (struct si_screen *)pscreen;
 386
 387         if (sscreen == NULL)
 388                 return;
 389
 390         if (!sscreen->b.ws->unref(sscreen->b.ws))
 391                 return;
 392
 393         r600_destroy_common_screen(&sscreen->b);
 394 }
 395
 396 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 397 {
 398         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 399         if (sscreen == NULL) {
 400                 return NULL;
 401         }
 402
 403         /* Set functions first. */
 404         sscreen->b.b.context_create = si_create_context;
 405         sscreen->b.b.destroy = si_destroy_screen;
 406         sscreen->b.b.get_param = si_get_param;
 407         sscreen->b.b.get_shader_param = si_get_shader_param;
 408         sscreen->b.b.is_format_supported = si_is_format_supported;
 409         sscreen->b.b.resource_create = r600_resource_create_common;
 410
 411         if (!r600_common_screen_init(&sscreen->b, ws)) {
 412                 FREE(sscreen);
 413                 return NULL;
 414         }
 415
 416         sscreen->b.has_cp_dma = true;
 417         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 418
 419         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 420                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 421
 422         /* Create the auxiliary context. This must be done last. */
 423         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 424
 425         return &sscreen->b.b;
 426 }