2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader.h"
26 #include "si_public.h"
29 #include "radeon/radeon_llvm_emit.h"
30 #include "radeon/radeon_uvd.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "vl/vl_decoder.h"
38 static void si_destroy_context(struct pipe_context
*context
)
40 struct si_context
*sctx
= (struct si_context
*)context
;
43 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
45 si_release_all_descriptors(sctx
);
47 if (sctx
->ce_suballocator
)
48 u_suballocator_destroy(sctx
->ce_suballocator
);
50 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
51 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
52 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
53 pipe_resource_reference(&sctx
->tess_offchip_ring
, NULL
);
54 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
55 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
56 free(sctx
->border_color_table
);
57 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
58 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
59 sctx
->b
.ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
61 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
62 if (sctx
->init_config_gs_rings
)
63 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
64 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
65 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
67 if (sctx
->fixed_func_tcs_shader
.cso
)
68 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
69 if (sctx
->custom_dsa_flush
)
70 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
71 if (sctx
->custom_blend_resolve
)
72 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
73 if (sctx
->custom_blend_decompress
)
74 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
75 if (sctx
->custom_blend_fastclear
)
76 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
77 if (sctx
->custom_blend_dcc_decompress
)
78 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_dcc_decompress
);
79 util_unreference_framebuffer_state(&sctx
->framebuffer
.state
);
82 util_blitter_destroy(sctx
->blitter
);
84 r600_common_context_cleanup(&sctx
->b
);
86 LLVMDisposeTargetMachine(sctx
->tm
);
88 r600_resource_reference(&sctx
->trace_buf
, NULL
);
89 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
91 if (sctx
->last_bo_list
) {
92 for (i
= 0; i
< sctx
->last_bo_count
; i
++)
93 pb_reference(&sctx
->last_bo_list
[i
].buf
, NULL
);
94 free(sctx
->last_bo_list
);
99 static enum pipe_reset_status
100 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
102 struct si_context
*sctx
= (struct si_context
*)ctx
;
104 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
107 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
108 void *priv
, unsigned flags
)
110 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
111 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
112 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
113 LLVMTargetRef r600_target
;
114 const char *triple
= "amdgcn--";
120 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
121 flags
|= PIPE_CONTEXT_DEBUG
;
123 sctx
->b
.b
.screen
= screen
; /* this must be set first */
124 sctx
->b
.b
.priv
= priv
;
125 sctx
->b
.b
.destroy
= si_destroy_context
;
126 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
127 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
128 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
130 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
133 if (sscreen
->b
.info
.drm_major
== 3)
134 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
136 si_init_blit_functions(sctx
);
137 si_init_compute_functions(sctx
);
138 si_init_cp_dma_functions(sctx
);
139 si_init_debug_functions(sctx
);
141 if (sscreen
->b
.info
.has_uvd
) {
142 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
143 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
145 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
146 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
149 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
,
150 si_context_gfx_flush
, sctx
);
152 if (!(sscreen
->b
.debug_flags
& DBG_NO_CE
) && ws
->cs_add_const_ib
) {
153 sctx
->ce_ib
= ws
->cs_add_const_ib(sctx
->b
.gfx
.cs
);
157 if (ws
->cs_add_const_preamble_ib
) {
158 sctx
->ce_preamble_ib
=
159 ws
->cs_add_const_preamble_ib(sctx
->b
.gfx
.cs
);
161 if (!sctx
->ce_preamble_ib
)
165 sctx
->ce_suballocator
=
166 u_suballocator_create(&sctx
->b
.b
, 1024 * 1024,
168 PIPE_USAGE_DEFAULT
, FALSE
);
169 if (!sctx
->ce_suballocator
)
173 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
176 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
177 sizeof(*sctx
->border_color_table
));
178 if (!sctx
->border_color_table
)
181 sctx
->border_color_buffer
= (struct r600_resource
*)
182 pipe_buffer_create(screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_DEFAULT
,
183 SI_MAX_BORDER_COLORS
*
184 sizeof(*sctx
->border_color_table
));
185 if (!sctx
->border_color_buffer
)
188 sctx
->border_color_map
=
189 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
190 NULL
, PIPE_TRANSFER_WRITE
);
191 if (!sctx
->border_color_map
)
194 si_init_all_descriptors(sctx
);
195 si_init_state_functions(sctx
);
196 si_init_shader_functions(sctx
);
198 if (sctx
->b
.chip_class
>= CIK
)
199 cik_init_sdma_functions(sctx
);
201 si_init_dma_functions(sctx
);
203 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
204 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
206 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
207 if (sctx
->blitter
== NULL
)
209 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
211 sctx
->sample_mask
.sample_mask
= 0xffff;
213 /* these must be last */
214 si_begin_new_cs(sctx
);
215 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
217 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
218 * with a NULL buffer). We need to use a dummy buffer instead. */
219 if (sctx
->b
.chip_class
== CIK
) {
220 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
221 PIPE_USAGE_DEFAULT
, 16);
222 if (!sctx
->null_const_buf
.buffer
)
224 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
226 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
227 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
228 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
229 &sctx
->null_const_buf
);
233 /* Clear the NULL constant buffer, because loads should return zeros. */
234 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
235 sctx
->null_const_buf
.buffer
->width0
, 0,
236 R600_COHERENCY_SHADER
);
239 uint64_t max_threads_per_block
;
240 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
241 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
242 &max_threads_per_block
);
244 /* The maximum number of scratch waves. Scratch space isn't divided
245 * evenly between CUs. The number is only a function of the number of CUs.
246 * We can decrease the constant to decrease the scratch buffer size.
248 * sctx->scratch_waves must be >= the maximum posible size of
249 * 1 threadgroup, so that the hw doesn't hang from being unable
252 * The recommended value is 4 per CU at most. Higher numbers don't
253 * bring much benefit, but they still occupy chip resources (think
254 * async compute). I've seen ~2% performance difference between 4 and 32.
256 sctx
->scratch_waves
= MAX2(32 * sscreen
->b
.info
.num_good_compute_units
,
257 max_threads_per_block
/ 64);
259 /* Initialize LLVM TargetMachine */
260 r600_target
= radeon_llvm_get_r600_target(triple
);
261 sctx
->tm
= LLVMCreateTargetMachine(r600_target
, triple
,
262 r600_get_llvm_processor_name(sscreen
->b
.family
),
263 #if HAVE_LLVM >= 0x0308
264 sscreen
->b
.debug_flags
& DBG_SI_SCHED
?
265 "+DumpCode,+vgpr-spilling,+si-scheduler" :
267 "+DumpCode,+vgpr-spilling",
268 LLVMCodeGenLevelDefault
,
270 LLVMCodeModelDefault
);
274 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
275 si_destroy_context(&sctx
->b
.b
);
283 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
285 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
288 /* Supported features (boolean caps). */
289 case PIPE_CAP_TWO_SIDED_STENCIL
:
290 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
291 case PIPE_CAP_ANISOTROPIC_FILTER
:
292 case PIPE_CAP_POINT_SPRITE
:
293 case PIPE_CAP_OCCLUSION_QUERY
:
294 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
295 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
296 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
297 case PIPE_CAP_TEXTURE_SWIZZLE
:
298 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
299 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
300 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
301 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
302 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
303 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
304 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
306 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
307 case PIPE_CAP_PRIMITIVE_RESTART
:
308 case PIPE_CAP_CONDITIONAL_RENDER
:
309 case PIPE_CAP_TEXTURE_BARRIER
:
310 case PIPE_CAP_INDEP_BLEND_ENABLE
:
311 case PIPE_CAP_INDEP_BLEND_FUNC
:
312 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
313 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
314 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
315 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
316 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
317 case PIPE_CAP_USER_INDEX_BUFFERS
:
318 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
319 case PIPE_CAP_START_INSTANCE
:
320 case PIPE_CAP_NPOT_TEXTURES
:
321 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
322 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
323 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
324 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
325 case PIPE_CAP_TGSI_INSTANCEID
:
326 case PIPE_CAP_COMPUTE
:
327 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
328 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
329 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
330 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
331 case PIPE_CAP_CUBE_MAP_ARRAY
:
332 case PIPE_CAP_SAMPLE_SHADING
:
333 case PIPE_CAP_DRAW_INDIRECT
:
334 case PIPE_CAP_CLIP_HALFZ
:
335 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
336 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
337 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
338 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
339 case PIPE_CAP_TGSI_TEXCOORD
:
340 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
341 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
342 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
343 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
344 case PIPE_CAP_SHAREABLE_SHADERS
:
345 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
346 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
347 case PIPE_CAP_TEXTURE_QUERY_LOD
:
348 case PIPE_CAP_TEXTURE_GATHER_SM5
:
349 case PIPE_CAP_TGSI_TXQS
:
350 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
351 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
352 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
353 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
354 case PIPE_CAP_INVALIDATE_BUFFER
:
355 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
356 case PIPE_CAP_QUERY_MEMORY_INFO
:
357 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
358 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
359 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
362 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
363 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
365 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
366 return (sscreen
->b
.info
.drm_major
== 2 &&
367 sscreen
->b
.info
.drm_minor
>= 43) ||
368 sscreen
->b
.info
.drm_major
== 3;
370 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
371 /* 2D tiling on CIK is supported since DRM 2.35.0 */
372 return sscreen
->b
.chip_class
< CIK
||
373 (sscreen
->b
.info
.drm_major
== 2 &&
374 sscreen
->b
.info
.drm_minor
>= 35) ||
375 sscreen
->b
.info
.drm_major
== 3;
377 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
378 return R600_MAP_BUFFER_ALIGNMENT
;
380 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
381 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
382 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
384 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
385 return HAVE_LLVM
>= 0x0309 ? 4 : 0;
387 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
388 if (pscreen
->get_shader_param(pscreen
, PIPE_SHADER_COMPUTE
,
389 PIPE_SHADER_CAP_SUPPORTED_IRS
) &
390 (1 << PIPE_SHADER_IR_TGSI
))
392 return HAVE_LLVM
>= 0x0309 ? 420 :
393 HAVE_LLVM
>= 0x0307 ? 410 : 330;
395 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
396 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
398 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
401 /* Unsupported features. */
402 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
403 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
404 case PIPE_CAP_USER_VERTEX_BUFFERS
:
405 case PIPE_CAP_FAKE_SW_MSAA
:
406 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
407 case PIPE_CAP_VERTEXID_NOBASE
:
408 case PIPE_CAP_CLEAR_TEXTURE
:
409 case PIPE_CAP_DRAW_PARAMETERS
:
410 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
411 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
412 case PIPE_CAP_GENERATE_MIPMAP
:
413 case PIPE_CAP_STRING_MARKER
:
414 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
415 case PIPE_CAP_CULL_DISTANCE
:
416 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
417 case PIPE_CAP_TGSI_VOTE
:
420 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
423 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
424 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
427 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
428 return sscreen
->b
.has_streamout
? 4 : 0;
429 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
430 return sscreen
->b
.has_streamout
? 1 : 0;
431 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
432 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
433 return sscreen
->b
.has_streamout
? 32*4 : 0;
435 /* Geometry shader output. */
436 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
438 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
440 case PIPE_CAP_MAX_VERTEX_STREAMS
:
443 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
447 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
448 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
449 return 15; /* 16384 */
450 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
451 /* textures support 8192, but layered rendering supports 2048 */
453 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
454 /* textures support 8192, but layered rendering supports 2048 */
457 /* Render targets. */
458 case PIPE_CAP_MAX_RENDER_TARGETS
:
461 case PIPE_CAP_MAX_VIEWPORTS
:
462 return R600_MAX_VIEWPORTS
;
464 /* Timer queries, present when the clock frequency is non zero. */
465 case PIPE_CAP_QUERY_TIMESTAMP
:
466 case PIPE_CAP_QUERY_TIME_ELAPSED
:
467 return sscreen
->b
.info
.clock_crystal_freq
!= 0;
469 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
470 case PIPE_CAP_MIN_TEXEL_OFFSET
:
473 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
474 case PIPE_CAP_MAX_TEXEL_OFFSET
:
477 case PIPE_CAP_ENDIANNESS
:
478 return PIPE_ENDIAN_LITTLE
;
480 case PIPE_CAP_VENDOR_ID
:
481 return ATI_VENDOR_ID
;
482 case PIPE_CAP_DEVICE_ID
:
483 return sscreen
->b
.info
.pci_id
;
484 case PIPE_CAP_ACCELERATED
:
486 case PIPE_CAP_VIDEO_MEMORY
:
487 return sscreen
->b
.info
.vram_size
>> 20;
490 case PIPE_CAP_PCI_GROUP
:
491 return sscreen
->b
.info
.pci_domain
;
492 case PIPE_CAP_PCI_BUS
:
493 return sscreen
->b
.info
.pci_bus
;
494 case PIPE_CAP_PCI_DEVICE
:
495 return sscreen
->b
.info
.pci_dev
;
496 case PIPE_CAP_PCI_FUNCTION
:
497 return sscreen
->b
.info
.pci_func
;
502 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
504 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
508 case PIPE_SHADER_FRAGMENT
:
509 case PIPE_SHADER_VERTEX
:
510 case PIPE_SHADER_GEOMETRY
:
512 case PIPE_SHADER_TESS_CTRL
:
513 case PIPE_SHADER_TESS_EVAL
:
514 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
515 if (HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 2)
518 case PIPE_SHADER_COMPUTE
:
520 case PIPE_SHADER_CAP_PREFERRED_IR
:
521 return PIPE_SHADER_IR_NATIVE
;
523 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
524 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
526 /* Old kernels disallowed some register writes for SI
527 * that are used for indirect dispatches. */
528 if (HAVE_LLVM
>= 0x309 && (sscreen
->b
.chip_class
>= CIK
||
529 sscreen
->b
.info
.drm_major
== 3 ||
530 (sscreen
->b
.info
.drm_major
== 2 &&
531 sscreen
->b
.info
.drm_minor
>= 45)))
532 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
536 case PIPE_SHADER_CAP_DOUBLES
:
537 return HAVE_LLVM
>= 0x0307;
539 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
540 uint64_t max_const_buffer_size
;
541 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
542 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
543 &max_const_buffer_size
);
544 return max_const_buffer_size
;
547 /* If compute shaders don't require a special value
548 * for this cap, we can return the same value we
549 * do for other shader types. */
558 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
559 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
560 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
561 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
563 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
565 case PIPE_SHADER_CAP_MAX_INPUTS
:
566 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
567 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
568 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
569 case PIPE_SHADER_CAP_MAX_TEMPS
:
570 return 256; /* Max native temporaries. */
571 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
572 return 4096 * sizeof(float[4]); /* actually only memory limits this */
573 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
574 return SI_NUM_CONST_BUFFERS
;
575 case PIPE_SHADER_CAP_MAX_PREDS
:
576 return 0; /* FIXME */
577 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
579 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
581 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
582 /* Indirection of geometry shader input dimension is not
585 return shader
!= PIPE_SHADER_GEOMETRY
;
586 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
587 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
588 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
590 case PIPE_SHADER_CAP_INTEGERS
:
592 case PIPE_SHADER_CAP_SUBROUTINES
:
594 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
595 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
596 return SI_NUM_SAMPLERS
;
597 case PIPE_SHADER_CAP_PREFERRED_IR
:
598 return PIPE_SHADER_IR_TGSI
;
599 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
601 case PIPE_SHADER_CAP_DOUBLES
:
602 return HAVE_LLVM
>= 0x0307;
603 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
604 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
606 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
607 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
609 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
611 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
612 return HAVE_LLVM
>= 0x0309 ? SI_NUM_SHADER_BUFFERS
: 0;
613 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
614 return HAVE_LLVM
>= 0x0309 ? SI_NUM_IMAGES
: 0;
619 static void si_destroy_screen(struct pipe_screen
* pscreen
)
621 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
622 struct si_shader_part
*parts
[] = {
625 sscreen
->tcs_epilogs
,
634 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
637 /* Free shader parts. */
638 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
640 struct si_shader_part
*part
= parts
[i
];
642 parts
[i
] = part
->next
;
643 radeon_shader_binary_clean(&part
->binary
);
647 pipe_mutex_destroy(sscreen
->shader_parts_mutex
);
648 si_destroy_shader_cache(sscreen
);
649 r600_destroy_common_screen(&sscreen
->b
);
652 static bool si_init_gs_info(struct si_screen
*sscreen
)
654 switch (sscreen
->b
.family
) {
663 sscreen
->gs_table_depth
= 16;
674 sscreen
->gs_table_depth
= 32;
681 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
683 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
689 /* Set functions first. */
690 sscreen
->b
.b
.context_create
= si_create_context
;
691 sscreen
->b
.b
.destroy
= si_destroy_screen
;
692 sscreen
->b
.b
.get_param
= si_get_param
;
693 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
694 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
695 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
697 si_init_screen_state_functions(sscreen
);
699 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
700 !si_init_gs_info(sscreen
) ||
701 !si_init_shader_cache(sscreen
)) {
706 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE
))
707 si_init_perfcounters(sscreen
);
709 sscreen
->b
.has_cp_dma
= true;
710 sscreen
->b
.has_streamout
= true;
711 pipe_mutex_init(sscreen
->shader_parts_mutex
);
712 sscreen
->use_monolithic_shaders
=
713 HAVE_LLVM
< 0x0308 ||
714 (sscreen
->b
.debug_flags
& DBG_MONOLITHIC_SHADERS
) != 0;
716 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
717 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
719 /* Create the auxiliary context. This must be done last. */
720 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
722 if (sscreen
->b
.debug_flags
& DBG_TEST_DMA
)
723 r600_test_dma(&sscreen
->b
);
725 return &sscreen
->b
.b
;