src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_suballoc.h"
  32 #include "util/u_tests.h"
  33 #include "vl/vl_decoder.h"
  34 #include "../ddebug/dd_util.h"
  35
  36 #define SI_LLVM_DEFAULT_FEATURES \
  37         "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
  38
  39 /*
  40  * pipe_context
  41  */
  42 static void si_destroy_context(struct pipe_context *context)
  43 {
  44         struct si_context *sctx = (struct si_context *)context;
  45         int i;
  46
  47         /* Unreference the framebuffer normally to disable related logic
  48          * properly.
  49          */
  50         struct pipe_framebuffer_state fb = {};
  51         context->set_framebuffer_state(context, &fb);
  52
  53         si_release_all_descriptors(sctx);
  54
  55         if (sctx->ce_suballocator)
  56                 u_suballocator_destroy(sctx->ce_suballocator);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67
  68         si_pm4_free_state(sctx, sctx->init_config, ~0);
  69         if (sctx->init_config_gs_rings)
  70                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  71         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  72                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  73
  74         if (sctx->fixed_func_tcs_shader.cso)
  75                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  76         if (sctx->custom_dsa_flush)
  77                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  78         if (sctx->custom_blend_resolve)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  80         if (sctx->custom_blend_decompress)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  82         if (sctx->custom_blend_fastclear)
  83                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  84         if (sctx->custom_blend_dcc_decompress)
  85                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  86
  87         if (sctx->blitter)
  88                 util_blitter_destroy(sctx->blitter);
  89
  90         r600_common_context_cleanup(&sctx->b);
  91
  92         LLVMDisposeTargetMachine(sctx->tm);
  93
  94         r600_resource_reference(&sctx->trace_buf, NULL);
  95         r600_resource_reference(&sctx->last_trace_buf, NULL);
  96         radeon_clear_saved_cs(&sctx->last_gfx);
  97
  98         FREE(sctx);
  99 }
 100
 101 static enum pipe_reset_status
 102 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 103 {
 104         struct si_context *sctx = (struct si_context *)ctx;
 105
 106         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 107 }
 108
 109 /* Apitrace profiling:
 110  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 111  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 112  *      and remember its number.
 113  *   3) In Mesa, enable queries and performance counters around that draw
 114  *      call and print the results.
 115  *   4) glretrace --benchmark --markers ..
 116  */
 117 static void si_emit_string_marker(struct pipe_context *ctx,
 118                                   const char *string, int len)
 119 {
 120         struct si_context *sctx = (struct si_context *)ctx;
 121
 122         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 123 }
 124
 125 static LLVMTargetMachineRef
 126 si_create_llvm_target_machine(struct si_screen *sscreen)
 127 {
 128         const char *triple = "amdgcn--";
 129
 130         return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
 131                                        r600_get_llvm_processor_name(sscreen->b.family),
 132                                        sscreen->b.debug_flags & DBG_SI_SCHED ?
 133                                                SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 134                                                SI_LLVM_DEFAULT_FEATURES,
 135                                        LLVMCodeGenLevelDefault,
 136                                        LLVMRelocDefault,
 137                                        LLVMCodeModelDefault);
 138 }
 139
 140 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 141                                               void *priv, unsigned flags)
 142 {
 143         struct si_context *sctx = CALLOC_STRUCT(si_context);
 144         struct si_screen* sscreen = (struct si_screen *)screen;
 145         struct radeon_winsys *ws = sscreen->b.ws;
 146         int shader, i;
 147
 148         if (!sctx)
 149                 return NULL;
 150
 151         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 152                 flags |= PIPE_CONTEXT_DEBUG;
 153
 154         if (flags & PIPE_CONTEXT_DEBUG)
 155                 sscreen->record_llvm_ir = true; /* racy but not critical */
 156
 157         sctx->b.b.screen = screen; /* this must be set first */
 158         sctx->b.b.priv = priv;
 159         sctx->b.b.destroy = si_destroy_context;
 160         sctx->b.b.emit_string_marker = si_emit_string_marker;
 161         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 162         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 163         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 164
 165         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 166                 goto fail;
 167
 168         if (sscreen->b.info.drm_major == 3)
 169                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 170
 171         si_init_blit_functions(sctx);
 172         si_init_compute_functions(sctx);
 173         si_init_cp_dma_functions(sctx);
 174         si_init_debug_functions(sctx);
 175
 176         if (sscreen->b.info.has_uvd) {
 177                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 178                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 179         } else {
 180                 sctx->b.b.create_video_codec = vl_create_decoder;
 181                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 182         }
 183
 184         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 185                                        si_context_gfx_flush, sctx);
 186
 187         /* SI + AMDGPU + CE = GPU hang */
 188         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 189             sscreen->b.chip_class != SI &&
 190             /* These can't use CE due to a power gating bug in the kernel. */
 191             sscreen->b.family != CHIP_CARRIZO &&
 192             sscreen->b.family != CHIP_STONEY &&
 193             /* Some CE bug is causing green screen corruption w/ MPV video
 194              * playback and occasional corruption w/ 3D. */
 195             sscreen->b.chip_class != GFX9) {
 196                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 197                 if (!sctx->ce_ib)
 198                         goto fail;
 199
 200                 if (ws->cs_add_const_preamble_ib) {
 201                         sctx->ce_preamble_ib =
 202                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 203
 204                         if (!sctx->ce_preamble_ib)
 205                                 goto fail;
 206                 }
 207
 208                 sctx->ce_suballocator =
 209                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 210                                               PIPE_USAGE_DEFAULT,
 211                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 212                 if (!sctx->ce_suballocator)
 213                         goto fail;
 214         }
 215
 216         sctx->b.gfx.flush = si_context_gfx_flush;
 217
 218         /* Border colors. */
 219         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 220                                           sizeof(*sctx->border_color_table));
 221         if (!sctx->border_color_table)
 222                 goto fail;
 223
 224         sctx->border_color_buffer = (struct r600_resource*)
 225                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 226                                    SI_MAX_BORDER_COLORS *
 227                                    sizeof(*sctx->border_color_table));
 228         if (!sctx->border_color_buffer)
 229                 goto fail;
 230
 231         sctx->border_color_map =
 232                 ws->buffer_map(sctx->border_color_buffer->buf,
 233                                NULL, PIPE_TRANSFER_WRITE);
 234         if (!sctx->border_color_map)
 235                 goto fail;
 236
 237         si_init_all_descriptors(sctx);
 238         si_init_state_functions(sctx);
 239         si_init_shader_functions(sctx);
 240         si_init_ia_multi_vgt_param_table(sctx);
 241
 242         if (sctx->b.chip_class >= CIK)
 243                 cik_init_sdma_functions(sctx);
 244         else
 245                 si_init_dma_functions(sctx);
 246
 247         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 248                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 249
 250         sctx->blitter = util_blitter_create(&sctx->b.b);
 251         if (sctx->blitter == NULL)
 252                 goto fail;
 253         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 254
 255         sctx->sample_mask.sample_mask = 0xffff;
 256
 257         /* these must be last */
 258         si_begin_new_cs(sctx);
 259
 260         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 261          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 262         if (sctx->b.chip_class == CIK) {
 263                 sctx->null_const_buf.buffer =
 264                         r600_aligned_buffer_create(screen,
 265                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 266                                                    PIPE_USAGE_DEFAULT, 16,
 267                                                    sctx->screen->b.info.tcc_cache_line_size);
 268                 if (!sctx->null_const_buf.buffer)
 269                         goto fail;
 270                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 271
 272                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 273                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 274                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 275                                                               &sctx->null_const_buf);
 276                         }
 277                 }
 278
 279                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 280                                  &sctx->null_const_buf);
 281                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 282                                  &sctx->null_const_buf);
 283                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 284                                  &sctx->null_const_buf);
 285                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 286                                  &sctx->null_const_buf);
 287
 288                 /* Clear the NULL constant buffer, because loads should return zeros. */
 289                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 290                                      sctx->null_const_buf.buffer->width0, 0,
 291                                      R600_COHERENCY_SHADER);
 292         }
 293
 294         uint64_t max_threads_per_block;
 295         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 296                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 297                                   &max_threads_per_block);
 298
 299         /* The maximum number of scratch waves. Scratch space isn't divided
 300          * evenly between CUs. The number is only a function of the number of CUs.
 301          * We can decrease the constant to decrease the scratch buffer size.
 302          *
 303          * sctx->scratch_waves must be >= the maximum posible size of
 304          * 1 threadgroup, so that the hw doesn't hang from being unable
 305          * to start any.
 306          *
 307          * The recommended value is 4 per CU at most. Higher numbers don't
 308          * bring much benefit, but they still occupy chip resources (think
 309          * async compute). I've seen ~2% performance difference between 4 and 32.
 310          */
 311         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 312                                    max_threads_per_block / 64);
 313
 314         sctx->tm = si_create_llvm_target_machine(sscreen);
 315
 316         return &sctx->b.b;
 317 fail:
 318         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 319         si_destroy_context(&sctx->b.b);
 320         return NULL;
 321 }
 322
 323 /*
 324  * pipe_screen
 325  */
 326 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 327 {
 328         /* Old kernels disallowed some register writes for SI
 329          * that are used for indirect dispatches. */
 330         return (sscreen->b.chip_class >= CIK ||
 331                 sscreen->b.info.drm_major == 3 ||
 332                 (sscreen->b.info.drm_major == 2 &&
 333                  sscreen->b.info.drm_minor >= 45));
 334 }
 335
 336 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 337 {
 338         struct si_screen *sscreen = (struct si_screen *)pscreen;
 339
 340         switch (param) {
 341         /* Supported features (boolean caps). */
 342         case PIPE_CAP_ACCELERATED:
 343         case PIPE_CAP_TWO_SIDED_STENCIL:
 344         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 345         case PIPE_CAP_ANISOTROPIC_FILTER:
 346         case PIPE_CAP_POINT_SPRITE:
 347         case PIPE_CAP_OCCLUSION_QUERY:
 348         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 349         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 350         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 351         case PIPE_CAP_TEXTURE_SWIZZLE:
 352         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 353         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 354         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 355         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 356         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 357         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 358         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 359         case PIPE_CAP_SM3:
 360         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 361         case PIPE_CAP_PRIMITIVE_RESTART:
 362         case PIPE_CAP_CONDITIONAL_RENDER:
 363         case PIPE_CAP_TEXTURE_BARRIER:
 364         case PIPE_CAP_INDEP_BLEND_ENABLE:
 365         case PIPE_CAP_INDEP_BLEND_FUNC:
 366         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 367         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 368         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 369         case PIPE_CAP_START_INSTANCE:
 370         case PIPE_CAP_NPOT_TEXTURES:
 371         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 372         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 373         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 374         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 375         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 376         case PIPE_CAP_TGSI_INSTANCEID:
 377         case PIPE_CAP_COMPUTE:
 378         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 379         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 380         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 381         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 382         case PIPE_CAP_CUBE_MAP_ARRAY:
 383         case PIPE_CAP_SAMPLE_SHADING:
 384         case PIPE_CAP_DRAW_INDIRECT:
 385         case PIPE_CAP_CLIP_HALFZ:
 386         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 387         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 388         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 389         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 390         case PIPE_CAP_TGSI_TEXCOORD:
 391         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 392         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 393         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 394         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 395         case PIPE_CAP_SHAREABLE_SHADERS:
 396         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 397         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 398         case PIPE_CAP_TEXTURE_QUERY_LOD:
 399         case PIPE_CAP_TEXTURE_GATHER_SM5:
 400         case PIPE_CAP_TGSI_TXQS:
 401         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 402         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 403         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 404         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 405         case PIPE_CAP_INVALIDATE_BUFFER:
 406         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 407         case PIPE_CAP_QUERY_MEMORY_INFO:
 408         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 409         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 410         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 411         case PIPE_CAP_GENERATE_MIPMAP:
 412         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 413         case PIPE_CAP_STRING_MARKER:
 414         case PIPE_CAP_CLEAR_TEXTURE:
 415         case PIPE_CAP_CULL_DISTANCE:
 416         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 417         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 418         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 419         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 420         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 421         case PIPE_CAP_DOUBLES:
 422         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 423         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 424         case PIPE_CAP_INT64:
 425         case PIPE_CAP_INT64_DIVMOD:
 426         case PIPE_CAP_TGSI_CLOCK:
 427                 return 1;
 428
 429         case PIPE_CAP_TGSI_VOTE:
 430                 return HAVE_LLVM >= 0x0400;
 431
 432         case PIPE_CAP_TGSI_BALLOT:
 433                 return HAVE_LLVM >= 0x0500;
 434
 435         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 436                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 437
 438         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 439                 return (sscreen->b.info.drm_major == 2 &&
 440                         sscreen->b.info.drm_minor >= 43) ||
 441                        sscreen->b.info.drm_major == 3;
 442
 443         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 444                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 445                 return sscreen->b.chip_class < CIK ||
 446                        (sscreen->b.info.drm_major == 2 &&
 447                         sscreen->b.info.drm_minor >= 35) ||
 448                        sscreen->b.info.drm_major == 3;
 449
 450         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 451                 return R600_MAP_BUFFER_ALIGNMENT;
 452
 453         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 454         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 455         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 456         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 457         case PIPE_CAP_MAX_VERTEX_STREAMS:
 458         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 459                 return 4;
 460
 461         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 462                 if (si_have_tgsi_compute(sscreen))
 463                         return 450;
 464                 return 420;
 465
 466         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 467                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 468
 469         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 470         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 471         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 472                 /* SI doesn't support unaligned loads.
 473                  * CIK needs DRM 2.50.0 on radeon. */
 474                 return sscreen->b.chip_class == SI ||
 475                        (sscreen->b.info.drm_major == 2 &&
 476                         sscreen->b.info.drm_minor < 50);
 477
 478         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 479                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 480                  * faults are mitigated in software.
 481                  */
 482                 if (sscreen->b.chip_class >= CIK &&
 483                     sscreen->b.info.drm_major == 3 &&
 484                     sscreen->b.info.drm_minor >= 13)
 485                         return RADEON_SPARSE_PAGE_SIZE;
 486                 return 0;
 487
 488         /* Unsupported features. */
 489         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 490         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 491         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 492         case PIPE_CAP_USER_VERTEX_BUFFERS:
 493         case PIPE_CAP_FAKE_SW_MSAA:
 494         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 495         case PIPE_CAP_VERTEXID_NOBASE:
 496         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 497         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 498         case PIPE_CAP_NATIVE_FENCE_FD:
 499         case PIPE_CAP_TGSI_FS_FBFETCH:
 500         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 501         case PIPE_CAP_UMA:
 502         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 503                 return 0;
 504
 505         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 506                 return si_have_tgsi_compute(sscreen);
 507
 508         case PIPE_CAP_DRAW_PARAMETERS:
 509         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 510         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 511                 return sscreen->has_draw_indirect_multi;
 512
 513         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 514                 return 30;
 515
 516         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 517                 return sscreen->b.chip_class <= VI ?
 518                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 519
 520         /* Stream output. */
 521         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 522         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 523                 return 32*4;
 524
 525         /* Geometry shader output. */
 526         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 527                 return 1024;
 528         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 529                 return 4095;
 530
 531         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 532                 return 2048;
 533
 534         /* Texturing. */
 535         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 536         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 537                 return 15; /* 16384 */
 538         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 539                 /* textures support 8192, but layered rendering supports 2048 */
 540                 return 12;
 541         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 542                 /* textures support 8192, but layered rendering supports 2048 */
 543                 return 2048;
 544
 545         /* Viewports and render targets. */
 546         case PIPE_CAP_MAX_VIEWPORTS:
 547                 return R600_MAX_VIEWPORTS;
 548         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 549         case PIPE_CAP_MAX_RENDER_TARGETS:
 550                 return 8;
 551
 552         /* Timer queries, present when the clock frequency is non zero. */
 553         case PIPE_CAP_QUERY_TIMESTAMP:
 554         case PIPE_CAP_QUERY_TIME_ELAPSED:
 555                 return sscreen->b.info.clock_crystal_freq != 0;
 556
 557         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 558         case PIPE_CAP_MIN_TEXEL_OFFSET:
 559                 return -32;
 560
 561         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 562         case PIPE_CAP_MAX_TEXEL_OFFSET:
 563                 return 31;
 564
 565         case PIPE_CAP_ENDIANNESS:
 566                 return PIPE_ENDIAN_LITTLE;
 567
 568         case PIPE_CAP_VENDOR_ID:
 569                 return ATI_VENDOR_ID;
 570         case PIPE_CAP_DEVICE_ID:
 571                 return sscreen->b.info.pci_id;
 572         case PIPE_CAP_VIDEO_MEMORY:
 573                 return sscreen->b.info.vram_size >> 20;
 574         case PIPE_CAP_PCI_GROUP:
 575                 return sscreen->b.info.pci_domain;
 576         case PIPE_CAP_PCI_BUS:
 577                 return sscreen->b.info.pci_bus;
 578         case PIPE_CAP_PCI_DEVICE:
 579                 return sscreen->b.info.pci_dev;
 580         case PIPE_CAP_PCI_FUNCTION:
 581                 return sscreen->b.info.pci_func;
 582         }
 583         return 0;
 584 }
 585
 586 static int si_get_shader_param(struct pipe_screen* pscreen,
 587                                enum pipe_shader_type shader,
 588                                enum pipe_shader_cap param)
 589 {
 590         struct si_screen *sscreen = (struct si_screen *)pscreen;
 591
 592         switch(shader)
 593         {
 594         case PIPE_SHADER_FRAGMENT:
 595         case PIPE_SHADER_VERTEX:
 596         case PIPE_SHADER_GEOMETRY:
 597         case PIPE_SHADER_TESS_CTRL:
 598         case PIPE_SHADER_TESS_EVAL:
 599                 break;
 600         case PIPE_SHADER_COMPUTE:
 601                 switch (param) {
 602                 case PIPE_SHADER_CAP_PREFERRED_IR:
 603                         return PIPE_SHADER_IR_NATIVE;
 604
 605                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 606                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 607
 608                         if (si_have_tgsi_compute(sscreen))
 609                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 610
 611                         return ir;
 612                 }
 613
 614                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 615                         uint64_t max_const_buffer_size;
 616                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 617                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 618                                 &max_const_buffer_size);
 619                         return MIN2(max_const_buffer_size, INT_MAX);
 620                 }
 621                 default:
 622                         /* If compute shaders don't require a special value
 623                          * for this cap, we can return the same value we
 624                          * do for other shader types. */
 625                         break;
 626                 }
 627                 break;
 628         default:
 629                 return 0;
 630         }
 631
 632         switch (param) {
 633         /* Shader limits. */
 634         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 635         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 636         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 637         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 638         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 639                 return 16384;
 640         case PIPE_SHADER_CAP_MAX_INPUTS:
 641                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 642         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 643                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 644         case PIPE_SHADER_CAP_MAX_TEMPS:
 645                 return 256; /* Max native temporaries. */
 646         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 647                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 648         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 649                 return SI_NUM_CONST_BUFFERS;
 650         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 651         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 652                 return SI_NUM_SAMPLERS;
 653         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 654                 return SI_NUM_SHADER_BUFFERS;
 655         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 656                 return SI_NUM_IMAGES;
 657         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 658                 return 32;
 659         case PIPE_SHADER_CAP_PREFERRED_IR:
 660                 return PIPE_SHADER_IR_TGSI;
 661         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 662                 return 3;
 663
 664         /* Supported boolean features. */
 665         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 666         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 667         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 668         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 669         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 670         case PIPE_SHADER_CAP_INTEGERS:
 671         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 672         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 673         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 674                 return 1;
 675
 676         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 677                 /* TODO: Indirection of geometry shader input dimension is not
 678                  * handled yet
 679                  */
 680                 return shader != PIPE_SHADER_GEOMETRY;
 681
 682         /* Unsupported boolean features. */
 683         case PIPE_SHADER_CAP_SUBROUTINES:
 684         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 685         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 686         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 687                 return 0;
 688         }
 689         return 0;
 690 }
 691
 692 static void si_destroy_screen(struct pipe_screen* pscreen)
 693 {
 694         struct si_screen *sscreen = (struct si_screen *)pscreen;
 695         struct si_shader_part *parts[] = {
 696                 sscreen->vs_prologs,
 697                 sscreen->tcs_epilogs,
 698                 sscreen->gs_prologs,
 699                 sscreen->ps_prologs,
 700                 sscreen->ps_epilogs
 701         };
 702         unsigned i;
 703
 704         if (!sscreen->b.ws->unref(sscreen->b.ws))
 705                 return;
 706
 707         util_queue_destroy(&sscreen->shader_compiler_queue);
 708
 709         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 710                 if (sscreen->tm[i])
 711                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 712
 713         /* Free shader parts. */
 714         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 715                 while (parts[i]) {
 716                         struct si_shader_part *part = parts[i];
 717
 718                         parts[i] = part->next;
 719                         radeon_shader_binary_clean(&part->binary);
 720                         FREE(part);
 721                 }
 722         }
 723         mtx_destroy(&sscreen->shader_parts_mutex);
 724         si_destroy_shader_cache(sscreen);
 725         r600_destroy_common_screen(&sscreen->b);
 726 }
 727
 728 static bool si_init_gs_info(struct si_screen *sscreen)
 729 {
 730         switch (sscreen->b.family) {
 731         case CHIP_OLAND:
 732         case CHIP_HAINAN:
 733         case CHIP_KAVERI:
 734         case CHIP_KABINI:
 735         case CHIP_MULLINS:
 736         case CHIP_ICELAND:
 737         case CHIP_CARRIZO:
 738         case CHIP_STONEY:
 739                 sscreen->gs_table_depth = 16;
 740                 return true;
 741         case CHIP_TAHITI:
 742         case CHIP_PITCAIRN:
 743         case CHIP_VERDE:
 744         case CHIP_BONAIRE:
 745         case CHIP_HAWAII:
 746         case CHIP_TONGA:
 747         case CHIP_FIJI:
 748         case CHIP_POLARIS10:
 749         case CHIP_POLARIS11:
 750         case CHIP_POLARIS12:
 751         case CHIP_VEGA10:
 752                 sscreen->gs_table_depth = 32;
 753                 return true;
 754         default:
 755                 return false;
 756         }
 757 }
 758
 759 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 760 {
 761         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 762         unsigned i;
 763
 764         if (!family)
 765                 return;
 766
 767         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 768                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 769                         /* Override family and chip_class. */
 770                         sscreen->b.family = sscreen->b.info.family = i;
 771
 772                         if (i >= CHIP_VEGA10)
 773                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 774                         else if (i >= CHIP_TONGA)
 775                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 776                         else if (i >= CHIP_BONAIRE)
 777                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 778                         else
 779                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 780
 781                         /* Don't submit any IBs. */
 782                         setenv("RADEON_NOOP", "1", 1);
 783                         return;
 784                 }
 785         }
 786
 787         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 788         exit(1);
 789 }
 790
 791 static void si_test_vmfault(struct si_screen *sscreen)
 792 {
 793         struct pipe_context *ctx = sscreen->b.aux_context;
 794         struct si_context *sctx = (struct si_context *)ctx;
 795         struct pipe_resource *buf =
 796                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 797
 798         if (!buf) {
 799                 puts("Buffer allocation failed.");
 800                 exit(1);
 801         }
 802
 803         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 804
 805         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 806                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 807                 ctx->flush(ctx, NULL, 0);
 808                 puts("VM fault test: CP - done.");
 809         }
 810         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 811                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 812                 ctx->flush(ctx, NULL, 0);
 813                 puts("VM fault test: SDMA - done.");
 814         }
 815         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 816                 util_test_constant_buffer(ctx, buf);
 817                 puts("VM fault test: Shader - done.");
 818         }
 819         exit(0);
 820 }
 821
 822 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 823 {
 824         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 825         unsigned num_cpus, num_compiler_threads, i;
 826
 827         if (!sscreen) {
 828                 return NULL;
 829         }
 830
 831         /* Set functions first. */
 832         sscreen->b.b.context_create = si_create_context;
 833         sscreen->b.b.destroy = si_destroy_screen;
 834         sscreen->b.b.get_param = si_get_param;
 835         sscreen->b.b.get_shader_param = si_get_shader_param;
 836         sscreen->b.b.resource_create = r600_resource_create_common;
 837
 838         si_init_screen_state_functions(sscreen);
 839
 840         if (!r600_common_screen_init(&sscreen->b, ws) ||
 841             !si_init_gs_info(sscreen) ||
 842             !si_init_shader_cache(sscreen)) {
 843                 FREE(sscreen);
 844                 return NULL;
 845         }
 846
 847         /* Only enable as many threads as we have target machines and CPUs. */
 848         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 849         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 850
 851         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 852                              32, num_compiler_threads)) {
 853                 si_destroy_shader_cache(sscreen);
 854                 FREE(sscreen);
 855                 return NULL;
 856         }
 857
 858         si_handle_env_var_force_family(sscreen);
 859
 860         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 861                 si_init_perfcounters(sscreen);
 862
 863         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 864          * around by setting 4K granularity.
 865          */
 866         sscreen->tess_offchip_block_dw_size =
 867                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 868
 869         sscreen->has_distributed_tess =
 870                 sscreen->b.chip_class >= VI &&
 871                 sscreen->b.info.max_se >= 2;
 872
 873         sscreen->has_draw_indirect_multi =
 874                 (sscreen->b.family >= CHIP_POLARIS10) ||
 875                 (sscreen->b.chip_class == VI &&
 876                  sscreen->b.info.pfp_fw_version >= 121 &&
 877                  sscreen->b.info.me_fw_version >= 87) ||
 878                 (sscreen->b.chip_class == CIK &&
 879                  sscreen->b.info.pfp_fw_version >= 211 &&
 880                  sscreen->b.info.me_fw_version >= 173) ||
 881                 (sscreen->b.chip_class == SI &&
 882                  sscreen->b.info.pfp_fw_version >= 121 &&
 883                  sscreen->b.info.me_fw_version >= 87);
 884
 885         sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
 886         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
 887                                             sscreen->b.family <= CHIP_POLARIS12) ||
 888                                            sscreen->b.family == CHIP_VEGA10;
 889
 890         sscreen->b.has_cp_dma = true;
 891         sscreen->b.has_streamout = true;
 892
 893         /* Some chips have RB+ registers, but don't support RB+. Those must
 894          * always disable it.
 895          */
 896         if (sscreen->b.family == CHIP_STONEY ||
 897             sscreen->b.chip_class >= GFX9) {
 898                 sscreen->b.has_rbplus = true;
 899
 900                 sscreen->b.rbplus_allowed =
 901                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
 902                         sscreen->b.family == CHIP_STONEY;
 903         }
 904
 905         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
 906         sscreen->use_monolithic_shaders =
 907                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 908
 909         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 910                                             SI_CONTEXT_INV_VMEM_L1 |
 911                                             SI_CONTEXT_INV_GLOBAL_L2;
 912         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
 913
 914         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 915                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 916
 917         for (i = 0; i < num_compiler_threads; i++)
 918                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 919
 920         /* Create the auxiliary context. This must be done last. */
 921         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 922
 923         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 924                 r600_test_dma(&sscreen->b);
 925
 926         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
 927                                       DBG_TEST_VMFAULT_SDMA |
 928                                       DBG_TEST_VMFAULT_SHADER))
 929                 si_test_vmfault(sscreen);
 930
 931         return &sscreen->b.b;
 932 }