src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  37               unsigned flags)
  38 {
  39         struct si_context *sctx = (struct si_context *)ctx;
  40         struct pipe_query *render_cond = NULL;
  41         boolean render_cond_cond = FALSE;
  42         unsigned render_cond_mode = 0;
  43
  44         if (fence) {
  45                 *fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
  46         }
  47
  48         /* Disable render condition. */
  49         if (sctx->b.current_render_cond) {
  50                 render_cond = sctx->b.current_render_cond;
  51                 render_cond_cond = sctx->b.current_render_cond_cond;
  52                 render_cond_mode = sctx->b.current_render_cond_mode;
  53                 ctx->render_condition(ctx, NULL, FALSE, 0);
  54         }
  55
  56         si_context_flush(sctx, flags);
  57
  58         /* Re-enable render condition. */
  59         if (render_cond) {
  60                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  61         }
  62 }
  63
  64 static void si_flush_from_st(struct pipe_context *ctx,
  65                              struct pipe_fence_handle **fence,
  66                              unsigned flags)
  67 {
  68         si_flush(ctx, fence,
  69                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  70 }
  71
  72 static void si_flush_from_winsys(void *ctx, unsigned flags)
  73 {
  74         si_flush((struct pipe_context*)ctx, NULL, flags);
  75 }
  76
  77 static void si_destroy_context(struct pipe_context *context)
  78 {
  79         struct si_context *sctx = (struct si_context *)context;
  80
  81         si_release_all_descriptors(sctx);
  82
  83         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  84         r600_resource_reference(&sctx->border_color_table, NULL);
  85
  86         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  87         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  88         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  89
  90         if (sctx->dummy_pixel_shader) {
  91                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  92         }
  93         for (int i = 0; i < 8; i++) {
  94                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  95                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  96                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  97         }
  98         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  99         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
 100         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
 101         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
 102         util_unreference_framebuffer_state(&sctx->framebuffer.state);
 103
 104         util_blitter_destroy(sctx->blitter);
 105
 106         si_pm4_cleanup(sctx);
 107
 108         r600_common_context_cleanup(&sctx->b);
 109         FREE(sctx);
 110 }
 111
 112 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
 113 {
 114         struct si_context *sctx = CALLOC_STRUCT(si_context);
 115         struct si_screen* sscreen = (struct si_screen *)screen;
 116         int shader, i;
 117
 118         if (sctx == NULL)
 119                 return NULL;
 120
 121         sctx->b.b.screen = screen; /* this must be set first */
 122         sctx->b.b.priv = priv;
 123         sctx->b.b.destroy = si_destroy_context;
 124         sctx->b.b.flush = si_flush_from_st;
 125         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 126
 127         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 128                 goto fail;
 129
 130         si_init_blit_functions(sctx);
 131         si_init_compute_functions(sctx);
 132
 133         if (sscreen->b.info.has_uvd) {
 134                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 135                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 136         } else {
 137                 sctx->b.b.create_video_codec = vl_create_decoder;
 138                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 139         }
 140
 141         sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
 142         sctx->b.rings.gfx.flush = si_flush_from_winsys;
 143
 144         si_init_all_descriptors(sctx);
 145
 146         /* Initialize cache_flush. */
 147         sctx->cache_flush = si_atom_cache_flush;
 148         sctx->atoms.cache_flush = &sctx->cache_flush;
 149
 150         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 151         sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
 152
 153         switch (sctx->b.chip_class) {
 154         case SI:
 155         case CIK:
 156                 si_init_state_functions(sctx);
 157                 si_init_config(sctx);
 158                 break;
 159         default:
 160                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 161                 goto fail;
 162         }
 163
 164         sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
 165
 166         sctx->blitter = util_blitter_create(&sctx->b.b);
 167         if (sctx->blitter == NULL)
 168                 goto fail;
 169
 170         sctx->dummy_pixel_shader =
 171                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 172                                                      TGSI_SEMANTIC_GENERIC,
 173                                                      TGSI_INTERPOLATE_CONSTANT);
 174         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 175
 176         /* these must be last */
 177         si_begin_new_cs(sctx);
 178         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 179
 180         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 181          * with a NULL buffer). We need to use a dummy buffer instead. */
 182         if (sctx->b.chip_class == CIK) {
 183                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 184                                                                  PIPE_USAGE_DEFAULT, 16);
 185                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 186
 187                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 188                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 189                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 190                                                               &sctx->null_const_buf);
 191                         }
 192                 }
 193
 194                 /* Clear the NULL constant buffer, because loads should return zeros. */
 195                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 196                                      sctx->null_const_buf.buffer->width0, 0);
 197         }
 198
 199         return &sctx->b.b;
 200 fail:
 201         si_destroy_context(&sctx->b.b);
 202         return NULL;
 203 }
 204
 205 /*
 206  * pipe_screen
 207  */
 208
 209 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 210 {
 211         struct si_screen *sscreen = (struct si_screen *)pscreen;
 212
 213         switch (param) {
 214         /* Supported features (boolean caps). */
 215         case PIPE_CAP_TWO_SIDED_STENCIL:
 216         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 217         case PIPE_CAP_ANISOTROPIC_FILTER:
 218         case PIPE_CAP_POINT_SPRITE:
 219         case PIPE_CAP_OCCLUSION_QUERY:
 220         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 221         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 222         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 223         case PIPE_CAP_TEXTURE_SWIZZLE:
 224         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 225         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 226         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 227         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 228         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 229         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 230         case PIPE_CAP_SM3:
 231         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 232         case PIPE_CAP_PRIMITIVE_RESTART:
 233         case PIPE_CAP_CONDITIONAL_RENDER:
 234         case PIPE_CAP_TEXTURE_BARRIER:
 235         case PIPE_CAP_INDEP_BLEND_ENABLE:
 236         case PIPE_CAP_INDEP_BLEND_FUNC:
 237         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 238         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 239         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 240         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 241         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 242         case PIPE_CAP_USER_INDEX_BUFFERS:
 243         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 244         case PIPE_CAP_START_INSTANCE:
 245         case PIPE_CAP_NPOT_TEXTURES:
 246         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 247         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 248         case PIPE_CAP_TGSI_INSTANCEID:
 249         case PIPE_CAP_COMPUTE:
 250         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 251         case PIPE_CAP_TGSI_VS_LAYER:
 252         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 253         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 254                 return 1;
 255
 256         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 257                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 258                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 259                                                sscreen->b.info.drm_minor >= 35);
 260
 261         case PIPE_CAP_TGSI_TEXCOORD:
 262                 return 0;
 263
 264         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 265                 return 64;
 266
 267         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 268                 return 256;
 269
 270         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 271                 return HAVE_LLVM >= 0x0305 ? 330 : 140;
 272
 273         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 274                 return 1;
 275         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 276                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 277
 278         /* Unsupported features. */
 279         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 280         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 281         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 282         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 283         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 284         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 285         case PIPE_CAP_USER_VERTEX_BUFFERS:
 286         case PIPE_CAP_CUBE_MAP_ARRAY:
 287         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 288         case PIPE_CAP_TEXTURE_GATHER_SM5:
 289                 return 0;
 290
 291         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 292                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 293
 294         /* Stream output. */
 295         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 296                 return sscreen->b.has_streamout ? 4 : 0;
 297         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 298                 return sscreen->b.has_streamout ? 1 : 0;
 299         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 300         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 301                 return sscreen->b.has_streamout ? 32*4 : 0;
 302
 303         /* Geometry shader output. */
 304         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 305                 return 1024;
 306         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 307                 return 4095;
 308
 309         /* Texturing. */
 310         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 311         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 312                 return 15; /* 16384 */
 313         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 314                 /* textures support 8192, but layered rendering supports 2048 */
 315                 return 12;
 316         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 317                 /* textures support 8192, but layered rendering supports 2048 */
 318                 return 2048;
 319
 320         /* Render targets. */
 321         case PIPE_CAP_MAX_RENDER_TARGETS:
 322                 return 8;
 323
 324         case PIPE_CAP_MAX_VIEWPORTS:
 325                 return 1;
 326
 327         /* Timer queries, present when the clock frequency is non zero. */
 328         case PIPE_CAP_QUERY_TIMESTAMP:
 329         case PIPE_CAP_QUERY_TIME_ELAPSED:
 330                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 331
 332         case PIPE_CAP_MIN_TEXEL_OFFSET:
 333                 return -8;
 334
 335         case PIPE_CAP_MAX_TEXEL_OFFSET:
 336                 return 7;
 337         case PIPE_CAP_ENDIANNESS:
 338                 return PIPE_ENDIAN_LITTLE;
 339         }
 340         return 0;
 341 }
 342
 343 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 344 {
 345         switch(shader)
 346         {
 347         case PIPE_SHADER_FRAGMENT:
 348         case PIPE_SHADER_VERTEX:
 349                 break;
 350         case PIPE_SHADER_GEOMETRY:
 351 #if HAVE_LLVM < 0x0305
 352                 return 0;
 353 #endif
 354                 break;
 355         case PIPE_SHADER_COMPUTE:
 356                 switch (param) {
 357                 case PIPE_SHADER_CAP_PREFERRED_IR:
 358                         return PIPE_SHADER_IR_LLVM;
 359                 default:
 360                         return 0;
 361                 }
 362         default:
 363                 /* TODO: support tessellation */
 364                 return 0;
 365         }
 366
 367         switch (param) {
 368         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 369         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 370         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 371         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 372                 return 16384;
 373         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 374                 return 32;
 375         case PIPE_SHADER_CAP_MAX_INPUTS:
 376                 return 32;
 377         case PIPE_SHADER_CAP_MAX_TEMPS:
 378                 return 256; /* Max native temporaries. */
 379         case PIPE_SHADER_CAP_MAX_ADDRS:
 380                 /* FIXME Isn't this equal to TEMPS? */
 381                 return 1; /* Max native address registers */
 382         case PIPE_SHADER_CAP_MAX_CONSTS:
 383                 return 4096; /* actually only memory limits this */
 384         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 385                 return NUM_PIPE_CONST_BUFFERS;
 386         case PIPE_SHADER_CAP_MAX_PREDS:
 387                 return 0; /* FIXME */
 388         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 389                 return 1;
 390         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 391                 return 0;
 392         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 393                 /* Indirection of geometry shader input dimension is not
 394                  * handled yet
 395                  */
 396                 return shader < PIPE_SHADER_GEOMETRY;
 397         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 398         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 399         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 400                 return 1;
 401         case PIPE_SHADER_CAP_INTEGERS:
 402                 return 1;
 403         case PIPE_SHADER_CAP_SUBROUTINES:
 404                 return 0;
 405         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 406         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 407                 return 16;
 408         case PIPE_SHADER_CAP_PREFERRED_IR:
 409                 return PIPE_SHADER_IR_TGSI;
 410         }
 411         return 0;
 412 }
 413
 414 static void si_destroy_screen(struct pipe_screen* pscreen)
 415 {
 416         struct si_screen *sscreen = (struct si_screen *)pscreen;
 417
 418         if (sscreen == NULL)
 419                 return;
 420
 421         if (!radeon_winsys_unref(sscreen->b.ws))
 422                 return;
 423
 424         r600_destroy_common_screen(&sscreen->b);
 425 }
 426
 427 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 428 {
 429         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 430         if (sscreen == NULL) {
 431                 return NULL;
 432         }
 433
 434         /* Set functions first. */
 435         sscreen->b.b.context_create = si_create_context;
 436         sscreen->b.b.destroy = si_destroy_screen;
 437         sscreen->b.b.get_param = si_get_param;
 438         sscreen->b.b.get_shader_param = si_get_shader_param;
 439         sscreen->b.b.is_format_supported = si_is_format_supported;
 440         sscreen->b.b.resource_create = r600_resource_create_common;
 441
 442         if (!r600_common_screen_init(&sscreen->b, ws)) {
 443                 FREE(sscreen);
 444                 return NULL;
 445         }
 446
 447         sscreen->b.has_cp_dma = true;
 448         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 449
 450         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 451                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 452
 453         /* Create the auxiliary context. This must be done last. */
 454         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 455
 456         return &sscreen->b.b;
 457 }