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0f58286fed126b2fc3dd0f0917bfa2ed4b445b12
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "sid.h"
30
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 static const struct debug_named_value debug_options[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS), "Print vertex shaders" },
47 { "ps", DBG(PS), "Print pixel shaders" },
48 { "gs", DBG(GS), "Print geometry shaders" },
49 { "tcs", DBG(TCS), "Print tessellation control shaders" },
50 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS), "Print compute shaders" },
52 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
56
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
60
61 /* Shader compiler options (with no effect on the shader cache): */
62 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
63 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
64 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
65 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
66
67 /* Information logging options: */
68 { "info", DBG(INFO), "Print driver information" },
69 { "tex", DBG(TEX), "Print texture info" },
70 { "compute", DBG(COMPUTE), "Print compute info" },
71 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
72
73 /* Driver options: */
74 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
75 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
76 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
77 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
78 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
79 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
80
81 /* 3D engine options: */
82 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
83 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
84 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
85 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
86 { "dpbb", DBG(DPBB), "Enable DPBB." },
87 { "dfsm", DBG(DFSM), "Enable DFSM." },
88 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
89 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
90 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
91 { "notiling", DBG(NO_TILING), "Disable tiling" },
92 { "nodcc", DBG(NO_DCC), "Disable DCC." },
93 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
94 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
95 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
96 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
97
98 /* Tests: */
99 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
100 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
101 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
102 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
103
104 DEBUG_NAMED_VALUE_END /* must be last */
105 };
106
107 static void si_init_compiler(struct si_screen *sscreen,
108 struct si_compiler *compiler)
109 {
110 enum ac_target_machine_options tm_options =
111 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
112 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
113 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
114 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
115
116 const char *triple;
117 ac_init_llvm_once();
118 compiler->tm = ac_create_target_machine(sscreen->info.family,
119 tm_options, &triple);
120 if (!compiler->tm)
121 return;
122
123 compiler->target_library_info =
124 gallivm_create_target_library_info(triple);
125 if (!compiler->target_library_info)
126 return;
127
128 compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
129 (sscreen->debug_flags & DBG(CHECK_IR)));
130 if (!compiler->passmgr)
131 return;
132 }
133
134 static void si_destroy_compiler(struct si_compiler *compiler)
135 {
136 if (compiler->passmgr)
137 LLVMDisposePassManager(compiler->passmgr);
138 #if HAVE_LLVM >= 0x0700
139 /* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
140 if (compiler->target_library_info)
141 gallivm_dispose_target_library_info(compiler->target_library_info);
142 #endif
143 if (compiler->tm)
144 LLVMDisposeTargetMachine(compiler->tm);
145 }
146
147 /*
148 * pipe_context
149 */
150 static void si_destroy_context(struct pipe_context *context)
151 {
152 struct si_context *sctx = (struct si_context *)context;
153 int i;
154
155 /* Unreference the framebuffer normally to disable related logic
156 * properly.
157 */
158 struct pipe_framebuffer_state fb = {};
159 if (context->set_framebuffer_state)
160 context->set_framebuffer_state(context, &fb);
161
162 si_release_all_descriptors(sctx);
163
164 pipe_resource_reference(&sctx->esgs_ring, NULL);
165 pipe_resource_reference(&sctx->gsvs_ring, NULL);
166 pipe_resource_reference(&sctx->tess_rings, NULL);
167 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
168 r600_resource_reference(&sctx->border_color_buffer, NULL);
169 free(sctx->border_color_table);
170 r600_resource_reference(&sctx->scratch_buffer, NULL);
171 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
172 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
173
174 si_pm4_free_state(sctx, sctx->init_config, ~0);
175 if (sctx->init_config_gs_rings)
176 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
177 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
178 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
179
180 if (sctx->fixed_func_tcs_shader.cso)
181 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
182 if (sctx->custom_dsa_flush)
183 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
184 if (sctx->custom_blend_resolve)
185 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
186 if (sctx->custom_blend_fmask_decompress)
187 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
188 if (sctx->custom_blend_eliminate_fastclear)
189 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
190 if (sctx->custom_blend_dcc_decompress)
191 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
192 if (sctx->vs_blit_pos)
193 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
194 if (sctx->vs_blit_pos_layered)
195 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
196 if (sctx->vs_blit_color)
197 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
198 if (sctx->vs_blit_color_layered)
199 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
200 if (sctx->vs_blit_texcoord)
201 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
202
203 if (sctx->blitter)
204 util_blitter_destroy(sctx->blitter);
205
206 /* Release DCC stats. */
207 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
208 assert(!sctx->dcc_stats[i].query_active);
209
210 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
211 if (sctx->dcc_stats[i].ps_stats[j])
212 sctx->b.destroy_query(&sctx->b,
213 sctx->dcc_stats[i].ps_stats[j]);
214
215 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
216 }
217
218 if (sctx->query_result_shader)
219 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
220
221 if (sctx->gfx_cs)
222 sctx->ws->cs_destroy(sctx->gfx_cs);
223 if (sctx->dma_cs)
224 sctx->ws->cs_destroy(sctx->dma_cs);
225 if (sctx->ctx)
226 sctx->ws->ctx_destroy(sctx->ctx);
227
228 if (sctx->b.stream_uploader)
229 u_upload_destroy(sctx->b.stream_uploader);
230 if (sctx->b.const_uploader)
231 u_upload_destroy(sctx->b.const_uploader);
232 if (sctx->cached_gtt_allocator)
233 u_upload_destroy(sctx->cached_gtt_allocator);
234
235 slab_destroy_child(&sctx->pool_transfers);
236 slab_destroy_child(&sctx->pool_transfers_unsync);
237
238 if (sctx->allocator_zeroed_memory)
239 u_suballocator_destroy(sctx->allocator_zeroed_memory);
240
241 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
242 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
243 r600_resource_reference(&sctx->eop_bug_scratch, NULL);
244
245 si_destroy_compiler(&sctx->compiler);
246
247 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
248
249 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
250 _mesa_hash_table_destroy(sctx->img_handles, NULL);
251
252 util_dynarray_fini(&sctx->resident_tex_handles);
253 util_dynarray_fini(&sctx->resident_img_handles);
254 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
255 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
256 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
257 FREE(sctx);
258 }
259
260 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
261 {
262 struct si_context *sctx = (struct si_context *)ctx;
263
264 if (sctx->screen->info.has_gpu_reset_status_query)
265 return sctx->ws->ctx_query_reset_status(sctx->ctx);
266
267 if (sctx->screen->info.has_gpu_reset_counter_query) {
268 unsigned latest = sctx->ws->query_value(sctx->ws,
269 RADEON_GPU_RESET_COUNTER);
270
271 if (sctx->gpu_reset_counter == latest)
272 return PIPE_NO_RESET;
273
274 sctx->gpu_reset_counter = latest;
275 return PIPE_UNKNOWN_CONTEXT_RESET;
276 }
277
278 return PIPE_NO_RESET;
279 }
280
281 static void si_set_device_reset_callback(struct pipe_context *ctx,
282 const struct pipe_device_reset_callback *cb)
283 {
284 struct si_context *sctx = (struct si_context *)ctx;
285
286 if (cb)
287 sctx->device_reset_callback = *cb;
288 else
289 memset(&sctx->device_reset_callback, 0,
290 sizeof(sctx->device_reset_callback));
291 }
292
293 bool si_check_device_reset(struct si_context *sctx)
294 {
295 enum pipe_reset_status status;
296
297 if (!sctx->device_reset_callback.reset)
298 return false;
299
300 if (!sctx->b.get_device_reset_status)
301 return false;
302
303 status = sctx->b.get_device_reset_status(&sctx->b);
304 if (status == PIPE_NO_RESET)
305 return false;
306
307 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
308 return true;
309 }
310
311 /* Apitrace profiling:
312 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
313 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
314 * and remember its number.
315 * 3) In Mesa, enable queries and performance counters around that draw
316 * call and print the results.
317 * 4) glretrace --benchmark --markers ..
318 */
319 static void si_emit_string_marker(struct pipe_context *ctx,
320 const char *string, int len)
321 {
322 struct si_context *sctx = (struct si_context *)ctx;
323
324 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
325
326 if (sctx->log)
327 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
328 }
329
330 static void si_set_debug_callback(struct pipe_context *ctx,
331 const struct pipe_debug_callback *cb)
332 {
333 struct si_context *sctx = (struct si_context *)ctx;
334 struct si_screen *screen = sctx->screen;
335
336 util_queue_finish(&screen->shader_compiler_queue);
337 util_queue_finish(&screen->shader_compiler_queue_low_priority);
338
339 if (cb)
340 sctx->debug = *cb;
341 else
342 memset(&sctx->debug, 0, sizeof(sctx->debug));
343 }
344
345 static void si_set_log_context(struct pipe_context *ctx,
346 struct u_log_context *log)
347 {
348 struct si_context *sctx = (struct si_context *)ctx;
349 sctx->log = log;
350
351 if (log)
352 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
353 }
354
355 static struct pipe_context *si_create_context(struct pipe_screen *screen,
356 unsigned flags)
357 {
358 struct si_context *sctx = CALLOC_STRUCT(si_context);
359 struct si_screen* sscreen = (struct si_screen *)screen;
360 struct radeon_winsys *ws = sscreen->ws;
361 int shader, i;
362
363 if (!sctx)
364 return NULL;
365
366 if (flags & PIPE_CONTEXT_DEBUG)
367 sscreen->record_llvm_ir = true; /* racy but not critical */
368
369 sctx->b.screen = screen; /* this must be set first */
370 sctx->b.priv = NULL;
371 sctx->b.destroy = si_destroy_context;
372 sctx->b.emit_string_marker = si_emit_string_marker;
373 sctx->b.set_debug_callback = si_set_debug_callback;
374 sctx->b.set_log_context = si_set_log_context;
375 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
376 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
377
378 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
379 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
380
381 sctx->ws = sscreen->ws;
382 sctx->family = sscreen->info.family;
383 sctx->chip_class = sscreen->info.chip_class;
384
385 if (sscreen->info.has_gpu_reset_counter_query) {
386 sctx->gpu_reset_counter =
387 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
388 }
389
390 sctx->b.get_device_reset_status = si_get_reset_status;
391 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
392
393 si_init_context_texture_functions(sctx);
394 si_init_query_functions(sctx);
395
396 if (sctx->chip_class == CIK ||
397 sctx->chip_class == VI ||
398 sctx->chip_class == GFX9) {
399 sctx->eop_bug_scratch = r600_resource(
400 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
401 16 * sscreen->info.num_render_backends));
402 if (!sctx->eop_bug_scratch)
403 goto fail;
404 }
405
406 sctx->allocator_zeroed_memory =
407 u_suballocator_create(&sctx->b, sscreen->info.gart_page_size,
408 0, PIPE_USAGE_DEFAULT, 0, true);
409 if (!sctx->allocator_zeroed_memory)
410 goto fail;
411
412 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
413 0, PIPE_USAGE_STREAM,
414 SI_RESOURCE_FLAG_READ_ONLY);
415 if (!sctx->b.stream_uploader)
416 goto fail;
417
418 sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024,
419 0, PIPE_USAGE_DEFAULT,
420 SI_RESOURCE_FLAG_32BIT |
421 (sscreen->cpdma_prefetch_writes_memory ?
422 0 : SI_RESOURCE_FLAG_READ_ONLY));
423 if (!sctx->b.const_uploader)
424 goto fail;
425
426 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
427 0, PIPE_USAGE_STAGING, 0);
428 if (!sctx->cached_gtt_allocator)
429 goto fail;
430
431 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
432 if (!sctx->ctx)
433 goto fail;
434
435 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
436 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
437 (void*)si_flush_dma_cs,
438 sctx);
439 }
440
441 si_init_buffer_functions(sctx);
442 si_init_clear_functions(sctx);
443 si_init_blit_functions(sctx);
444 si_init_compute_functions(sctx);
445 si_init_cp_dma_functions(sctx);
446 si_init_debug_functions(sctx);
447 si_init_msaa_functions(sctx);
448 si_init_streamout_functions(sctx);
449
450 if (sscreen->info.has_hw_decode) {
451 sctx->b.create_video_codec = si_uvd_create_decoder;
452 sctx->b.create_video_buffer = si_video_buffer_create;
453 } else {
454 sctx->b.create_video_codec = vl_create_decoder;
455 sctx->b.create_video_buffer = vl_video_buffer_create;
456 }
457
458 sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
459 (void*)si_flush_gfx_cs, sctx);
460
461 /* Border colors. */
462 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
463 sizeof(*sctx->border_color_table));
464 if (!sctx->border_color_table)
465 goto fail;
466
467 sctx->border_color_buffer = r600_resource(
468 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
469 SI_MAX_BORDER_COLORS *
470 sizeof(*sctx->border_color_table)));
471 if (!sctx->border_color_buffer)
472 goto fail;
473
474 sctx->border_color_map =
475 ws->buffer_map(sctx->border_color_buffer->buf,
476 NULL, PIPE_TRANSFER_WRITE);
477 if (!sctx->border_color_map)
478 goto fail;
479
480 si_init_all_descriptors(sctx);
481 si_init_fence_functions(sctx);
482 si_init_state_functions(sctx);
483 si_init_shader_functions(sctx);
484 si_init_viewport_functions(sctx);
485 si_init_ia_multi_vgt_param_table(sctx);
486
487 if (sctx->chip_class >= CIK)
488 cik_init_sdma_functions(sctx);
489 else
490 si_init_dma_functions(sctx);
491
492 if (sscreen->debug_flags & DBG(FORCE_DMA))
493 sctx->b.resource_copy_region = sctx->dma_copy;
494
495 sctx->blitter = util_blitter_create(&sctx->b);
496 if (sctx->blitter == NULL)
497 goto fail;
498 sctx->blitter->draw_rectangle = si_draw_rectangle;
499 sctx->blitter->skip_viewport_restore = true;
500
501 sctx->sample_mask = 0xffff;
502
503 if (sctx->chip_class >= GFX9) {
504 sctx->wait_mem_scratch = r600_resource(
505 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
506 if (!sctx->wait_mem_scratch)
507 goto fail;
508
509 /* Initialize the memory. */
510 struct radeon_cmdbuf *cs = sctx->gfx_cs;
511 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
512 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
513 S_370_WR_CONFIRM(1) |
514 S_370_ENGINE_SEL(V_370_ME));
515 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
516 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
517 radeon_emit(cs, sctx->wait_mem_number);
518 radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch,
519 RADEON_USAGE_WRITE, RADEON_PRIO_FENCE);
520 }
521
522 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
523 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
524 if (sctx->chip_class == CIK) {
525 sctx->null_const_buf.buffer =
526 pipe_aligned_buffer_create(screen,
527 SI_RESOURCE_FLAG_32BIT,
528 PIPE_USAGE_DEFAULT, 16,
529 sctx->screen->info.tcc_cache_line_size);
530 if (!sctx->null_const_buf.buffer)
531 goto fail;
532 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
533
534 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
535 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
536 sctx->b.set_constant_buffer(&sctx->b, shader, i,
537 &sctx->null_const_buf);
538 }
539 }
540
541 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
542 &sctx->null_const_buf);
543 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
544 &sctx->null_const_buf);
545 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
546 &sctx->null_const_buf);
547 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
548 &sctx->null_const_buf);
549 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
550 &sctx->null_const_buf);
551
552 /* Clear the NULL constant buffer, because loads should return zeros. */
553 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
554 sctx->null_const_buf.buffer->width0, 0,
555 SI_COHERENCY_SHADER);
556 }
557
558 uint64_t max_threads_per_block;
559 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
560 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
561 &max_threads_per_block);
562
563 /* The maximum number of scratch waves. Scratch space isn't divided
564 * evenly between CUs. The number is only a function of the number of CUs.
565 * We can decrease the constant to decrease the scratch buffer size.
566 *
567 * sctx->scratch_waves must be >= the maximum posible size of
568 * 1 threadgroup, so that the hw doesn't hang from being unable
569 * to start any.
570 *
571 * The recommended value is 4 per CU at most. Higher numbers don't
572 * bring much benefit, but they still occupy chip resources (think
573 * async compute). I've seen ~2% performance difference between 4 and 32.
574 */
575 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
576 max_threads_per_block / 64);
577
578 si_init_compiler(sscreen, &sctx->compiler);
579
580 /* Bindless handles. */
581 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
582 _mesa_key_pointer_equal);
583 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
584 _mesa_key_pointer_equal);
585
586 util_dynarray_init(&sctx->resident_tex_handles, NULL);
587 util_dynarray_init(&sctx->resident_img_handles, NULL);
588 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
589 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
590 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
591
592 /* this must be last */
593 si_begin_new_gfx_cs(sctx);
594 return &sctx->b;
595 fail:
596 fprintf(stderr, "radeonsi: Failed to create a context.\n");
597 si_destroy_context(&sctx->b);
598 return NULL;
599 }
600
601 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
602 void *priv, unsigned flags)
603 {
604 struct si_screen *sscreen = (struct si_screen *)screen;
605 struct pipe_context *ctx;
606
607 if (sscreen->debug_flags & DBG(CHECK_VM))
608 flags |= PIPE_CONTEXT_DEBUG;
609
610 ctx = si_create_context(screen, flags);
611
612 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
613 return ctx;
614
615 /* Clover (compute-only) is unsupported. */
616 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
617 return ctx;
618
619 /* When shaders are logged to stderr, asynchronous compilation is
620 * disabled too. */
621 if (sscreen->debug_flags & DBG_ALL_SHADERS)
622 return ctx;
623
624 /* Use asynchronous flushes only on amdgpu, since the radeon
625 * implementation for fence_server_sync is incomplete. */
626 return threaded_context_create(ctx, &sscreen->pool_transfers,
627 si_replace_buffer_storage,
628 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
629 &((struct si_context*)ctx)->tc);
630 }
631
632 /*
633 * pipe_screen
634 */
635 static void si_destroy_screen(struct pipe_screen* pscreen)
636 {
637 struct si_screen *sscreen = (struct si_screen *)pscreen;
638 struct si_shader_part *parts[] = {
639 sscreen->vs_prologs,
640 sscreen->tcs_epilogs,
641 sscreen->gs_prologs,
642 sscreen->ps_prologs,
643 sscreen->ps_epilogs
644 };
645 unsigned i;
646
647 if (!sscreen->ws->unref(sscreen->ws))
648 return;
649
650 util_queue_destroy(&sscreen->shader_compiler_queue);
651 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
652
653 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
654 si_destroy_compiler(&sscreen->compiler[i]);
655
656 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
657 si_destroy_compiler(&sscreen->compiler_lowp[i]);
658
659 /* Free shader parts. */
660 for (i = 0; i < ARRAY_SIZE(parts); i++) {
661 while (parts[i]) {
662 struct si_shader_part *part = parts[i];
663
664 parts[i] = part->next;
665 ac_shader_binary_clean(&part->binary);
666 FREE(part);
667 }
668 }
669 mtx_destroy(&sscreen->shader_parts_mutex);
670 si_destroy_shader_cache(sscreen);
671
672 si_perfcounters_destroy(sscreen);
673 si_gpu_load_kill_thread(sscreen);
674
675 mtx_destroy(&sscreen->gpu_load_mutex);
676 mtx_destroy(&sscreen->aux_context_lock);
677 sscreen->aux_context->destroy(sscreen->aux_context);
678
679 slab_destroy_parent(&sscreen->pool_transfers);
680
681 disk_cache_destroy(sscreen->disk_shader_cache);
682 sscreen->ws->destroy(sscreen->ws);
683 FREE(sscreen);
684 }
685
686 static void si_init_gs_info(struct si_screen *sscreen)
687 {
688 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
689 sscreen->info.family);
690 }
691
692 static void si_handle_env_var_force_family(struct si_screen *sscreen)
693 {
694 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
695 unsigned i;
696
697 if (!family)
698 return;
699
700 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
701 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
702 /* Override family and chip_class. */
703 sscreen->info.family = i;
704
705 if (i >= CHIP_VEGA10)
706 sscreen->info.chip_class = GFX9;
707 else if (i >= CHIP_TONGA)
708 sscreen->info.chip_class = VI;
709 else if (i >= CHIP_BONAIRE)
710 sscreen->info.chip_class = CIK;
711 else
712 sscreen->info.chip_class = SI;
713
714 /* Don't submit any IBs. */
715 setenv("RADEON_NOOP", "1", 1);
716 return;
717 }
718 }
719
720 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
721 exit(1);
722 }
723
724 static void si_test_vmfault(struct si_screen *sscreen)
725 {
726 struct pipe_context *ctx = sscreen->aux_context;
727 struct si_context *sctx = (struct si_context *)ctx;
728 struct pipe_resource *buf =
729 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
730
731 if (!buf) {
732 puts("Buffer allocation failed.");
733 exit(1);
734 }
735
736 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
737
738 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
739 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
740 ctx->flush(ctx, NULL, 0);
741 puts("VM fault test: CP - done.");
742 }
743 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
744 sctx->dma_clear_buffer(sctx, buf, 0, 4, 0);
745 ctx->flush(ctx, NULL, 0);
746 puts("VM fault test: SDMA - done.");
747 }
748 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
749 util_test_constant_buffer(ctx, buf);
750 puts("VM fault test: Shader - done.");
751 }
752 exit(0);
753 }
754
755 static void si_disk_cache_create(struct si_screen *sscreen)
756 {
757 /* Don't use the cache if shader dumping is enabled. */
758 if (sscreen->debug_flags & DBG_ALL_SHADERS)
759 return;
760
761 uint32_t mesa_timestamp;
762 if (disk_cache_get_function_timestamp(si_disk_cache_create,
763 &mesa_timestamp)) {
764 char *timestamp_str;
765 int res = -1;
766 uint32_t llvm_timestamp;
767
768 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
769 &llvm_timestamp)) {
770 res = asprintf(&timestamp_str, "%u_%u",
771 mesa_timestamp, llvm_timestamp);
772 }
773
774 if (res != -1) {
775 /* These flags affect shader compilation. */
776 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
777 DBG(SI_SCHED) | \
778 DBG(UNSAFE_MATH) | \
779 DBG(NIR))
780 uint64_t shader_debug_flags = sscreen->debug_flags &
781 ALL_FLAGS;
782
783 /* Add the high bits of 32-bit addresses, which affects
784 * how 32-bit addresses are expanded to 64 bits.
785 */
786 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
787 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
788
789 sscreen->disk_shader_cache =
790 disk_cache_create(si_get_family_name(sscreen),
791 timestamp_str,
792 shader_debug_flags);
793 free(timestamp_str);
794 }
795 }
796 }
797
798 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
799 const struct pipe_screen_config *config)
800 {
801 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
802 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
803
804 if (!sscreen) {
805 return NULL;
806 }
807
808 sscreen->ws = ws;
809 ws->query_info(ws, &sscreen->info);
810
811 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
812 debug_options, 0);
813
814 /* Set functions first. */
815 sscreen->b.context_create = si_pipe_create_context;
816 sscreen->b.destroy = si_destroy_screen;
817
818 si_init_screen_get_functions(sscreen);
819 si_init_screen_buffer_functions(sscreen);
820 si_init_screen_fence_functions(sscreen);
821 si_init_screen_state_functions(sscreen);
822 si_init_screen_texture_functions(sscreen);
823 si_init_screen_query_functions(sscreen);
824
825 /* Set these flags in debug_flags early, so that the shader cache takes
826 * them into account.
827 */
828 if (driQueryOptionb(config->options,
829 "glsl_correct_derivatives_after_discard"))
830 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
831 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
832 sscreen->debug_flags |= DBG(SI_SCHED);
833
834
835 if (sscreen->debug_flags & DBG(INFO))
836 ac_print_gpu_info(&sscreen->info);
837
838 slab_create_parent(&sscreen->pool_transfers,
839 sizeof(struct si_transfer), 64);
840
841 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
842 if (sscreen->force_aniso >= 0) {
843 printf("radeonsi: Forcing anisotropy filter to %ix\n",
844 /* round down to a power of two */
845 1 << util_logbase2(sscreen->force_aniso));
846 }
847
848 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
849 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
850
851 si_init_gs_info(sscreen);
852 if (!si_init_shader_cache(sscreen)) {
853 FREE(sscreen);
854 return NULL;
855 }
856
857 si_disk_cache_create(sscreen);
858
859 /* Determine the number of shader compiler threads. */
860 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
861
862 if (hw_threads >= 12) {
863 num_comp_hi_threads = hw_threads * 3 / 4;
864 num_comp_lo_threads = hw_threads / 3;
865 } else if (hw_threads >= 6) {
866 num_comp_hi_threads = hw_threads - 2;
867 num_comp_lo_threads = hw_threads / 2;
868 } else if (hw_threads >= 2) {
869 num_comp_hi_threads = hw_threads - 1;
870 num_comp_lo_threads = hw_threads / 2;
871 } else {
872 num_comp_hi_threads = 1;
873 num_comp_lo_threads = 1;
874 }
875
876 num_comp_hi_threads = MIN2(num_comp_hi_threads,
877 ARRAY_SIZE(sscreen->compiler));
878 num_comp_lo_threads = MIN2(num_comp_lo_threads,
879 ARRAY_SIZE(sscreen->compiler_lowp));
880
881 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
882 64, num_comp_hi_threads,
883 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
884 si_destroy_shader_cache(sscreen);
885 FREE(sscreen);
886 return NULL;
887 }
888
889 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
890 "si_shader_low",
891 64, num_comp_lo_threads,
892 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
893 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
894 si_destroy_shader_cache(sscreen);
895 FREE(sscreen);
896 return NULL;
897 }
898
899 si_handle_env_var_force_family(sscreen);
900
901 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
902 si_init_perfcounters(sscreen);
903
904 /* Determine tessellation ring info. */
905 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
906 sscreen->info.family != CHIP_CARRIZO &&
907 sscreen->info.family != CHIP_STONEY;
908 /* This must be one less than the maximum number due to a hw limitation.
909 * Various hardware bugs in SI, CIK, and GFX9 need this.
910 */
911 unsigned max_offchip_buffers_per_se;
912
913 /* Only certain chips can use the maximum value. */
914 if (sscreen->info.family == CHIP_VEGA12)
915 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
916 else
917 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
918
919 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
920 sscreen->info.max_se;
921 unsigned offchip_granularity;
922
923 /* Hawaii has a bug with offchip buffers > 256 that can be worked
924 * around by setting 4K granularity.
925 */
926 if (sscreen->info.family == CHIP_HAWAII) {
927 sscreen->tess_offchip_block_dw_size = 4096;
928 offchip_granularity = V_03093C_X_4K_DWORDS;
929 } else {
930 sscreen->tess_offchip_block_dw_size = 8192;
931 offchip_granularity = V_03093C_X_8K_DWORDS;
932 }
933
934 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
935 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
936 sscreen->tess_offchip_ring_size = max_offchip_buffers *
937 sscreen->tess_offchip_block_dw_size * 4;
938
939 if (sscreen->info.chip_class >= CIK) {
940 if (sscreen->info.chip_class >= VI)
941 --max_offchip_buffers;
942 sscreen->vgt_hs_offchip_param =
943 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
944 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
945 } else {
946 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
947 sscreen->vgt_hs_offchip_param =
948 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
949 }
950
951 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
952 * on SI. */
953 sscreen->has_clear_state = sscreen->info.chip_class >= CIK;
954
955 sscreen->has_distributed_tess =
956 sscreen->info.chip_class >= VI &&
957 sscreen->info.max_se >= 2;
958
959 sscreen->has_draw_indirect_multi =
960 (sscreen->info.family >= CHIP_POLARIS10) ||
961 (sscreen->info.chip_class == VI &&
962 sscreen->info.pfp_fw_version >= 121 &&
963 sscreen->info.me_fw_version >= 87) ||
964 (sscreen->info.chip_class == CIK &&
965 sscreen->info.pfp_fw_version >= 211 &&
966 sscreen->info.me_fw_version >= 173) ||
967 (sscreen->info.chip_class == SI &&
968 sscreen->info.pfp_fw_version >= 79 &&
969 sscreen->info.me_fw_version >= 142);
970
971 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
972 sscreen->info.max_se >= 2 &&
973 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
974 sscreen->assume_no_z_fights =
975 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
976 sscreen->commutative_blend_add =
977 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
978 sscreen->clear_db_cache_before_clear =
979 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
980 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
981 sscreen->info.family <= CHIP_POLARIS12) ||
982 sscreen->info.family == CHIP_VEGA10 ||
983 sscreen->info.family == CHIP_RAVEN;
984 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
985 sscreen->info.family == CHIP_RAVEN;
986
987 if (sscreen->debug_flags & DBG(DPBB)) {
988 sscreen->dpbb_allowed = true;
989 } else {
990 /* Only enable primitive binning on Raven by default. */
991 /* TODO: Investigate if binning is profitable on Vega12. */
992 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
993 !(sscreen->debug_flags & DBG(NO_DPBB));
994 }
995
996 if (sscreen->debug_flags & DBG(DFSM)) {
997 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
998 } else {
999 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1000 !(sscreen->debug_flags & DBG(NO_DFSM));
1001 }
1002
1003 /* While it would be nice not to have this flag, we are constrained
1004 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1005 * on GFX9.
1006 */
1007 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1008
1009 /* Some chips have RB+ registers, but don't support RB+. Those must
1010 * always disable it.
1011 */
1012 if (sscreen->info.family == CHIP_STONEY ||
1013 sscreen->info.chip_class >= GFX9) {
1014 sscreen->has_rbplus = true;
1015
1016 sscreen->rbplus_allowed =
1017 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1018 (sscreen->info.family == CHIP_STONEY ||
1019 sscreen->info.family == CHIP_VEGA12 ||
1020 sscreen->info.family == CHIP_RAVEN);
1021 }
1022
1023 sscreen->dcc_msaa_allowed =
1024 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1025
1026 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1027
1028 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1029 sscreen->use_monolithic_shaders =
1030 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1031
1032 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1033 SI_CONTEXT_INV_VMEM_L1;
1034 if (sscreen->info.chip_class <= VI) {
1035 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1036 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1037 }
1038
1039 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1040 sscreen->debug_flags |= DBG_ALL_SHADERS;
1041
1042 /* Syntax:
1043 * EQAA=s,z,c
1044 * Example:
1045 * EQAA=8,4,2
1046
1047 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1048 * Constraints:
1049 * s >= z >= c (ignoring this only wastes memory)
1050 * s = [2..16]
1051 * z = [2..8]
1052 * c = [2..8]
1053 *
1054 * Only MSAA color and depth buffers are overriden.
1055 */
1056 if (sscreen->info.has_eqaa_surface_allocator) {
1057 const char *eqaa = debug_get_option("EQAA", NULL);
1058 unsigned s,z,f;
1059
1060 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1061 sscreen->eqaa_force_coverage_samples = s;
1062 sscreen->eqaa_force_z_samples = z;
1063 sscreen->eqaa_force_color_samples = f;
1064 }
1065 }
1066
1067 for (i = 0; i < num_comp_hi_threads; i++)
1068 si_init_compiler(sscreen, &sscreen->compiler[i]);
1069 for (i = 0; i < num_comp_lo_threads; i++)
1070 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1071
1072 /* Create the auxiliary context. This must be done last. */
1073 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1074
1075 if (sscreen->debug_flags & DBG(TEST_DMA))
1076 si_test_dma(sscreen);
1077
1078 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1079 DBG(TEST_VMFAULT_SDMA) |
1080 DBG(TEST_VMFAULT_SHADER)))
1081 si_test_vmfault(sscreen);
1082
1083 return &sscreen->b;
1084 }