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1e7c9916a8f39600577b74b6f4bf599ed71c0171
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "sid.h"
30
31 #include "radeon/radeon_uvd.h"
32 #include "gallivm/lp_bld_misc.h"
33 #include "util/disk_cache.h"
34 #include "util/hash_table.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include <llvm-c/Transforms/IPO.h>
45 #include <llvm-c/Transforms/Scalar.h>
46 #if HAVE_LLVM >= 0x0700
47 #include <llvm-c/Transforms/Utils.h>
48 #endif
49
50 static const struct debug_named_value debug_options[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS), "Print vertex shaders" },
53 { "ps", DBG(PS), "Print pixel shaders" },
54 { "gs", DBG(GS), "Print geometry shaders" },
55 { "tcs", DBG(TCS), "Print tessellation control shaders" },
56 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS), "Print compute shaders" },
58 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
59 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
60 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
62
63 /* Shader compiler options the shader cache should be aware of: */
64 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
65 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
66
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
69 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
70 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
71 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
72
73 /* Information logging options: */
74 { "info", DBG(INFO), "Print driver information" },
75 { "tex", DBG(TEX), "Print texture info" },
76 { "compute", DBG(COMPUTE), "Print compute info" },
77 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
78
79 /* Driver options: */
80 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
81 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
82 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
83 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
84 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
85
86 /* 3D engine options: */
87 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
88 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
89 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
90 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
91 { "dpbb", DBG(DPBB), "Enable DPBB." },
92 { "dfsm", DBG(DFSM), "Enable DFSM." },
93 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
94 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
95 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
96 { "notiling", DBG(NO_TILING), "Disable tiling" },
97 { "nodcc", DBG(NO_DCC), "Disable DCC." },
98 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
99 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
100 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
101 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
102
103 /* Tests: */
104 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
105 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
106 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
107 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
108
109 DEBUG_NAMED_VALUE_END /* must be last */
110 };
111
112 static void si_init_compiler(struct si_screen *sscreen,
113 struct si_compiler *compiler)
114 {
115 enum ac_target_machine_options tm_options =
116 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
117 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
118 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
119 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
120
121 compiler->tm = ac_create_target_machine(sscreen->info.family,
122 tm_options, &compiler->triple);
123 if (!compiler->tm)
124 return;
125
126 compiler->target_library_info =
127 gallivm_create_target_library_info(compiler->triple);
128 if (!compiler->target_library_info)
129 return;
130
131 compiler->passmgr = LLVMCreatePassManager();
132 if (!compiler->passmgr)
133 return;
134
135 LLVMAddTargetLibraryInfo(compiler->target_library_info,
136 compiler->passmgr);
137
138 /* Add LLVM passes into the pass manager. */
139 if (sscreen->debug_flags & DBG(CHECK_IR))
140 LLVMAddVerifierPass(compiler->passmgr);
141
142 LLVMAddAlwaysInlinerPass(compiler->passmgr);
143 /* This pass should eliminate all the load and store instructions. */
144 LLVMAddPromoteMemoryToRegisterPass(compiler->passmgr);
145 LLVMAddScalarReplAggregatesPass(compiler->passmgr);
146 LLVMAddLICMPass(compiler->passmgr);
147 LLVMAddAggressiveDCEPass(compiler->passmgr);
148 LLVMAddCFGSimplificationPass(compiler->passmgr);
149 /* This is recommended by the instruction combining pass. */
150 LLVMAddEarlyCSEMemSSAPass(compiler->passmgr);
151 LLVMAddInstructionCombiningPass(compiler->passmgr);
152
153 /* Get the data layout. */
154 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(compiler->tm);
155 if (!data_layout)
156 return;
157 compiler->data_layout = LLVMCopyStringRepOfTargetData(data_layout);
158 LLVMDisposeTargetData(data_layout);
159 }
160
161 static void si_destroy_compiler(struct si_compiler *compiler)
162 {
163 if (compiler->data_layout)
164 LLVMDisposeMessage((char*)compiler->data_layout);
165 if (compiler->passmgr)
166 LLVMDisposePassManager(compiler->passmgr);
167 #if HAVE_LLVM >= 0x0700
168 /* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
169 if (compiler->target_library_info)
170 gallivm_dispose_target_library_info(compiler->target_library_info);
171 #endif
172 if (compiler->tm)
173 LLVMDisposeTargetMachine(compiler->tm);
174 }
175
176 /*
177 * pipe_context
178 */
179 static void si_destroy_context(struct pipe_context *context)
180 {
181 struct si_context *sctx = (struct si_context *)context;
182 int i;
183
184 /* Unreference the framebuffer normally to disable related logic
185 * properly.
186 */
187 struct pipe_framebuffer_state fb = {};
188 if (context->set_framebuffer_state)
189 context->set_framebuffer_state(context, &fb);
190
191 si_release_all_descriptors(sctx);
192
193 pipe_resource_reference(&sctx->esgs_ring, NULL);
194 pipe_resource_reference(&sctx->gsvs_ring, NULL);
195 pipe_resource_reference(&sctx->tess_rings, NULL);
196 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
197 r600_resource_reference(&sctx->border_color_buffer, NULL);
198 free(sctx->border_color_table);
199 r600_resource_reference(&sctx->scratch_buffer, NULL);
200 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
201 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
202
203 si_pm4_free_state(sctx, sctx->init_config, ~0);
204 if (sctx->init_config_gs_rings)
205 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
206 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
207 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
208
209 if (sctx->fixed_func_tcs_shader.cso)
210 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
211 if (sctx->custom_dsa_flush)
212 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
213 if (sctx->custom_blend_resolve)
214 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
215 if (sctx->custom_blend_fmask_decompress)
216 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
217 if (sctx->custom_blend_eliminate_fastclear)
218 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
219 if (sctx->custom_blend_dcc_decompress)
220 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
221 if (sctx->vs_blit_pos)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
223 if (sctx->vs_blit_pos_layered)
224 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
225 if (sctx->vs_blit_color)
226 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
227 if (sctx->vs_blit_color_layered)
228 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
229 if (sctx->vs_blit_texcoord)
230 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
231
232 if (sctx->blitter)
233 util_blitter_destroy(sctx->blitter);
234
235 /* Release DCC stats. */
236 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
237 assert(!sctx->dcc_stats[i].query_active);
238
239 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
240 if (sctx->dcc_stats[i].ps_stats[j])
241 sctx->b.destroy_query(&sctx->b,
242 sctx->dcc_stats[i].ps_stats[j]);
243
244 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
245 }
246
247 if (sctx->query_result_shader)
248 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
249
250 if (sctx->gfx_cs)
251 sctx->ws->cs_destroy(sctx->gfx_cs);
252 if (sctx->dma_cs)
253 sctx->ws->cs_destroy(sctx->dma_cs);
254 if (sctx->ctx)
255 sctx->ws->ctx_destroy(sctx->ctx);
256
257 if (sctx->b.stream_uploader)
258 u_upload_destroy(sctx->b.stream_uploader);
259 if (sctx->b.const_uploader)
260 u_upload_destroy(sctx->b.const_uploader);
261 if (sctx->cached_gtt_allocator)
262 u_upload_destroy(sctx->cached_gtt_allocator);
263
264 slab_destroy_child(&sctx->pool_transfers);
265 slab_destroy_child(&sctx->pool_transfers_unsync);
266
267 if (sctx->allocator_zeroed_memory)
268 u_suballocator_destroy(sctx->allocator_zeroed_memory);
269
270 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
271 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
272 r600_resource_reference(&sctx->eop_bug_scratch, NULL);
273
274 si_destroy_compiler(&sctx->compiler);
275
276 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
277
278 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
279 _mesa_hash_table_destroy(sctx->img_handles, NULL);
280
281 util_dynarray_fini(&sctx->resident_tex_handles);
282 util_dynarray_fini(&sctx->resident_img_handles);
283 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
284 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
285 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
286 FREE(sctx);
287 }
288
289 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
290 {
291 struct si_context *sctx = (struct si_context *)ctx;
292
293 if (sctx->screen->info.has_gpu_reset_status_query)
294 return sctx->ws->ctx_query_reset_status(sctx->ctx);
295
296 if (sctx->screen->info.has_gpu_reset_counter_query) {
297 unsigned latest = sctx->ws->query_value(sctx->ws,
298 RADEON_GPU_RESET_COUNTER);
299
300 if (sctx->gpu_reset_counter == latest)
301 return PIPE_NO_RESET;
302
303 sctx->gpu_reset_counter = latest;
304 return PIPE_UNKNOWN_CONTEXT_RESET;
305 }
306
307 return PIPE_NO_RESET;
308 }
309
310 static void si_set_device_reset_callback(struct pipe_context *ctx,
311 const struct pipe_device_reset_callback *cb)
312 {
313 struct si_context *sctx = (struct si_context *)ctx;
314
315 if (cb)
316 sctx->device_reset_callback = *cb;
317 else
318 memset(&sctx->device_reset_callback, 0,
319 sizeof(sctx->device_reset_callback));
320 }
321
322 bool si_check_device_reset(struct si_context *sctx)
323 {
324 enum pipe_reset_status status;
325
326 if (!sctx->device_reset_callback.reset)
327 return false;
328
329 if (!sctx->b.get_device_reset_status)
330 return false;
331
332 status = sctx->b.get_device_reset_status(&sctx->b);
333 if (status == PIPE_NO_RESET)
334 return false;
335
336 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
337 return true;
338 }
339
340 /* Apitrace profiling:
341 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
342 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
343 * and remember its number.
344 * 3) In Mesa, enable queries and performance counters around that draw
345 * call and print the results.
346 * 4) glretrace --benchmark --markers ..
347 */
348 static void si_emit_string_marker(struct pipe_context *ctx,
349 const char *string, int len)
350 {
351 struct si_context *sctx = (struct si_context *)ctx;
352
353 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
354
355 if (sctx->log)
356 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
357 }
358
359 static void si_set_debug_callback(struct pipe_context *ctx,
360 const struct pipe_debug_callback *cb)
361 {
362 struct si_context *sctx = (struct si_context *)ctx;
363 struct si_screen *screen = sctx->screen;
364
365 util_queue_finish(&screen->shader_compiler_queue);
366 util_queue_finish(&screen->shader_compiler_queue_low_priority);
367
368 if (cb)
369 sctx->debug = *cb;
370 else
371 memset(&sctx->debug, 0, sizeof(sctx->debug));
372 }
373
374 static void si_set_log_context(struct pipe_context *ctx,
375 struct u_log_context *log)
376 {
377 struct si_context *sctx = (struct si_context *)ctx;
378 sctx->log = log;
379
380 if (log)
381 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
382 }
383
384 static struct pipe_context *si_create_context(struct pipe_screen *screen,
385 unsigned flags)
386 {
387 struct si_context *sctx = CALLOC_STRUCT(si_context);
388 struct si_screen* sscreen = (struct si_screen *)screen;
389 struct radeon_winsys *ws = sscreen->ws;
390 int shader, i;
391
392 if (!sctx)
393 return NULL;
394
395 if (flags & PIPE_CONTEXT_DEBUG)
396 sscreen->record_llvm_ir = true; /* racy but not critical */
397
398 sctx->b.screen = screen; /* this must be set first */
399 sctx->b.priv = NULL;
400 sctx->b.destroy = si_destroy_context;
401 sctx->b.emit_string_marker = si_emit_string_marker;
402 sctx->b.set_debug_callback = si_set_debug_callback;
403 sctx->b.set_log_context = si_set_log_context;
404 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
405 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
406
407 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
408 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
409
410 sctx->ws = sscreen->ws;
411 sctx->family = sscreen->info.family;
412 sctx->chip_class = sscreen->info.chip_class;
413
414 if (sscreen->info.has_gpu_reset_counter_query) {
415 sctx->gpu_reset_counter =
416 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
417 }
418
419 sctx->b.get_device_reset_status = si_get_reset_status;
420 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
421
422 si_init_context_texture_functions(sctx);
423 si_init_query_functions(sctx);
424
425 if (sctx->chip_class == CIK ||
426 sctx->chip_class == VI ||
427 sctx->chip_class == GFX9) {
428 sctx->eop_bug_scratch = r600_resource(
429 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
430 16 * sscreen->info.num_render_backends));
431 if (!sctx->eop_bug_scratch)
432 goto fail;
433 }
434
435 sctx->allocator_zeroed_memory =
436 u_suballocator_create(&sctx->b, sscreen->info.gart_page_size,
437 0, PIPE_USAGE_DEFAULT, 0, true);
438 if (!sctx->allocator_zeroed_memory)
439 goto fail;
440
441 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
442 0, PIPE_USAGE_STREAM,
443 SI_RESOURCE_FLAG_READ_ONLY);
444 if (!sctx->b.stream_uploader)
445 goto fail;
446
447 sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024,
448 0, PIPE_USAGE_DEFAULT,
449 SI_RESOURCE_FLAG_32BIT |
450 (sscreen->cpdma_prefetch_writes_memory ?
451 0 : SI_RESOURCE_FLAG_READ_ONLY));
452 if (!sctx->b.const_uploader)
453 goto fail;
454
455 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
456 0, PIPE_USAGE_STAGING, 0);
457 if (!sctx->cached_gtt_allocator)
458 goto fail;
459
460 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
461 if (!sctx->ctx)
462 goto fail;
463
464 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
465 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
466 (void*)si_flush_dma_cs,
467 sctx);
468 }
469
470 si_init_buffer_functions(sctx);
471 si_init_clear_functions(sctx);
472 si_init_blit_functions(sctx);
473 si_init_compute_functions(sctx);
474 si_init_cp_dma_functions(sctx);
475 si_init_debug_functions(sctx);
476 si_init_msaa_functions(sctx);
477 si_init_streamout_functions(sctx);
478
479 if (sscreen->info.has_hw_decode) {
480 sctx->b.create_video_codec = si_uvd_create_decoder;
481 sctx->b.create_video_buffer = si_video_buffer_create;
482 } else {
483 sctx->b.create_video_codec = vl_create_decoder;
484 sctx->b.create_video_buffer = vl_video_buffer_create;
485 }
486
487 sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
488 (void*)si_flush_gfx_cs, sctx);
489
490 /* Border colors. */
491 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
492 sizeof(*sctx->border_color_table));
493 if (!sctx->border_color_table)
494 goto fail;
495
496 sctx->border_color_buffer = r600_resource(
497 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
498 SI_MAX_BORDER_COLORS *
499 sizeof(*sctx->border_color_table)));
500 if (!sctx->border_color_buffer)
501 goto fail;
502
503 sctx->border_color_map =
504 ws->buffer_map(sctx->border_color_buffer->buf,
505 NULL, PIPE_TRANSFER_WRITE);
506 if (!sctx->border_color_map)
507 goto fail;
508
509 si_init_all_descriptors(sctx);
510 si_init_fence_functions(sctx);
511 si_init_state_functions(sctx);
512 si_init_shader_functions(sctx);
513 si_init_viewport_functions(sctx);
514 si_init_ia_multi_vgt_param_table(sctx);
515
516 if (sctx->chip_class >= CIK)
517 cik_init_sdma_functions(sctx);
518 else
519 si_init_dma_functions(sctx);
520
521 if (sscreen->debug_flags & DBG(FORCE_DMA))
522 sctx->b.resource_copy_region = sctx->dma_copy;
523
524 sctx->blitter = util_blitter_create(&sctx->b);
525 if (sctx->blitter == NULL)
526 goto fail;
527 sctx->blitter->draw_rectangle = si_draw_rectangle;
528 sctx->blitter->skip_viewport_restore = true;
529
530 sctx->sample_mask = 0xffff;
531
532 if (sctx->chip_class >= GFX9) {
533 sctx->wait_mem_scratch = r600_resource(
534 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
535 if (!sctx->wait_mem_scratch)
536 goto fail;
537
538 /* Initialize the memory. */
539 struct radeon_cmdbuf *cs = sctx->gfx_cs;
540 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
541 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
542 S_370_WR_CONFIRM(1) |
543 S_370_ENGINE_SEL(V_370_ME));
544 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
545 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
546 radeon_emit(cs, sctx->wait_mem_number);
547 radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch,
548 RADEON_USAGE_WRITE, RADEON_PRIO_FENCE);
549 }
550
551 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
552 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
553 if (sctx->chip_class == CIK) {
554 sctx->null_const_buf.buffer =
555 pipe_aligned_buffer_create(screen,
556 SI_RESOURCE_FLAG_32BIT,
557 PIPE_USAGE_DEFAULT, 16,
558 sctx->screen->info.tcc_cache_line_size);
559 if (!sctx->null_const_buf.buffer)
560 goto fail;
561 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
562
563 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
564 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
565 sctx->b.set_constant_buffer(&sctx->b, shader, i,
566 &sctx->null_const_buf);
567 }
568 }
569
570 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
571 &sctx->null_const_buf);
572 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
573 &sctx->null_const_buf);
574 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
575 &sctx->null_const_buf);
576 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
577 &sctx->null_const_buf);
578 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
579 &sctx->null_const_buf);
580
581 /* Clear the NULL constant buffer, because loads should return zeros. */
582 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
583 sctx->null_const_buf.buffer->width0, 0,
584 SI_COHERENCY_SHADER);
585 }
586
587 uint64_t max_threads_per_block;
588 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
589 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
590 &max_threads_per_block);
591
592 /* The maximum number of scratch waves. Scratch space isn't divided
593 * evenly between CUs. The number is only a function of the number of CUs.
594 * We can decrease the constant to decrease the scratch buffer size.
595 *
596 * sctx->scratch_waves must be >= the maximum posible size of
597 * 1 threadgroup, so that the hw doesn't hang from being unable
598 * to start any.
599 *
600 * The recommended value is 4 per CU at most. Higher numbers don't
601 * bring much benefit, but they still occupy chip resources (think
602 * async compute). I've seen ~2% performance difference between 4 and 32.
603 */
604 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
605 max_threads_per_block / 64);
606
607 si_init_compiler(sscreen, &sctx->compiler);
608
609 /* Bindless handles. */
610 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
611 _mesa_key_pointer_equal);
612 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
613 _mesa_key_pointer_equal);
614
615 util_dynarray_init(&sctx->resident_tex_handles, NULL);
616 util_dynarray_init(&sctx->resident_img_handles, NULL);
617 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
618 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
619 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
620
621 /* this must be last */
622 si_begin_new_gfx_cs(sctx);
623 return &sctx->b;
624 fail:
625 fprintf(stderr, "radeonsi: Failed to create a context.\n");
626 si_destroy_context(&sctx->b);
627 return NULL;
628 }
629
630 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
631 void *priv, unsigned flags)
632 {
633 struct si_screen *sscreen = (struct si_screen *)screen;
634 struct pipe_context *ctx;
635
636 if (sscreen->debug_flags & DBG(CHECK_VM))
637 flags |= PIPE_CONTEXT_DEBUG;
638
639 ctx = si_create_context(screen, flags);
640
641 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
642 return ctx;
643
644 /* Clover (compute-only) is unsupported. */
645 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
646 return ctx;
647
648 /* When shaders are logged to stderr, asynchronous compilation is
649 * disabled too. */
650 if (sscreen->debug_flags & DBG_ALL_SHADERS)
651 return ctx;
652
653 /* Use asynchronous flushes only on amdgpu, since the radeon
654 * implementation for fence_server_sync is incomplete. */
655 return threaded_context_create(ctx, &sscreen->pool_transfers,
656 si_replace_buffer_storage,
657 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
658 &((struct si_context*)ctx)->tc);
659 }
660
661 /*
662 * pipe_screen
663 */
664 static void si_destroy_screen(struct pipe_screen* pscreen)
665 {
666 struct si_screen *sscreen = (struct si_screen *)pscreen;
667 struct si_shader_part *parts[] = {
668 sscreen->vs_prologs,
669 sscreen->tcs_epilogs,
670 sscreen->gs_prologs,
671 sscreen->ps_prologs,
672 sscreen->ps_epilogs
673 };
674 unsigned i;
675
676 if (!sscreen->ws->unref(sscreen->ws))
677 return;
678
679 util_queue_destroy(&sscreen->shader_compiler_queue);
680 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
681
682 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
683 si_destroy_compiler(&sscreen->compiler[i]);
684
685 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
686 si_destroy_compiler(&sscreen->compiler_lowp[i]);
687
688 /* Free shader parts. */
689 for (i = 0; i < ARRAY_SIZE(parts); i++) {
690 while (parts[i]) {
691 struct si_shader_part *part = parts[i];
692
693 parts[i] = part->next;
694 ac_shader_binary_clean(&part->binary);
695 FREE(part);
696 }
697 }
698 mtx_destroy(&sscreen->shader_parts_mutex);
699 si_destroy_shader_cache(sscreen);
700
701 si_perfcounters_destroy(sscreen);
702 si_gpu_load_kill_thread(sscreen);
703
704 mtx_destroy(&sscreen->gpu_load_mutex);
705 mtx_destroy(&sscreen->aux_context_lock);
706 sscreen->aux_context->destroy(sscreen->aux_context);
707
708 slab_destroy_parent(&sscreen->pool_transfers);
709
710 disk_cache_destroy(sscreen->disk_shader_cache);
711 sscreen->ws->destroy(sscreen->ws);
712 FREE(sscreen);
713 }
714
715 static void si_init_gs_info(struct si_screen *sscreen)
716 {
717 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
718 sscreen->info.family);
719 }
720
721 static void si_handle_env_var_force_family(struct si_screen *sscreen)
722 {
723 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
724 unsigned i;
725
726 if (!family)
727 return;
728
729 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
730 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
731 /* Override family and chip_class. */
732 sscreen->info.family = i;
733
734 if (i >= CHIP_VEGA10)
735 sscreen->info.chip_class = GFX9;
736 else if (i >= CHIP_TONGA)
737 sscreen->info.chip_class = VI;
738 else if (i >= CHIP_BONAIRE)
739 sscreen->info.chip_class = CIK;
740 else
741 sscreen->info.chip_class = SI;
742
743 /* Don't submit any IBs. */
744 setenv("RADEON_NOOP", "1", 1);
745 return;
746 }
747 }
748
749 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
750 exit(1);
751 }
752
753 static void si_test_vmfault(struct si_screen *sscreen)
754 {
755 struct pipe_context *ctx = sscreen->aux_context;
756 struct si_context *sctx = (struct si_context *)ctx;
757 struct pipe_resource *buf =
758 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
759
760 if (!buf) {
761 puts("Buffer allocation failed.");
762 exit(1);
763 }
764
765 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
766
767 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
768 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
769 ctx->flush(ctx, NULL, 0);
770 puts("VM fault test: CP - done.");
771 }
772 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
773 sctx->dma_clear_buffer(sctx, buf, 0, 4, 0);
774 ctx->flush(ctx, NULL, 0);
775 puts("VM fault test: SDMA - done.");
776 }
777 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
778 util_test_constant_buffer(ctx, buf);
779 puts("VM fault test: Shader - done.");
780 }
781 exit(0);
782 }
783
784 static void si_disk_cache_create(struct si_screen *sscreen)
785 {
786 /* Don't use the cache if shader dumping is enabled. */
787 if (sscreen->debug_flags & DBG_ALL_SHADERS)
788 return;
789
790 uint32_t mesa_timestamp;
791 if (disk_cache_get_function_timestamp(si_disk_cache_create,
792 &mesa_timestamp)) {
793 char *timestamp_str;
794 int res = -1;
795 uint32_t llvm_timestamp;
796
797 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
798 &llvm_timestamp)) {
799 res = asprintf(&timestamp_str, "%u_%u",
800 mesa_timestamp, llvm_timestamp);
801 }
802
803 if (res != -1) {
804 /* These flags affect shader compilation. */
805 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
806 DBG(SI_SCHED) | \
807 DBG(UNSAFE_MATH) | \
808 DBG(NIR))
809 uint64_t shader_debug_flags = sscreen->debug_flags &
810 ALL_FLAGS;
811
812 /* Add the high bits of 32-bit addresses, which affects
813 * how 32-bit addresses are expanded to 64 bits.
814 */
815 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
816 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
817
818 sscreen->disk_shader_cache =
819 disk_cache_create(si_get_family_name(sscreen),
820 timestamp_str,
821 shader_debug_flags);
822 free(timestamp_str);
823 }
824 }
825 }
826
827 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
828 const struct pipe_screen_config *config)
829 {
830 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
831 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
832
833 if (!sscreen) {
834 return NULL;
835 }
836
837 sscreen->ws = ws;
838 ws->query_info(ws, &sscreen->info);
839
840 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
841 debug_options, 0);
842
843 /* Set functions first. */
844 sscreen->b.context_create = si_pipe_create_context;
845 sscreen->b.destroy = si_destroy_screen;
846
847 si_init_screen_get_functions(sscreen);
848 si_init_screen_buffer_functions(sscreen);
849 si_init_screen_fence_functions(sscreen);
850 si_init_screen_state_functions(sscreen);
851 si_init_screen_texture_functions(sscreen);
852 si_init_screen_query_functions(sscreen);
853
854 /* Set these flags in debug_flags early, so that the shader cache takes
855 * them into account.
856 */
857 if (driQueryOptionb(config->options,
858 "glsl_correct_derivatives_after_discard"))
859 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
860 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
861 sscreen->debug_flags |= DBG(SI_SCHED);
862
863
864 if (sscreen->debug_flags & DBG(INFO))
865 ac_print_gpu_info(&sscreen->info);
866
867 slab_create_parent(&sscreen->pool_transfers,
868 sizeof(struct r600_transfer), 64);
869
870 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
871 if (sscreen->force_aniso >= 0) {
872 printf("radeonsi: Forcing anisotropy filter to %ix\n",
873 /* round down to a power of two */
874 1 << util_logbase2(sscreen->force_aniso));
875 }
876
877 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
878 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
879
880 si_init_gs_info(sscreen);
881 if (!si_init_shader_cache(sscreen)) {
882 FREE(sscreen);
883 return NULL;
884 }
885
886 si_disk_cache_create(sscreen);
887
888 /* Determine the number of shader compiler threads. */
889 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
890
891 if (hw_threads >= 12) {
892 num_comp_hi_threads = hw_threads * 3 / 4;
893 num_comp_lo_threads = hw_threads / 3;
894 } else if (hw_threads >= 6) {
895 num_comp_hi_threads = hw_threads - 2;
896 num_comp_lo_threads = hw_threads / 2;
897 } else if (hw_threads >= 2) {
898 num_comp_hi_threads = hw_threads - 1;
899 num_comp_lo_threads = hw_threads / 2;
900 } else {
901 num_comp_hi_threads = 1;
902 num_comp_lo_threads = 1;
903 }
904
905 num_comp_hi_threads = MIN2(num_comp_hi_threads,
906 ARRAY_SIZE(sscreen->compiler));
907 num_comp_lo_threads = MIN2(num_comp_lo_threads,
908 ARRAY_SIZE(sscreen->compiler_lowp));
909
910 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
911 64, num_comp_hi_threads,
912 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
913 si_destroy_shader_cache(sscreen);
914 FREE(sscreen);
915 return NULL;
916 }
917
918 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
919 "si_shader_low",
920 64, num_comp_lo_threads,
921 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
922 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
923 si_destroy_shader_cache(sscreen);
924 FREE(sscreen);
925 return NULL;
926 }
927
928 si_handle_env_var_force_family(sscreen);
929
930 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
931 si_init_perfcounters(sscreen);
932
933 /* Determine tessellation ring info. */
934 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
935 sscreen->info.family != CHIP_CARRIZO &&
936 sscreen->info.family != CHIP_STONEY;
937 /* This must be one less than the maximum number due to a hw limitation.
938 * Various hardware bugs in SI, CIK, and GFX9 need this.
939 */
940 unsigned max_offchip_buffers_per_se;
941
942 /* Only certain chips can use the maximum value. */
943 if (sscreen->info.family == CHIP_VEGA12)
944 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
945 else
946 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
947
948 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
949 sscreen->info.max_se;
950 unsigned offchip_granularity;
951
952 /* Hawaii has a bug with offchip buffers > 256 that can be worked
953 * around by setting 4K granularity.
954 */
955 if (sscreen->info.family == CHIP_HAWAII) {
956 sscreen->tess_offchip_block_dw_size = 4096;
957 offchip_granularity = V_03093C_X_4K_DWORDS;
958 } else {
959 sscreen->tess_offchip_block_dw_size = 8192;
960 offchip_granularity = V_03093C_X_8K_DWORDS;
961 }
962
963 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
964 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
965 sscreen->tess_offchip_ring_size = max_offchip_buffers *
966 sscreen->tess_offchip_block_dw_size * 4;
967
968 if (sscreen->info.chip_class >= CIK) {
969 if (sscreen->info.chip_class >= VI)
970 --max_offchip_buffers;
971 sscreen->vgt_hs_offchip_param =
972 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
973 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
974 } else {
975 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
976 sscreen->vgt_hs_offchip_param =
977 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
978 }
979
980 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
981 * on SI. */
982 sscreen->has_clear_state = sscreen->info.chip_class >= CIK;
983
984 sscreen->has_distributed_tess =
985 sscreen->info.chip_class >= VI &&
986 sscreen->info.max_se >= 2;
987
988 sscreen->has_draw_indirect_multi =
989 (sscreen->info.family >= CHIP_POLARIS10) ||
990 (sscreen->info.chip_class == VI &&
991 sscreen->info.pfp_fw_version >= 121 &&
992 sscreen->info.me_fw_version >= 87) ||
993 (sscreen->info.chip_class == CIK &&
994 sscreen->info.pfp_fw_version >= 211 &&
995 sscreen->info.me_fw_version >= 173) ||
996 (sscreen->info.chip_class == SI &&
997 sscreen->info.pfp_fw_version >= 79 &&
998 sscreen->info.me_fw_version >= 142);
999
1000 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1001 sscreen->info.max_se >= 2 &&
1002 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1003 sscreen->assume_no_z_fights =
1004 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1005 sscreen->commutative_blend_add =
1006 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1007 sscreen->clear_db_cache_before_clear =
1008 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1009 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1010 sscreen->info.family <= CHIP_POLARIS12) ||
1011 sscreen->info.family == CHIP_VEGA10 ||
1012 sscreen->info.family == CHIP_RAVEN;
1013 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1014 sscreen->info.family == CHIP_RAVEN;
1015
1016 if (sscreen->debug_flags & DBG(DPBB)) {
1017 sscreen->dpbb_allowed = true;
1018 } else {
1019 /* Only enable primitive binning on Raven by default. */
1020 /* TODO: Investigate if binning is profitable on Vega12. */
1021 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
1022 !(sscreen->debug_flags & DBG(NO_DPBB));
1023 }
1024
1025 if (sscreen->debug_flags & DBG(DFSM)) {
1026 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1027 } else {
1028 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1029 !(sscreen->debug_flags & DBG(NO_DFSM));
1030 }
1031
1032 /* While it would be nice not to have this flag, we are constrained
1033 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1034 * on GFX9.
1035 */
1036 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1037
1038 /* Some chips have RB+ registers, but don't support RB+. Those must
1039 * always disable it.
1040 */
1041 if (sscreen->info.family == CHIP_STONEY ||
1042 sscreen->info.chip_class >= GFX9) {
1043 sscreen->has_rbplus = true;
1044
1045 sscreen->rbplus_allowed =
1046 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1047 (sscreen->info.family == CHIP_STONEY ||
1048 sscreen->info.family == CHIP_VEGA12 ||
1049 sscreen->info.family == CHIP_RAVEN);
1050 }
1051
1052 sscreen->dcc_msaa_allowed =
1053 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1054
1055 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1056
1057 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1058 sscreen->use_monolithic_shaders =
1059 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1060
1061 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1062 SI_CONTEXT_INV_VMEM_L1;
1063 if (sscreen->info.chip_class <= VI) {
1064 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1065 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1066 }
1067
1068 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1069 sscreen->debug_flags |= DBG_ALL_SHADERS;
1070
1071 /* Syntax:
1072 * EQAA=s,z,c
1073 * Example:
1074 * EQAA=8,4,2
1075
1076 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1077 * Constraints:
1078 * s >= z >= c (ignoring this only wastes memory)
1079 * s = [2..16]
1080 * z = [2..8]
1081 * c = [2..8]
1082 *
1083 * Only MSAA color and depth buffers are overriden.
1084 */
1085 if (sscreen->info.has_eqaa_surface_allocator) {
1086 const char *eqaa = debug_get_option("EQAA", NULL);
1087 unsigned s,z,f;
1088
1089 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1090 sscreen->eqaa_force_coverage_samples = s;
1091 sscreen->eqaa_force_z_samples = z;
1092 sscreen->eqaa_force_color_samples = f;
1093 }
1094 }
1095
1096 for (i = 0; i < num_comp_hi_threads; i++)
1097 si_init_compiler(sscreen, &sscreen->compiler[i]);
1098 for (i = 0; i < num_comp_lo_threads; i++)
1099 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1100
1101 /* Create the auxiliary context. This must be done last. */
1102 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1103
1104 if (sscreen->debug_flags & DBG(TEST_DMA))
1105 si_test_dma(sscreen);
1106
1107 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1108 DBG(TEST_VMFAULT_SDMA) |
1109 DBG(TEST_VMFAULT_SHADER)))
1110 si_test_vmfault(sscreen);
1111
1112 return &sscreen->b;
1113 }