src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  37               unsigned flags)
  38 {
  39         struct si_context *sctx = (struct si_context *)ctx;
  40         struct pipe_query *render_cond = NULL;
  41         boolean render_cond_cond = FALSE;
  42         unsigned render_cond_mode = 0;
  43
  44         if (fence) {
  45                 *fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
  46         }
  47
  48         /* Disable render condition. */
  49         if (sctx->b.current_render_cond) {
  50                 render_cond = sctx->b.current_render_cond;
  51                 render_cond_cond = sctx->b.current_render_cond_cond;
  52                 render_cond_mode = sctx->b.current_render_cond_mode;
  53                 ctx->render_condition(ctx, NULL, FALSE, 0);
  54         }
  55
  56         si_context_flush(sctx, flags);
  57
  58         /* Re-enable render condition. */
  59         if (render_cond) {
  60                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  61         }
  62 }
  63
  64 static void si_flush_from_st(struct pipe_context *ctx,
  65                              struct pipe_fence_handle **fence,
  66                              unsigned flags)
  67 {
  68         si_flush(ctx, fence,
  69                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  70 }
  71
  72 static void si_flush_from_winsys(void *ctx, unsigned flags)
  73 {
  74         si_flush((struct pipe_context*)ctx, NULL, flags);
  75 }
  76
  77 static void si_destroy_context(struct pipe_context *context)
  78 {
  79         struct si_context *sctx = (struct si_context *)context;
  80
  81         si_release_all_descriptors(sctx);
  82
  83         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  84         r600_resource_reference(&sctx->border_color_table, NULL);
  85
  86         if (sctx->dummy_pixel_shader) {
  87                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  88         }
  89         for (int i = 0; i < 8; i++) {
  90                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  91                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  92                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  93         }
  94         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  95         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  96         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  97         util_unreference_framebuffer_state(&sctx->framebuffer);
  98
  99         util_blitter_destroy(sctx->blitter);
 100
 101         r600_common_context_cleanup(&sctx->b);
 102         FREE(sctx);
 103 }
 104
 105 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
 106 {
 107         struct si_context *sctx = CALLOC_STRUCT(si_context);
 108         struct si_screen* sscreen = (struct si_screen *)screen;
 109         int shader, i;
 110
 111         if (sctx == NULL)
 112                 return NULL;
 113
 114         sctx->b.b.screen = screen; /* this must be set first */
 115         sctx->b.b.priv = priv;
 116         sctx->b.b.destroy = si_destroy_context;
 117         sctx->b.b.flush = si_flush_from_st;
 118         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 119
 120         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 121                 goto fail;
 122
 123         si_init_blit_functions(sctx);
 124         si_init_compute_functions(sctx);
 125
 126         if (sscreen->b.info.has_uvd) {
 127                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 128                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 129         } else {
 130                 sctx->b.b.create_video_codec = vl_create_decoder;
 131                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 132         }
 133
 134         sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
 135         sctx->b.rings.gfx.flush = si_flush_from_winsys;
 136
 137         si_init_all_descriptors(sctx);
 138
 139         /* Initialize cache_flush. */
 140         sctx->cache_flush = si_atom_cache_flush;
 141         sctx->atoms.cache_flush = &sctx->cache_flush;
 142
 143         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 144
 145         switch (sctx->b.chip_class) {
 146         case SI:
 147         case CIK:
 148                 si_init_state_functions(sctx);
 149                 si_init_config(sctx);
 150                 break;
 151         default:
 152                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 153                 goto fail;
 154         }
 155
 156         sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
 157
 158         sctx->blitter = util_blitter_create(&sctx->b.b);
 159         if (sctx->blitter == NULL)
 160                 goto fail;
 161
 162         sctx->dummy_pixel_shader =
 163                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 164                                                      TGSI_SEMANTIC_GENERIC,
 165                                                      TGSI_INTERPOLATE_CONSTANT);
 166         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 167
 168         /* these must be last */
 169         si_begin_new_cs(sctx);
 170         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 171
 172         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 173          * with a NULL buffer). We need to use a dummy buffer instead. */
 174         if (sctx->b.chip_class == CIK) {
 175                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 176                                                                  PIPE_USAGE_STATIC, 16);
 177                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 178
 179                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 180                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 181                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 182                                                               &sctx->null_const_buf);
 183                         }
 184                 }
 185
 186                 /* Clear the NULL constant buffer, because loads should return zeros. */
 187                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 188                                      sctx->null_const_buf.buffer->width0, 0);
 189         }
 190
 191         return &sctx->b.b;
 192 fail:
 193         si_destroy_context(&sctx->b.b);
 194         return NULL;
 195 }
 196
 197 /*
 198  * pipe_screen
 199  */
 200
 201 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 202 {
 203         struct si_screen *sscreen = (struct si_screen *)pscreen;
 204
 205         switch (param) {
 206         /* Supported features (boolean caps). */
 207         case PIPE_CAP_TWO_SIDED_STENCIL:
 208         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 209         case PIPE_CAP_ANISOTROPIC_FILTER:
 210         case PIPE_CAP_POINT_SPRITE:
 211         case PIPE_CAP_OCCLUSION_QUERY:
 212         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 213         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 214         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 215         case PIPE_CAP_TEXTURE_SWIZZLE:
 216         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 217         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 218         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 219         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 220         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 221         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 222         case PIPE_CAP_SM3:
 223         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 224         case PIPE_CAP_PRIMITIVE_RESTART:
 225         case PIPE_CAP_CONDITIONAL_RENDER:
 226         case PIPE_CAP_TEXTURE_BARRIER:
 227         case PIPE_CAP_INDEP_BLEND_ENABLE:
 228         case PIPE_CAP_INDEP_BLEND_FUNC:
 229         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 230         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 231         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 232         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 233         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 234         case PIPE_CAP_USER_INDEX_BUFFERS:
 235         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 236         case PIPE_CAP_START_INSTANCE:
 237         case PIPE_CAP_NPOT_TEXTURES:
 238         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 239         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 240         case PIPE_CAP_TGSI_INSTANCEID:
 241         case PIPE_CAP_COMPUTE:
 242         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 243         case PIPE_CAP_TGSI_VS_LAYER:
 244         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 245                 return 1;
 246
 247         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 248                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 249                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 250                                                sscreen->b.info.drm_minor >= 35);
 251
 252         case PIPE_CAP_TGSI_TEXCOORD:
 253                 return 0;
 254
 255         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 256                 return 64;
 257
 258         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 259                 return 256;
 260
 261         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 262                 return 140;
 263
 264         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 265                 return 1;
 266         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 267                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 268
 269         /* Unsupported features. */
 270         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 271         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 272         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 273         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 274         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 275         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 276         case PIPE_CAP_USER_VERTEX_BUFFERS:
 277         case PIPE_CAP_CUBE_MAP_ARRAY:
 278                 return 0;
 279
 280         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 281                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 282
 283         /* Stream output. */
 284         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 285                 return sscreen->b.has_streamout ? 4 : 0;
 286         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 287                 return sscreen->b.has_streamout ? 1 : 0;
 288         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 289         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 290                 return sscreen->b.has_streamout ? 32*4 : 0;
 291
 292         /* Texturing. */
 293         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 294         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 295         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 296                         return 15;
 297         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 298                 return 16384;
 299         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 300                 return 32;
 301
 302         /* Render targets. */
 303         case PIPE_CAP_MAX_RENDER_TARGETS:
 304                 return 8;
 305
 306         case PIPE_CAP_MAX_VIEWPORTS:
 307                 return 1;
 308
 309         /* Timer queries, present when the clock frequency is non zero. */
 310         case PIPE_CAP_QUERY_TIMESTAMP:
 311         case PIPE_CAP_QUERY_TIME_ELAPSED:
 312                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 313
 314         case PIPE_CAP_MIN_TEXEL_OFFSET:
 315                 return -8;
 316
 317         case PIPE_CAP_MAX_TEXEL_OFFSET:
 318                 return 7;
 319         case PIPE_CAP_ENDIANNESS:
 320                 return PIPE_ENDIAN_LITTLE;
 321         }
 322         return 0;
 323 }
 324
 325 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 326 {
 327         switch(shader)
 328         {
 329         case PIPE_SHADER_FRAGMENT:
 330         case PIPE_SHADER_VERTEX:
 331                 break;
 332         case PIPE_SHADER_GEOMETRY:
 333                 /* TODO: support and enable geometry programs */
 334                 return 0;
 335         case PIPE_SHADER_COMPUTE:
 336                 switch (param) {
 337                 case PIPE_SHADER_CAP_PREFERRED_IR:
 338                         return PIPE_SHADER_IR_LLVM;
 339                 default:
 340                         return 0;
 341                 }
 342         default:
 343                 /* TODO: support tessellation */
 344                 return 0;
 345         }
 346
 347         switch (param) {
 348         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 349         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 350         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 351         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 352                 return 16384;
 353         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 354                 return 32;
 355         case PIPE_SHADER_CAP_MAX_INPUTS:
 356                 return 32;
 357         case PIPE_SHADER_CAP_MAX_TEMPS:
 358                 return 256; /* Max native temporaries. */
 359         case PIPE_SHADER_CAP_MAX_ADDRS:
 360                 /* FIXME Isn't this equal to TEMPS? */
 361                 return 1; /* Max native address registers */
 362         case PIPE_SHADER_CAP_MAX_CONSTS:
 363                 return 4096; /* actually only memory limits this */
 364         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 365                 return NUM_PIPE_CONST_BUFFERS;
 366         case PIPE_SHADER_CAP_MAX_PREDS:
 367                 return 0; /* FIXME */
 368         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 369                 return 1;
 370         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 371                 return 0;
 372         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 373         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 374         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 375         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 376                 return 1;
 377         case PIPE_SHADER_CAP_INTEGERS:
 378                 return 1;
 379         case PIPE_SHADER_CAP_SUBROUTINES:
 380                 return 0;
 381         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 382         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 383                 return 16;
 384         case PIPE_SHADER_CAP_PREFERRED_IR:
 385                 return PIPE_SHADER_IR_TGSI;
 386         }
 387         return 0;
 388 }
 389
 390 static void si_destroy_screen(struct pipe_screen* pscreen)
 391 {
 392         struct si_screen *sscreen = (struct si_screen *)pscreen;
 393
 394         if (sscreen == NULL)
 395                 return;
 396
 397         if (!radeon_winsys_unref(sscreen->b.ws))
 398                 return;
 399
 400         r600_destroy_common_screen(&sscreen->b);
 401 }
 402
 403 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 404 {
 405         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 406         if (sscreen == NULL) {
 407                 return NULL;
 408         }
 409
 410         /* Set functions first. */
 411         sscreen->b.b.context_create = si_create_context;
 412         sscreen->b.b.destroy = si_destroy_screen;
 413         sscreen->b.b.get_param = si_get_param;
 414         sscreen->b.b.get_shader_param = si_get_shader_param;
 415         sscreen->b.b.is_format_supported = si_is_format_supported;
 416
 417         if (!r600_common_screen_init(&sscreen->b, ws)) {
 418                 FREE(sscreen);
 419                 return NULL;
 420         }
 421
 422         sscreen->b.has_cp_dma = true;
 423         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 424
 425         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 426                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 427
 428         /* Create the auxiliary context. This must be done last. */
 429         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 430
 431         return &sscreen->b.b;
 432 }