src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_table, NULL);
  48         r600_resource_reference(&sctx->scratch_buffer, NULL);
  49         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  50
  51         si_pm4_free_state(sctx, sctx->init_config, ~0);
  52         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  53         si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
  54         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  55                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  56
  57         if (sctx->pstipple_sampler_state)
  58                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  59         if (sctx->dummy_pixel_shader)
  60                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  61         if (sctx->fixed_func_tcs_shader)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  72
  73         if (sctx->blitter)
  74                 util_blitter_destroy(sctx->blitter);
  75
  76         si_pm4_cleanup(sctx);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80 #if HAVE_LLVM >= 0x0306
  81         LLVMDisposeTargetMachine(sctx->tm);
  82 #endif
  83
  84         FREE(sctx);
  85 }
  86
  87 static enum pipe_reset_status
  88 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  89 {
  90         struct si_context *sctx = (struct si_context *)ctx;
  91
  92         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  93 }
  94
  95 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  96 {
  97         struct si_context *sctx = CALLOC_STRUCT(si_context);
  98         struct si_screen* sscreen = (struct si_screen *)screen;
  99         struct radeon_winsys *ws = sscreen->b.ws;
 100         LLVMTargetRef r600_target;
 101 #if HAVE_LLVM >= 0x0306
 102         const char *triple = "amdgcn--";
 103 #endif
 104         int shader, i;
 105
 106         if (sctx == NULL)
 107                 return NULL;
 108
 109         sctx->b.b.screen = screen; /* this must be set first */
 110         sctx->b.b.priv = priv;
 111         sctx->b.b.destroy = si_destroy_context;
 112         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 113         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 114
 115         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 116                 goto fail;
 117
 118         if (sscreen->b.info.drm_major == 3)
 119                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 120
 121         si_init_blit_functions(sctx);
 122         si_init_compute_functions(sctx);
 123         si_init_cp_dma_functions(sctx);
 124
 125         if (sscreen->b.info.has_uvd) {
 126                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 127                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 128         } else {
 129                 sctx->b.b.create_video_codec = vl_create_decoder;
 130                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 131         }
 132
 133         sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 134                                              sctx, sscreen->b.trace_bo ?
 135                                                 sscreen->b.trace_bo->cs_buf : NULL);
 136         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 137
 138         si_init_all_descriptors(sctx);
 139
 140         /* Initialize cache_flush. */
 141         sctx->cache_flush = si_atom_cache_flush;
 142         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 143
 144         sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
 145         sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
 146
 147         sctx->msaa_config = si_atom_msaa_config;
 148         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 149
 150         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 151         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 152
 153         si_init_state_functions(sctx);
 154         si_init_shader_functions(sctx);
 155
 156         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 157                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 158
 159         sctx->blitter = util_blitter_create(&sctx->b.b);
 160         if (sctx->blitter == NULL)
 161                 goto fail;
 162         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 163
 164         /* these must be last */
 165         si_begin_new_cs(sctx);
 166         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 167
 168         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 169          * with a NULL buffer). We need to use a dummy buffer instead. */
 170         if (sctx->b.chip_class == CIK) {
 171                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 172                                                                  PIPE_USAGE_DEFAULT, 16);
 173                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 174
 175                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 176                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 177                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 178                                                               &sctx->null_const_buf);
 179                         }
 180                 }
 181
 182                 /* Clear the NULL constant buffer, because loads should return zeros. */
 183                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 184                                      sctx->null_const_buf.buffer->width0, 0, false);
 185         }
 186
 187         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 188          * this for non-cs shaders.  Using the wrong value here can result in
 189          * GPU lockups, but the maximum value seems to always work.
 190          */
 191         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 192
 193 #if HAVE_LLVM >= 0x0306
 194         /* Initialize LLVM TargetMachine */
 195         r600_target = radeon_llvm_get_r600_target(triple);
 196         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 197                                            r600_get_llvm_processor_name(sscreen->b.family),
 198                                            sctx->b.chip_class >= VI ?
 199                                                    "+DumpCode" :
 200                                                    "+DumpCode,+vgpr-spilling",
 201                                            LLVMCodeGenLevelDefault,
 202                                            LLVMRelocDefault,
 203                                            LLVMCodeModelDefault);
 204 #endif
 205
 206         return &sctx->b.b;
 207 fail:
 208         si_destroy_context(&sctx->b.b);
 209         return NULL;
 210 }
 211
 212 /*
 213  * pipe_screen
 214  */
 215
 216 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 217 {
 218         struct si_screen *sscreen = (struct si_screen *)pscreen;
 219
 220         switch (param) {
 221         /* Supported features (boolean caps). */
 222         case PIPE_CAP_TWO_SIDED_STENCIL:
 223         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 224         case PIPE_CAP_ANISOTROPIC_FILTER:
 225         case PIPE_CAP_POINT_SPRITE:
 226         case PIPE_CAP_OCCLUSION_QUERY:
 227         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 228         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 229         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 230         case PIPE_CAP_TEXTURE_SWIZZLE:
 231         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 232         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 233         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 234         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 235         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 236         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 237         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 238         case PIPE_CAP_SM3:
 239         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 240         case PIPE_CAP_PRIMITIVE_RESTART:
 241         case PIPE_CAP_CONDITIONAL_RENDER:
 242         case PIPE_CAP_TEXTURE_BARRIER:
 243         case PIPE_CAP_INDEP_BLEND_ENABLE:
 244         case PIPE_CAP_INDEP_BLEND_FUNC:
 245         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 246         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 247         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 248         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 249         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 250         case PIPE_CAP_USER_INDEX_BUFFERS:
 251         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 252         case PIPE_CAP_START_INSTANCE:
 253         case PIPE_CAP_NPOT_TEXTURES:
 254         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 255         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 256         case PIPE_CAP_TGSI_INSTANCEID:
 257         case PIPE_CAP_COMPUTE:
 258         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 259         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 260         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 261         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 262         case PIPE_CAP_CUBE_MAP_ARRAY:
 263         case PIPE_CAP_SAMPLE_SHADING:
 264         case PIPE_CAP_DRAW_INDIRECT:
 265         case PIPE_CAP_CLIP_HALFZ:
 266         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 267         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 268         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 269         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 270         case PIPE_CAP_TGSI_TEXCOORD:
 271         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 272         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 273         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 274         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 275         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 276                 return 1;
 277
 278         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 279                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 280
 281         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 282                 return (sscreen->b.info.drm_major == 2 &&
 283                         sscreen->b.info.drm_minor >= 43) ||
 284                        sscreen->b.info.drm_major == 3;
 285
 286         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 287                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 288                 return sscreen->b.chip_class < CIK ||
 289                        (sscreen->b.info.drm_major == 2 &&
 290                         sscreen->b.info.drm_minor >= 35) ||
 291                        sscreen->b.info.drm_major == 3;
 292
 293         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 294                 return R600_MAP_BUFFER_ALIGNMENT;
 295
 296         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 297         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 298                 return 4;
 299
 300         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 301                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 302
 303         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 304                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 305
 306         case PIPE_CAP_TEXTURE_QUERY_LOD:
 307         case PIPE_CAP_TEXTURE_GATHER_SM5:
 308                 return HAVE_LLVM >= 0x0305;
 309         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 310                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 311
 312         /* Unsupported features. */
 313         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 314         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 315         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 316         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 317         case PIPE_CAP_USER_VERTEX_BUFFERS:
 318         case PIPE_CAP_FAKE_SW_MSAA:
 319         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 320         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 321         case PIPE_CAP_VERTEXID_NOBASE:
 322                 return 0;
 323
 324         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 325                 return 30;
 326
 327         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 328                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 329
 330         /* Stream output. */
 331         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 332                 return sscreen->b.has_streamout ? 4 : 0;
 333         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 334                 return sscreen->b.has_streamout ? 1 : 0;
 335         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 336         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 337                 return sscreen->b.has_streamout ? 32*4 : 0;
 338
 339         /* Geometry shader output. */
 340         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 341                 return 1024;
 342         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 343                 return 4095;
 344         case PIPE_CAP_MAX_VERTEX_STREAMS:
 345                 return 4;
 346
 347         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 348                 return 2048;
 349
 350         /* Texturing. */
 351         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 352         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 353                 return 15; /* 16384 */
 354         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 355                 /* textures support 8192, but layered rendering supports 2048 */
 356                 return 12;
 357         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 358                 /* textures support 8192, but layered rendering supports 2048 */
 359                 return 2048;
 360
 361         /* Render targets. */
 362         case PIPE_CAP_MAX_RENDER_TARGETS:
 363                 return 8;
 364
 365         case PIPE_CAP_MAX_VIEWPORTS:
 366                 return 16;
 367
 368         /* Timer queries, present when the clock frequency is non zero. */
 369         case PIPE_CAP_QUERY_TIMESTAMP:
 370         case PIPE_CAP_QUERY_TIME_ELAPSED:
 371                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 372
 373         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 374         case PIPE_CAP_MIN_TEXEL_OFFSET:
 375                 return -32;
 376
 377         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 378         case PIPE_CAP_MAX_TEXEL_OFFSET:
 379                 return 31;
 380
 381         case PIPE_CAP_ENDIANNESS:
 382                 return PIPE_ENDIAN_LITTLE;
 383
 384         case PIPE_CAP_VENDOR_ID:
 385                 return 0x1002;
 386         case PIPE_CAP_DEVICE_ID:
 387                 return sscreen->b.info.pci_id;
 388         case PIPE_CAP_ACCELERATED:
 389                 return 1;
 390         case PIPE_CAP_VIDEO_MEMORY:
 391                 return sscreen->b.info.vram_size >> 20;
 392         case PIPE_CAP_UMA:
 393                 return 0;
 394         }
 395         return 0;
 396 }
 397
 398 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 399 {
 400         switch(shader)
 401         {
 402         case PIPE_SHADER_FRAGMENT:
 403         case PIPE_SHADER_VERTEX:
 404         case PIPE_SHADER_GEOMETRY:
 405                 break;
 406         case PIPE_SHADER_TESS_CTRL:
 407         case PIPE_SHADER_TESS_EVAL:
 408                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 409                 if (HAVE_LLVM < 0x0306 ||
 410                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 411                         return 0;
 412                 break;
 413         case PIPE_SHADER_COMPUTE:
 414                 switch (param) {
 415                 case PIPE_SHADER_CAP_PREFERRED_IR:
 416 #if HAVE_LLVM < 0x0306
 417                         return PIPE_SHADER_IR_LLVM;
 418 #else
 419                         return PIPE_SHADER_IR_NATIVE;
 420 #endif
 421                 case PIPE_SHADER_CAP_DOUBLES:
 422                         return HAVE_LLVM >= 0x0307;
 423
 424                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 425                         uint64_t max_const_buffer_size;
 426                         pscreen->get_compute_param(pscreen,
 427                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 428                                 &max_const_buffer_size);
 429                         return max_const_buffer_size;
 430                 }
 431                 default:
 432                         /* If compute shaders don't require a special value
 433                          * for this cap, we can return the same value we
 434                          * do for other shader types. */
 435                         break;
 436                 }
 437                 break;
 438         default:
 439                 return 0;
 440         }
 441
 442         switch (param) {
 443         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 444         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 445         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 446         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 447                 return 16384;
 448         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 449                 return 32;
 450         case PIPE_SHADER_CAP_MAX_INPUTS:
 451                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 452         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 453                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 454         case PIPE_SHADER_CAP_MAX_TEMPS:
 455                 return 256; /* Max native temporaries. */
 456         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 457                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 458         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 459                 return SI_NUM_USER_CONST_BUFFERS;
 460         case PIPE_SHADER_CAP_MAX_PREDS:
 461                 return 0; /* FIXME */
 462         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 463                 return 1;
 464         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 465                 return 1;
 466         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 467                 /* Indirection of geometry shader input dimension is not
 468                  * handled yet
 469                  */
 470                 return shader != PIPE_SHADER_GEOMETRY;
 471         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 472         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 473         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 474                 return 1;
 475         case PIPE_SHADER_CAP_INTEGERS:
 476                 return 1;
 477         case PIPE_SHADER_CAP_SUBROUTINES:
 478                 return 0;
 479         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 480         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 481                 return 16;
 482         case PIPE_SHADER_CAP_PREFERRED_IR:
 483                 return PIPE_SHADER_IR_TGSI;
 484         case PIPE_SHADER_CAP_DOUBLES:
 485                 return HAVE_LLVM >= 0x0307;
 486         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 487         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 488                 return 0;
 489         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 490         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 491                 return 1;
 492         }
 493         return 0;
 494 }
 495
 496 static void si_destroy_screen(struct pipe_screen* pscreen)
 497 {
 498         struct si_screen *sscreen = (struct si_screen *)pscreen;
 499
 500         if (sscreen == NULL)
 501                 return;
 502
 503         if (!sscreen->b.ws->unref(sscreen->b.ws))
 504                 return;
 505
 506         r600_destroy_common_screen(&sscreen->b);
 507 }
 508
 509 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 510
 511 /* Initialize pipe config. This is especially important for GPUs
 512  * with 16 pipes and more where it's initialized incorrectly by
 513  * the TILING_CONFIG ioctl. */
 514 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 515 {
 516         unsigned mode2d;
 517
 518         /* This is okay, because there can be no 2D tiling without
 519          * the tile mode array, so we won't need the pipe config.
 520          * Return "success".
 521          */
 522         if (!sscreen->b.info.si_tile_mode_array_valid)
 523                 return true;
 524
 525         /* The same index is used for the 2D mode on CIK too. */
 526         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 527
 528         switch (G_009910_PIPE_CONFIG(mode2d)) {
 529         case V_02803C_ADDR_SURF_P2:
 530                 sscreen->b.tiling_info.num_channels = 2;
 531                 break;
 532         case V_02803C_X_ADDR_SURF_P4_8X16:
 533         case V_02803C_X_ADDR_SURF_P4_16X16:
 534         case V_02803C_X_ADDR_SURF_P4_16X32:
 535         case V_02803C_X_ADDR_SURF_P4_32X32:
 536                 sscreen->b.tiling_info.num_channels = 4;
 537                 break;
 538         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 539         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 540         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 541         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 542         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 543         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 544         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 545                 sscreen->b.tiling_info.num_channels = 8;
 546                 break;
 547         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 548         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 549                 sscreen->b.tiling_info.num_channels = 16;
 550                 break;
 551         default:
 552                 assert(0);
 553                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 554                         G_009910_PIPE_CONFIG(mode2d));
 555                 return false;
 556         }
 557         return true;
 558 }
 559
 560 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 561 {
 562         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 563
 564         if (sscreen == NULL) {
 565                 return NULL;
 566         }
 567
 568         /* Set functions first. */
 569         sscreen->b.b.context_create = si_create_context;
 570         sscreen->b.b.destroy = si_destroy_screen;
 571         sscreen->b.b.get_param = si_get_param;
 572         sscreen->b.b.get_shader_param = si_get_shader_param;
 573         sscreen->b.b.is_format_supported = si_is_format_supported;
 574         sscreen->b.b.resource_create = r600_resource_create_common;
 575
 576         if (!r600_common_screen_init(&sscreen->b, ws) ||
 577             !si_initialize_pipe_config(sscreen)) {
 578                 FREE(sscreen);
 579                 return NULL;
 580         }
 581
 582         sscreen->b.has_cp_dma = true;
 583         sscreen->b.has_streamout = true;
 584
 585         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 586                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 587
 588         /* Create the auxiliary context. This must be done last. */
 589         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 590
 591         return &sscreen->b.b;
 592 }