src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_surface.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_simple_shaders.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "si_pipe.h"
  46 #include "radeon/radeon_uvd.h"
  47 #include "si.h"
  48 #include "sid.h"
  49 #include "si_resource.h"
  50 #include "si_pipe.h"
  51 #include "si_state.h"
  52 #include "../radeon/r600_cs.h"
  53
  54 /*
  55  * pipe_context
  56  */
  57 void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  58               unsigned flags)
  59 {
  60         struct si_context *sctx = (struct si_context *)ctx;
  61         struct pipe_query *render_cond = NULL;
  62         boolean render_cond_cond = FALSE;
  63         unsigned render_cond_mode = 0;
  64
  65         if (fence) {
  66                 *fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
  67         }
  68
  69         /* Disable render condition. */
  70         if (sctx->b.current_render_cond) {
  71                 render_cond = sctx->b.current_render_cond;
  72                 render_cond_cond = sctx->b.current_render_cond_cond;
  73                 render_cond_mode = sctx->b.current_render_cond_mode;
  74                 ctx->render_condition(ctx, NULL, FALSE, 0);
  75         }
  76
  77         si_context_flush(sctx, flags);
  78
  79         /* Re-enable render condition. */
  80         if (render_cond) {
  81                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  82         }
  83 }
  84
  85 static void si_flush_from_st(struct pipe_context *ctx,
  86                              struct pipe_fence_handle **fence,
  87                              unsigned flags)
  88 {
  89         si_flush(ctx, fence,
  90                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  91 }
  92
  93 static void si_flush_from_winsys(void *ctx, unsigned flags)
  94 {
  95         si_flush((struct pipe_context*)ctx, NULL, flags);
  96 }
  97
  98 static void si_destroy_context(struct pipe_context *context)
  99 {
 100         struct si_context *sctx = (struct si_context *)context;
 101
 102         si_release_all_descriptors(sctx);
 103
 104         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
 105         r600_resource_reference(&sctx->border_color_table, NULL);
 106
 107         if (sctx->dummy_pixel_shader) {
 108                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 109         }
 110         for (int i = 0; i < 8; i++) {
 111                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
 112                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
 113                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
 114         }
 115         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
 116         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
 117         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
 118         util_unreference_framebuffer_state(&sctx->framebuffer);
 119
 120         util_blitter_destroy(sctx->blitter);
 121
 122         r600_common_context_cleanup(&sctx->b);
 123         FREE(sctx);
 124 }
 125
 126 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
 127 {
 128         struct si_context *sctx = CALLOC_STRUCT(si_context);
 129         struct si_screen* sscreen = (struct si_screen *)screen;
 130         int shader, i;
 131
 132         if (sctx == NULL)
 133                 return NULL;
 134
 135         sctx->b.b.screen = screen; /* this must be set first */
 136         sctx->b.b.priv = priv;
 137         sctx->b.b.destroy = si_destroy_context;
 138         sctx->b.b.flush = si_flush_from_st;
 139         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 140
 141         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 142                 goto fail;
 143
 144         si_init_blit_functions(sctx);
 145         si_init_compute_functions(sctx);
 146
 147         if (sscreen->b.info.has_uvd) {
 148                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 149                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 150         } else {
 151                 sctx->b.b.create_video_codec = vl_create_decoder;
 152                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 153         }
 154
 155         sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
 156         sctx->b.rings.gfx.flush = si_flush_from_winsys;
 157
 158         si_init_all_descriptors(sctx);
 159
 160         /* Initialize cache_flush. */
 161         sctx->cache_flush = si_atom_cache_flush;
 162         sctx->atoms.cache_flush = &sctx->cache_flush;
 163
 164         sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
 165
 166         switch (sctx->b.chip_class) {
 167         case SI:
 168         case CIK:
 169                 si_init_state_functions(sctx);
 170                 si_init_config(sctx);
 171                 break;
 172         default:
 173                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 174                 goto fail;
 175         }
 176
 177         sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
 178
 179         sctx->blitter = util_blitter_create(&sctx->b.b);
 180         if (sctx->blitter == NULL)
 181                 goto fail;
 182
 183         sctx->dummy_pixel_shader =
 184                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 185                                                      TGSI_SEMANTIC_GENERIC,
 186                                                      TGSI_INTERPOLATE_CONSTANT);
 187         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 188
 189         /* these must be last */
 190         si_begin_new_cs(sctx);
 191         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 192
 193         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 194          * with a NULL buffer). We need to use a dummy buffer instead. */
 195         if (sctx->b.chip_class == CIK) {
 196                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 197                                                                  PIPE_USAGE_STATIC, 16);
 198                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 199
 200                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 201                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 202                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 203                                                               &sctx->null_const_buf);
 204                         }
 205                 }
 206
 207                 /* Clear the NULL constant buffer, because loads should return zeros. */
 208                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 209                                      sctx->null_const_buf.buffer->width0, 0);
 210         }
 211
 212         return &sctx->b.b;
 213 fail:
 214         si_destroy_context(&sctx->b.b);
 215         return NULL;
 216 }
 217
 218 /*
 219  * pipe_screen
 220  */
 221 static const char* si_get_vendor(struct pipe_screen* pscreen)
 222 {
 223         return "X.Org";
 224 }
 225
 226 const char *si_get_llvm_processor_name(enum radeon_family family)
 227 {
 228         switch (family) {
 229                 case CHIP_TAHITI: return "tahiti";
 230                 case CHIP_PITCAIRN: return "pitcairn";
 231                 case CHIP_VERDE: return "verde";
 232                 case CHIP_OLAND: return "oland";
 233 #if HAVE_LLVM <= 0x0303
 234                 default: return "SI";
 235 #else
 236                 case CHIP_HAINAN: return "hainan";
 237                 case CHIP_BONAIRE: return "bonaire";
 238                 case CHIP_KABINI: return "kabini";
 239                 case CHIP_KAVERI: return "kaveri";
 240                 case CHIP_HAWAII: return "hawaii";
 241                 default: return "";
 242 #endif
 243         }
 244 }
 245
 246 static const char *si_get_family_name(enum radeon_family family)
 247 {
 248         switch(family) {
 249         case CHIP_TAHITI: return "AMD TAHITI";
 250         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 251         case CHIP_VERDE: return "AMD CAPE VERDE";
 252         case CHIP_OLAND: return "AMD OLAND";
 253         case CHIP_HAINAN: return "AMD HAINAN";
 254         case CHIP_BONAIRE: return "AMD BONAIRE";
 255         case CHIP_KAVERI: return "AMD KAVERI";
 256         case CHIP_KABINI: return "AMD KABINI";
 257         case CHIP_HAWAII: return "AMD HAWAII";
 258         default: return "AMD unknown";
 259         }
 260 }
 261
 262 static const char* si_get_name(struct pipe_screen* pscreen)
 263 {
 264         struct si_screen *sscreen = (struct si_screen *)pscreen;
 265
 266         return si_get_family_name(sscreen->b.family);
 267 }
 268
 269 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 270 {
 271         struct si_screen *sscreen = (struct si_screen *)pscreen;
 272
 273         switch (param) {
 274         /* Supported features (boolean caps). */
 275         case PIPE_CAP_TWO_SIDED_STENCIL:
 276         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 277         case PIPE_CAP_ANISOTROPIC_FILTER:
 278         case PIPE_CAP_POINT_SPRITE:
 279         case PIPE_CAP_OCCLUSION_QUERY:
 280         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 281         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 282         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 283         case PIPE_CAP_TEXTURE_SWIZZLE:
 284         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 286         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 287         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 288         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 289         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 290         case PIPE_CAP_SM3:
 291         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 292         case PIPE_CAP_PRIMITIVE_RESTART:
 293         case PIPE_CAP_CONDITIONAL_RENDER:
 294         case PIPE_CAP_TEXTURE_BARRIER:
 295         case PIPE_CAP_INDEP_BLEND_ENABLE:
 296         case PIPE_CAP_INDEP_BLEND_FUNC:
 297         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 298         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 299         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 300         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 301         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 302         case PIPE_CAP_USER_INDEX_BUFFERS:
 303         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 304         case PIPE_CAP_START_INSTANCE:
 305         case PIPE_CAP_NPOT_TEXTURES:
 306         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 307         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 308         case PIPE_CAP_TGSI_INSTANCEID:
 309         case PIPE_CAP_COMPUTE:
 310         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 311         case PIPE_CAP_TGSI_VS_LAYER:
 312         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 313                 return 1;
 314
 315         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 316                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 317                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 318                                                sscreen->b.info.drm_minor >= 35);
 319
 320         case PIPE_CAP_TGSI_TEXCOORD:
 321                 return 0;
 322
 323         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 324                 return 64;
 325
 326         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 327                 return 256;
 328
 329         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 330                 return 140;
 331
 332         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 333                 return 1;
 334         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 335                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 336
 337         /* Unsupported features. */
 338         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 339         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 340         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 341         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 342         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 343         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 344         case PIPE_CAP_USER_VERTEX_BUFFERS:
 345         case PIPE_CAP_CUBE_MAP_ARRAY:
 346                 return 0;
 347
 348         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 349                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 350
 351         /* Stream output. */
 352         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 353                 return sscreen->b.has_streamout ? 4 : 0;
 354         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 355                 return sscreen->b.has_streamout ? 1 : 0;
 356         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 357         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 358                 return sscreen->b.has_streamout ? 32*4 : 0;
 359
 360         /* Texturing. */
 361         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 362         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 363         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 364                         return 15;
 365         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 366                 return 16384;
 367         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 368                 return 32;
 369
 370         /* Render targets. */
 371         case PIPE_CAP_MAX_RENDER_TARGETS:
 372                 return 8;
 373
 374         case PIPE_CAP_MAX_VIEWPORTS:
 375                 return 1;
 376
 377         /* Timer queries, present when the clock frequency is non zero. */
 378         case PIPE_CAP_QUERY_TIMESTAMP:
 379         case PIPE_CAP_QUERY_TIME_ELAPSED:
 380                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 381
 382         case PIPE_CAP_MIN_TEXEL_OFFSET:
 383                 return -8;
 384
 385         case PIPE_CAP_MAX_TEXEL_OFFSET:
 386                 return 7;
 387         case PIPE_CAP_ENDIANNESS:
 388                 return PIPE_ENDIAN_LITTLE;
 389         }
 390         return 0;
 391 }
 392
 393 static float si_get_paramf(struct pipe_screen* pscreen,
 394                              enum pipe_capf param)
 395 {
 396         switch (param) {
 397         case PIPE_CAPF_MAX_LINE_WIDTH:
 398         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 399         case PIPE_CAPF_MAX_POINT_WIDTH:
 400         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 401                 return 16384.0f;
 402         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 403                 return 16.0f;
 404         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 405                 return 16.0f;
 406         case PIPE_CAPF_GUARD_BAND_LEFT:
 407         case PIPE_CAPF_GUARD_BAND_TOP:
 408         case PIPE_CAPF_GUARD_BAND_RIGHT:
 409         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 410                 return 0.0f;
 411         }
 412         return 0.0f;
 413 }
 414
 415 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 416 {
 417         switch(shader)
 418         {
 419         case PIPE_SHADER_FRAGMENT:
 420         case PIPE_SHADER_VERTEX:
 421                 break;
 422         case PIPE_SHADER_GEOMETRY:
 423                 /* TODO: support and enable geometry programs */
 424                 return 0;
 425         case PIPE_SHADER_COMPUTE:
 426                 switch (param) {
 427                 case PIPE_SHADER_CAP_PREFERRED_IR:
 428                         return PIPE_SHADER_IR_LLVM;
 429                 default:
 430                         return 0;
 431                 }
 432         default:
 433                 /* TODO: support tessellation */
 434                 return 0;
 435         }
 436
 437         switch (param) {
 438         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 439         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 440         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 441         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 442                 return 16384;
 443         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 444                 return 32;
 445         case PIPE_SHADER_CAP_MAX_INPUTS:
 446                 return 32;
 447         case PIPE_SHADER_CAP_MAX_TEMPS:
 448                 return 256; /* Max native temporaries. */
 449         case PIPE_SHADER_CAP_MAX_ADDRS:
 450                 /* FIXME Isn't this equal to TEMPS? */
 451                 return 1; /* Max native address registers */
 452         case PIPE_SHADER_CAP_MAX_CONSTS:
 453                 return 4096; /* actually only memory limits this */
 454         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 455                 return NUM_PIPE_CONST_BUFFERS;
 456         case PIPE_SHADER_CAP_MAX_PREDS:
 457                 return 0; /* FIXME */
 458         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 459                 return 1;
 460         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 461                 return 0;
 462         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 463         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 464         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 465         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 466                 return 1;
 467         case PIPE_SHADER_CAP_INTEGERS:
 468                 return 1;
 469         case PIPE_SHADER_CAP_SUBROUTINES:
 470                 return 0;
 471         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 472         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 473                 return 16;
 474         case PIPE_SHADER_CAP_PREFERRED_IR:
 475                 return PIPE_SHADER_IR_TGSI;
 476         }
 477         return 0;
 478 }
 479
 480 static int si_get_video_param(struct pipe_screen *screen,
 481                               enum pipe_video_profile profile,
 482                               enum pipe_video_entrypoint entrypoint,
 483                               enum pipe_video_cap param)
 484 {
 485         switch (param) {
 486         case PIPE_VIDEO_CAP_SUPPORTED:
 487                 return vl_profile_supported(screen, profile, entrypoint);
 488         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 489                 return 1;
 490         case PIPE_VIDEO_CAP_MAX_WIDTH:
 491         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 492                 return vl_video_buffer_max_size(screen);
 493         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 494                 return PIPE_FORMAT_NV12;
 495         case PIPE_VIDEO_CAP_MAX_LEVEL:
 496                 return vl_level_supported(screen, profile);
 497         default:
 498                 return 0;
 499         }
 500 }
 501
 502 static int si_get_compute_param(struct pipe_screen *screen,
 503         enum pipe_compute_cap param,
 504         void *ret)
 505 {
 506         struct si_screen *sscreen = (struct si_screen *)screen;
 507         //TODO: select these params by asic
 508         switch (param) {
 509         case PIPE_COMPUTE_CAP_IR_TARGET: {
 510                 const char *gpu = si_get_llvm_processor_name(sscreen->b.family);
 511                 if (ret) {
 512                         sprintf(ret, "%s-r600--", gpu);
 513                 }
 514                 return (8 + strlen(gpu)) * sizeof(char);
 515         }
 516         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 517                 if (ret) {
 518                         uint64_t * grid_dimension = ret;
 519                         grid_dimension[0] = 3;
 520                 }
 521                 return 1 * sizeof(uint64_t);
 522         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 523                 if (ret) {
 524                         uint64_t * grid_size = ret;
 525                         grid_size[0] = 65535;
 526                         grid_size[1] = 65535;
 527                         grid_size[2] = 1;
 528                 }
 529                 return 3 * sizeof(uint64_t) ;
 530
 531         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 532                 if (ret) {
 533                         uint64_t * block_size = ret;
 534                         block_size[0] = 256;
 535                         block_size[1] = 256;
 536                         block_size[2] = 256;
 537                 }
 538                 return 3 * sizeof(uint64_t);
 539         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 540                 if (ret) {
 541                         uint64_t * max_threads_per_block = ret;
 542                         *max_threads_per_block = 256;
 543                 }
 544                 return sizeof(uint64_t);
 545
 546         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 547                 if (ret) {
 548                         uint64_t *max_global_size = ret;
 549                         /* XXX: Not sure what to put here. */
 550                         *max_global_size = 2000000000;
 551                 }
 552                 return sizeof(uint64_t);
 553         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 554                 if (ret) {
 555                         uint64_t *max_local_size = ret;
 556                         /* Value reported by the closed source driver. */
 557                         *max_local_size = 32768;
 558                 }
 559                 return sizeof(uint64_t);
 560         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 561                 if (ret) {
 562                         uint64_t *max_input_size = ret;
 563                         /* Value reported by the closed source driver. */
 564                         *max_input_size = 1024;
 565                 }
 566                 return sizeof(uint64_t);
 567         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 568                 if (ret) {
 569                         uint64_t max_global_size;
 570                         uint64_t *max_mem_alloc_size = ret;
 571                         si_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 572                         *max_mem_alloc_size = max_global_size / 4;
 573                 }
 574                 return sizeof(uint64_t);
 575         default:
 576                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 577                 return 0;
 578         }
 579 }
 580
 581 static void si_destroy_screen(struct pipe_screen* pscreen)
 582 {
 583         struct si_screen *sscreen = (struct si_screen *)pscreen;
 584
 585         if (sscreen == NULL)
 586                 return;
 587
 588         if (!radeon_winsys_unref(sscreen->b.ws))
 589                 return;
 590
 591         r600_common_screen_cleanup(&sscreen->b);
 592
 593 #if SI_TRACE_CS
 594         if (sscreen->trace_bo) {
 595                 sscreen->ws->buffer_unmap(sscreen->trace_bo->cs_buf);
 596                 pipe_resource_reference((struct pipe_resource**)&sscreen->trace_bo, NULL);
 597         }
 598 #endif
 599
 600         sscreen->b.ws->destroy(sscreen->b.ws);
 601         FREE(sscreen);
 602 }
 603
 604 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 605 {
 606         struct si_screen *sscreen = (struct si_screen*)screen;
 607
 608         return 1000000 * sscreen->b.ws->query_value(sscreen->b.ws, RADEON_TIMESTAMP) /
 609                 sscreen->b.info.r600_clock_crystal_freq;
 610 }
 611
 612 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 613 {
 614         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 615         if (sscreen == NULL) {
 616                 return NULL;
 617         }
 618
 619         ws->query_info(ws, &sscreen->b.info);
 620
 621         /* Set functions first. */
 622         sscreen->b.b.context_create = si_create_context;
 623         sscreen->b.b.destroy = si_destroy_screen;
 624         sscreen->b.b.get_name = si_get_name;
 625         sscreen->b.b.get_vendor = si_get_vendor;
 626         sscreen->b.b.get_param = si_get_param;
 627         sscreen->b.b.get_shader_param = si_get_shader_param;
 628         sscreen->b.b.get_paramf = si_get_paramf;
 629         sscreen->b.b.get_compute_param = si_get_compute_param;
 630         sscreen->b.b.get_timestamp = si_get_timestamp;
 631         sscreen->b.b.is_format_supported = si_is_format_supported;
 632         if (sscreen->b.info.has_uvd) {
 633                 sscreen->b.b.get_video_param = ruvd_get_video_param;
 634                 sscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 635         } else {
 636                 sscreen->b.b.get_video_param = si_get_video_param;
 637                 sscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 638         }
 639
 640         if (!r600_common_screen_init(&sscreen->b, ws)) {
 641                 FREE(sscreen);
 642                 return NULL;
 643         }
 644
 645         sscreen->b.has_cp_dma = true;
 646         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 647
 648         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 649                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 650
 651 #if SI_TRACE_CS
 652         sscreen->cs_count = 0;
 653         if (sscreen->info.drm_minor >= 28) {
 654                 sscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&sscreen->screen,
 655                                                                                 PIPE_BIND_CUSTOM,
 656                                                                                 PIPE_USAGE_STAGING,
 657                                                                                 4096);
 658                 if (sscreen->trace_bo) {
 659                         sscreen->trace_ptr = sscreen->ws->buffer_map(sscreen->trace_bo->cs_buf, NULL,
 660                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 661                 }
 662         }
 663 #endif
 664
 665         /* Create the auxiliary context. This must be done last. */
 666         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 667
 668         return &sscreen->b.b;
 669 }