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panfrost/midgard: Enable lower_find_lsb
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 static const struct debug_named_value debug_options[] = {
46 /* Shader logging options: */
47 { "vs", DBG(VS), "Print vertex shaders" },
48 { "ps", DBG(PS), "Print pixel shaders" },
49 { "gs", DBG(GS), "Print geometry shaders" },
50 { "tcs", DBG(TCS), "Print tessellation control shaders" },
51 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
52 { "cs", DBG(CS), "Print compute shaders" },
53 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
54 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
55 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
56 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
57
58 /* Shader compiler options the shader cache should be aware of: */
59 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
60 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
61 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
62
63 /* Shader compiler options (with no effect on the shader cache): */
64 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
65 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
66 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
67 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
68
69 /* Information logging options: */
70 { "info", DBG(INFO), "Print driver information" },
71 { "tex", DBG(TEX), "Print texture info" },
72 { "compute", DBG(COMPUTE), "Print compute info" },
73 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
74
75 /* Driver options: */
76 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
77 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
78 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
79 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
80 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
81 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
82
83 /* 3D engine options: */
84 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
85 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
86 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
87 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
88 { "dpbb", DBG(DPBB), "Enable DPBB." },
89 { "dfsm", DBG(DFSM), "Enable DFSM." },
90 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
91 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
92 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
93 { "notiling", DBG(NO_TILING), "Disable tiling" },
94 { "nodcc", DBG(NO_DCC), "Disable DCC." },
95 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
96 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
97 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
98 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
99
100 /* Tests: */
101 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
102 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
103 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
104 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
105 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
106 { "testgds", DBG(TEST_GDS), "Test GDS." },
107 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
108 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
109
110 DEBUG_NAMED_VALUE_END /* must be last */
111 };
112
113 static void si_init_compiler(struct si_screen *sscreen,
114 struct ac_llvm_compiler *compiler)
115 {
116 /* Only create the less-optimizing version of the compiler on APUs
117 * predating Ryzen (Raven). */
118 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
119 sscreen->info.chip_class <= VI;
120
121 enum ac_target_machine_options tm_options =
122 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
123 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
124 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
125 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
126 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
127 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
128 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
129
130 ac_init_llvm_once();
131 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
132 compiler->passes = ac_create_llvm_passes(compiler->tm);
133
134 if (compiler->low_opt_tm)
135 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
136 }
137
138 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
139 {
140 ac_destroy_llvm_passes(compiler->passes);
141 ac_destroy_llvm_passes(compiler->low_opt_passes);
142 ac_destroy_llvm_compiler(compiler);
143 }
144
145 /*
146 * pipe_context
147 */
148 static void si_destroy_context(struct pipe_context *context)
149 {
150 struct si_context *sctx = (struct si_context *)context;
151 int i;
152
153 /* Unreference the framebuffer normally to disable related logic
154 * properly.
155 */
156 struct pipe_framebuffer_state fb = {};
157 if (context->set_framebuffer_state)
158 context->set_framebuffer_state(context, &fb);
159
160 si_release_all_descriptors(sctx);
161
162 pipe_resource_reference(&sctx->esgs_ring, NULL);
163 pipe_resource_reference(&sctx->gsvs_ring, NULL);
164 pipe_resource_reference(&sctx->tess_rings, NULL);
165 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
166 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
167 si_resource_reference(&sctx->border_color_buffer, NULL);
168 free(sctx->border_color_table);
169 si_resource_reference(&sctx->scratch_buffer, NULL);
170 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
171 si_resource_reference(&sctx->wait_mem_scratch, NULL);
172
173 si_pm4_free_state(sctx, sctx->init_config, ~0);
174 if (sctx->init_config_gs_rings)
175 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
176 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
177 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
178
179 if (sctx->fixed_func_tcs_shader.cso)
180 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
181 if (sctx->custom_dsa_flush)
182 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
183 if (sctx->custom_blend_resolve)
184 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
185 if (sctx->custom_blend_fmask_decompress)
186 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
187 if (sctx->custom_blend_eliminate_fastclear)
188 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
189 if (sctx->custom_blend_dcc_decompress)
190 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
191 if (sctx->vs_blit_pos)
192 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
193 if (sctx->vs_blit_pos_layered)
194 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
195 if (sctx->vs_blit_color)
196 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
197 if (sctx->vs_blit_color_layered)
198 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
199 if (sctx->vs_blit_texcoord)
200 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
201 if (sctx->cs_clear_buffer)
202 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
203 if (sctx->cs_copy_buffer)
204 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
205 if (sctx->cs_copy_image)
206 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
207 if (sctx->cs_copy_image_1d_array)
208 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
209 if (sctx->cs_clear_render_target)
210 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
211 if (sctx->cs_clear_render_target_1d_array)
212 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
213 if (sctx->cs_dcc_retile)
214 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
215
216 if (sctx->blitter)
217 util_blitter_destroy(sctx->blitter);
218
219 /* Release DCC stats. */
220 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
221 assert(!sctx->dcc_stats[i].query_active);
222
223 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
224 if (sctx->dcc_stats[i].ps_stats[j])
225 sctx->b.destroy_query(&sctx->b,
226 sctx->dcc_stats[i].ps_stats[j]);
227
228 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
229 }
230
231 if (sctx->query_result_shader)
232 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
233
234 if (sctx->gfx_cs)
235 sctx->ws->cs_destroy(sctx->gfx_cs);
236 if (sctx->dma_cs)
237 sctx->ws->cs_destroy(sctx->dma_cs);
238 if (sctx->ctx)
239 sctx->ws->ctx_destroy(sctx->ctx);
240
241 if (sctx->b.stream_uploader)
242 u_upload_destroy(sctx->b.stream_uploader);
243 if (sctx->b.const_uploader)
244 u_upload_destroy(sctx->b.const_uploader);
245 if (sctx->cached_gtt_allocator)
246 u_upload_destroy(sctx->cached_gtt_allocator);
247
248 slab_destroy_child(&sctx->pool_transfers);
249 slab_destroy_child(&sctx->pool_transfers_unsync);
250
251 if (sctx->allocator_zeroed_memory)
252 u_suballocator_destroy(sctx->allocator_zeroed_memory);
253
254 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
255 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
256 si_resource_reference(&sctx->eop_bug_scratch, NULL);
257
258 si_destroy_compiler(&sctx->compiler);
259
260 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
261
262 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
263 _mesa_hash_table_destroy(sctx->img_handles, NULL);
264
265 util_dynarray_fini(&sctx->resident_tex_handles);
266 util_dynarray_fini(&sctx->resident_img_handles);
267 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
268 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
269 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
270 si_unref_sdma_uploads(sctx);
271 FREE(sctx);
272 }
273
274 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
275 {
276 struct si_context *sctx = (struct si_context *)ctx;
277
278 if (sctx->screen->info.has_gpu_reset_status_query)
279 return sctx->ws->ctx_query_reset_status(sctx->ctx);
280
281 if (sctx->screen->info.has_gpu_reset_counter_query) {
282 unsigned latest = sctx->ws->query_value(sctx->ws,
283 RADEON_GPU_RESET_COUNTER);
284
285 if (sctx->gpu_reset_counter == latest)
286 return PIPE_NO_RESET;
287
288 sctx->gpu_reset_counter = latest;
289 return PIPE_UNKNOWN_CONTEXT_RESET;
290 }
291
292 return PIPE_NO_RESET;
293 }
294
295 static void si_set_device_reset_callback(struct pipe_context *ctx,
296 const struct pipe_device_reset_callback *cb)
297 {
298 struct si_context *sctx = (struct si_context *)ctx;
299
300 if (cb)
301 sctx->device_reset_callback = *cb;
302 else
303 memset(&sctx->device_reset_callback, 0,
304 sizeof(sctx->device_reset_callback));
305 }
306
307 bool si_check_device_reset(struct si_context *sctx)
308 {
309 enum pipe_reset_status status;
310
311 if (!sctx->device_reset_callback.reset)
312 return false;
313
314 if (!sctx->b.get_device_reset_status)
315 return false;
316
317 status = sctx->b.get_device_reset_status(&sctx->b);
318 if (status == PIPE_NO_RESET)
319 return false;
320
321 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
322 return true;
323 }
324
325 /* Apitrace profiling:
326 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
327 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
328 * and remember its number.
329 * 3) In Mesa, enable queries and performance counters around that draw
330 * call and print the results.
331 * 4) glretrace --benchmark --markers ..
332 */
333 static void si_emit_string_marker(struct pipe_context *ctx,
334 const char *string, int len)
335 {
336 struct si_context *sctx = (struct si_context *)ctx;
337
338 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
339
340 if (sctx->log)
341 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
342 }
343
344 static void si_set_debug_callback(struct pipe_context *ctx,
345 const struct pipe_debug_callback *cb)
346 {
347 struct si_context *sctx = (struct si_context *)ctx;
348 struct si_screen *screen = sctx->screen;
349
350 util_queue_finish(&screen->shader_compiler_queue);
351 util_queue_finish(&screen->shader_compiler_queue_low_priority);
352
353 if (cb)
354 sctx->debug = *cb;
355 else
356 memset(&sctx->debug, 0, sizeof(sctx->debug));
357 }
358
359 static void si_set_log_context(struct pipe_context *ctx,
360 struct u_log_context *log)
361 {
362 struct si_context *sctx = (struct si_context *)ctx;
363 sctx->log = log;
364
365 if (log)
366 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
367 }
368
369 static void si_set_context_param(struct pipe_context *ctx,
370 enum pipe_context_param param,
371 unsigned value)
372 {
373 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
374
375 switch (param) {
376 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
377 ws->pin_threads_to_L3_cache(ws, value);
378 break;
379 default:;
380 }
381 }
382
383 static struct pipe_context *si_create_context(struct pipe_screen *screen,
384 unsigned flags)
385 {
386 struct si_context *sctx = CALLOC_STRUCT(si_context);
387 struct si_screen* sscreen = (struct si_screen *)screen;
388 struct radeon_winsys *ws = sscreen->ws;
389 int shader, i;
390 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
391
392 if (!sctx)
393 return NULL;
394
395 sctx->has_graphics = sscreen->info.chip_class == SI ||
396 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
397
398 if (flags & PIPE_CONTEXT_DEBUG)
399 sscreen->record_llvm_ir = true; /* racy but not critical */
400
401 sctx->b.screen = screen; /* this must be set first */
402 sctx->b.priv = NULL;
403 sctx->b.destroy = si_destroy_context;
404 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
405 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
406
407 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
408 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
409
410 sctx->ws = sscreen->ws;
411 sctx->family = sscreen->info.family;
412 sctx->chip_class = sscreen->info.chip_class;
413
414 if (sscreen->info.has_gpu_reset_counter_query) {
415 sctx->gpu_reset_counter =
416 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
417 }
418
419
420 if (sctx->chip_class == CIK ||
421 sctx->chip_class == VI ||
422 sctx->chip_class == GFX9) {
423 sctx->eop_bug_scratch = si_resource(
424 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
425 16 * sscreen->info.num_render_backends));
426 if (!sctx->eop_bug_scratch)
427 goto fail;
428 }
429
430 /* Initialize context allocators. */
431 sctx->allocator_zeroed_memory =
432 u_suballocator_create(&sctx->b, 128 * 1024,
433 0, PIPE_USAGE_DEFAULT,
434 SI_RESOURCE_FLAG_UNMAPPABLE |
435 SI_RESOURCE_FLAG_CLEAR, false);
436 if (!sctx->allocator_zeroed_memory)
437 goto fail;
438
439 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
440 0, PIPE_USAGE_STREAM,
441 SI_RESOURCE_FLAG_READ_ONLY);
442 if (!sctx->b.stream_uploader)
443 goto fail;
444
445 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
446 0, PIPE_USAGE_STAGING, 0);
447 if (!sctx->cached_gtt_allocator)
448 goto fail;
449
450 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
451 if (!sctx->ctx)
452 goto fail;
453
454 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
455 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
456 (void*)si_flush_dma_cs,
457 sctx, stop_exec_on_failure);
458 }
459
460 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
461 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
462 0, PIPE_USAGE_DEFAULT,
463 SI_RESOURCE_FLAG_32BIT |
464 (use_sdma_upload ?
465 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
466 (sscreen->cpdma_prefetch_writes_memory ?
467 0 : SI_RESOURCE_FLAG_READ_ONLY)));
468 if (!sctx->b.const_uploader)
469 goto fail;
470
471 if (use_sdma_upload)
472 u_upload_enable_flush_explicit(sctx->b.const_uploader);
473
474 sctx->gfx_cs = ws->cs_create(sctx->ctx,
475 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
476 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
477
478 /* Border colors. */
479 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
480 sizeof(*sctx->border_color_table));
481 if (!sctx->border_color_table)
482 goto fail;
483
484 sctx->border_color_buffer = si_resource(
485 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
486 SI_MAX_BORDER_COLORS *
487 sizeof(*sctx->border_color_table)));
488 if (!sctx->border_color_buffer)
489 goto fail;
490
491 sctx->border_color_map =
492 ws->buffer_map(sctx->border_color_buffer->buf,
493 NULL, PIPE_TRANSFER_WRITE);
494 if (!sctx->border_color_map)
495 goto fail;
496
497 /* Initialize context functions used by graphics and compute. */
498 sctx->b.emit_string_marker = si_emit_string_marker;
499 sctx->b.set_debug_callback = si_set_debug_callback;
500 sctx->b.set_log_context = si_set_log_context;
501 sctx->b.set_context_param = si_set_context_param;
502 sctx->b.get_device_reset_status = si_get_reset_status;
503 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
504 sctx->b.memory_barrier = si_memory_barrier;
505
506 si_init_all_descriptors(sctx);
507 si_init_buffer_functions(sctx);
508 si_init_clear_functions(sctx);
509 si_init_blit_functions(sctx);
510 si_init_compute_functions(sctx);
511 si_init_compute_blit_functions(sctx);
512 si_init_debug_functions(sctx);
513 si_init_fence_functions(sctx);
514
515 if (sscreen->debug_flags & DBG(FORCE_DMA))
516 sctx->b.resource_copy_region = sctx->dma_copy;
517
518 /* Initialize graphics-only context functions. */
519 if (sctx->has_graphics) {
520 si_init_context_texture_functions(sctx);
521 si_init_query_functions(sctx);
522 si_init_msaa_functions(sctx);
523 si_init_shader_functions(sctx);
524 si_init_state_functions(sctx);
525 si_init_streamout_functions(sctx);
526 si_init_viewport_functions(sctx);
527
528 sctx->blitter = util_blitter_create(&sctx->b);
529 if (sctx->blitter == NULL)
530 goto fail;
531 sctx->blitter->skip_viewport_restore = true;
532
533 si_init_draw_functions(sctx);
534 }
535
536 /* Initialize SDMA functions. */
537 if (sctx->chip_class >= CIK)
538 cik_init_sdma_functions(sctx);
539 else
540 si_init_dma_functions(sctx);
541
542 sctx->sample_mask = 0xffff;
543
544 /* Initialize multimedia functions. */
545 if (sscreen->info.has_hw_decode) {
546 sctx->b.create_video_codec = si_uvd_create_decoder;
547 sctx->b.create_video_buffer = si_video_buffer_create;
548 } else {
549 sctx->b.create_video_codec = vl_create_decoder;
550 sctx->b.create_video_buffer = vl_video_buffer_create;
551 }
552
553 if (sctx->chip_class >= GFX9) {
554 sctx->wait_mem_scratch = si_resource(
555 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
556 if (!sctx->wait_mem_scratch)
557 goto fail;
558
559 /* Initialize the memory. */
560 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
561 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
562 }
563
564 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
565 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
566 if (sctx->chip_class == CIK) {
567 sctx->null_const_buf.buffer =
568 pipe_aligned_buffer_create(screen,
569 SI_RESOURCE_FLAG_32BIT,
570 PIPE_USAGE_DEFAULT, 16,
571 sctx->screen->info.tcc_cache_line_size);
572 if (!sctx->null_const_buf.buffer)
573 goto fail;
574 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
575
576 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
577 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
578 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
579 sctx->b.set_constant_buffer(&sctx->b, shader, i,
580 &sctx->null_const_buf);
581 }
582 }
583
584 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
585 &sctx->null_const_buf);
586 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
587 &sctx->null_const_buf);
588 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
589 &sctx->null_const_buf);
590 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
591 &sctx->null_const_buf);
592 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
593 &sctx->null_const_buf);
594 }
595
596 uint64_t max_threads_per_block;
597 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
598 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
599 &max_threads_per_block);
600
601 /* The maximum number of scratch waves. Scratch space isn't divided
602 * evenly between CUs. The number is only a function of the number of CUs.
603 * We can decrease the constant to decrease the scratch buffer size.
604 *
605 * sctx->scratch_waves must be >= the maximum posible size of
606 * 1 threadgroup, so that the hw doesn't hang from being unable
607 * to start any.
608 *
609 * The recommended value is 4 per CU at most. Higher numbers don't
610 * bring much benefit, but they still occupy chip resources (think
611 * async compute). I've seen ~2% performance difference between 4 and 32.
612 */
613 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
614 max_threads_per_block / 64);
615
616 si_init_compiler(sscreen, &sctx->compiler);
617
618 /* Bindless handles. */
619 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
620 _mesa_key_pointer_equal);
621 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
622 _mesa_key_pointer_equal);
623
624 util_dynarray_init(&sctx->resident_tex_handles, NULL);
625 util_dynarray_init(&sctx->resident_img_handles, NULL);
626 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
627 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
628 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
629
630 sctx->sample_pos_buffer =
631 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
632 sizeof(sctx->sample_positions));
633 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
634 sizeof(sctx->sample_positions), &sctx->sample_positions);
635
636 /* this must be last */
637 si_begin_new_gfx_cs(sctx);
638
639 if (sctx->chip_class == CIK) {
640 /* Clear the NULL constant buffer, because loads should return zeros. */
641 uint32_t clear_value = 0;
642 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
643 sctx->null_const_buf.buffer->width0,
644 &clear_value, 4, SI_COHERENCY_SHADER);
645 }
646 return &sctx->b;
647 fail:
648 fprintf(stderr, "radeonsi: Failed to create a context.\n");
649 si_destroy_context(&sctx->b);
650 return NULL;
651 }
652
653 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
654 void *priv, unsigned flags)
655 {
656 struct si_screen *sscreen = (struct si_screen *)screen;
657 struct pipe_context *ctx;
658
659 if (sscreen->debug_flags & DBG(CHECK_VM))
660 flags |= PIPE_CONTEXT_DEBUG;
661
662 ctx = si_create_context(screen, flags);
663
664 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
665 return ctx;
666
667 /* Clover (compute-only) is unsupported. */
668 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
669 return ctx;
670
671 /* When shaders are logged to stderr, asynchronous compilation is
672 * disabled too. */
673 if (sscreen->debug_flags & DBG_ALL_SHADERS)
674 return ctx;
675
676 /* Use asynchronous flushes only on amdgpu, since the radeon
677 * implementation for fence_server_sync is incomplete. */
678 return threaded_context_create(ctx, &sscreen->pool_transfers,
679 si_replace_buffer_storage,
680 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
681 &((struct si_context*)ctx)->tc);
682 }
683
684 /*
685 * pipe_screen
686 */
687 static void si_destroy_screen(struct pipe_screen* pscreen)
688 {
689 struct si_screen *sscreen = (struct si_screen *)pscreen;
690 struct si_shader_part *parts[] = {
691 sscreen->vs_prologs,
692 sscreen->tcs_epilogs,
693 sscreen->gs_prologs,
694 sscreen->ps_prologs,
695 sscreen->ps_epilogs
696 };
697 unsigned i;
698
699 if (!sscreen->ws->unref(sscreen->ws))
700 return;
701
702 util_queue_destroy(&sscreen->shader_compiler_queue);
703 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
704
705 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
706 si_destroy_compiler(&sscreen->compiler[i]);
707
708 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
709 si_destroy_compiler(&sscreen->compiler_lowp[i]);
710
711 /* Free shader parts. */
712 for (i = 0; i < ARRAY_SIZE(parts); i++) {
713 while (parts[i]) {
714 struct si_shader_part *part = parts[i];
715
716 parts[i] = part->next;
717 ac_shader_binary_clean(&part->binary);
718 FREE(part);
719 }
720 }
721 mtx_destroy(&sscreen->shader_parts_mutex);
722 si_destroy_shader_cache(sscreen);
723
724 si_destroy_perfcounters(sscreen);
725 si_gpu_load_kill_thread(sscreen);
726
727 mtx_destroy(&sscreen->gpu_load_mutex);
728 mtx_destroy(&sscreen->aux_context_lock);
729 sscreen->aux_context->destroy(sscreen->aux_context);
730
731 slab_destroy_parent(&sscreen->pool_transfers);
732
733 disk_cache_destroy(sscreen->disk_shader_cache);
734 sscreen->ws->destroy(sscreen->ws);
735 FREE(sscreen);
736 }
737
738 static void si_init_gs_info(struct si_screen *sscreen)
739 {
740 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
741 sscreen->info.family);
742 }
743
744 static void si_test_vmfault(struct si_screen *sscreen)
745 {
746 struct pipe_context *ctx = sscreen->aux_context;
747 struct si_context *sctx = (struct si_context *)ctx;
748 struct pipe_resource *buf =
749 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
750
751 if (!buf) {
752 puts("Buffer allocation failed.");
753 exit(1);
754 }
755
756 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
757
758 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
759 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
760 SI_COHERENCY_NONE, L2_BYPASS);
761 ctx->flush(ctx, NULL, 0);
762 puts("VM fault test: CP - done.");
763 }
764 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
765 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
766 ctx->flush(ctx, NULL, 0);
767 puts("VM fault test: SDMA - done.");
768 }
769 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
770 util_test_constant_buffer(ctx, buf);
771 puts("VM fault test: Shader - done.");
772 }
773 exit(0);
774 }
775
776 static void si_test_gds_memory_management(struct si_context *sctx,
777 unsigned alloc_size, unsigned alignment,
778 enum radeon_bo_domain domain)
779 {
780 struct radeon_winsys *ws = sctx->ws;
781 struct radeon_cmdbuf *cs[8];
782 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
783
784 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
785 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
786 NULL, NULL, false);
787 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
788 assert(gds_bo[i]);
789 }
790
791 for (unsigned iterations = 0; iterations < 20000; iterations++) {
792 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
793 /* This clears GDS with CP DMA.
794 *
795 * We don't care if GDS is present. Just add some packet
796 * to make the GPU busy for a moment.
797 */
798 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
799 SI_CPDMA_SKIP_BO_LIST_UPDATE |
800 SI_CPDMA_SKIP_CHECK_CS_SPACE |
801 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
802
803 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
804 RADEON_USAGE_READWRITE, 0);
805 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
806 }
807 }
808 exit(0);
809 }
810
811 static void si_disk_cache_create(struct si_screen *sscreen)
812 {
813 /* Don't use the cache if shader dumping is enabled. */
814 if (sscreen->debug_flags & DBG_ALL_SHADERS)
815 return;
816
817 struct mesa_sha1 ctx;
818 unsigned char sha1[20];
819 char cache_id[20 * 2 + 1];
820
821 _mesa_sha1_init(&ctx);
822
823 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
824 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
825 &ctx))
826 return;
827
828 _mesa_sha1_final(&ctx, sha1);
829 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
830
831 /* These flags affect shader compilation. */
832 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
833 DBG(SI_SCHED) | \
834 DBG(GISEL) | \
835 DBG(UNSAFE_MATH) | \
836 DBG(NIR))
837 uint64_t shader_debug_flags = sscreen->debug_flags &
838 ALL_FLAGS;
839
840 /* Add the high bits of 32-bit addresses, which affects
841 * how 32-bit addresses are expanded to 64 bits.
842 */
843 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
844 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
845
846 sscreen->disk_shader_cache =
847 disk_cache_create(sscreen->info.name,
848 cache_id,
849 shader_debug_flags);
850 }
851
852 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
853 unsigned max_threads)
854 {
855 struct si_screen *sscreen = (struct si_screen *)screen;
856
857 /* This function doesn't allow a greater number of threads than
858 * the queue had at its creation. */
859 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
860 max_threads);
861 /* Don't change the number of threads on the low priority queue. */
862 }
863
864 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
865 void *shader,
866 unsigned shader_type)
867 {
868 if (shader_type == PIPE_SHADER_COMPUTE) {
869 struct si_compute *cs = (struct si_compute*)shader;
870
871 return util_queue_fence_is_signalled(&cs->ready);
872 }
873 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
874
875 return util_queue_fence_is_signalled(&sel->ready);
876 }
877
878 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
879 const struct pipe_screen_config *config)
880 {
881 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
882 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
883
884 if (!sscreen) {
885 return NULL;
886 }
887
888 sscreen->ws = ws;
889 ws->query_info(ws, &sscreen->info);
890
891 if (sscreen->info.chip_class >= GFX9) {
892 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
893 } else {
894 ac_get_raster_config(&sscreen->info,
895 &sscreen->pa_sc_raster_config,
896 &sscreen->pa_sc_raster_config_1,
897 &sscreen->se_tile_repeat);
898 }
899
900 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
901 debug_options, 0);
902 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
903 debug_options, 0);
904
905 /* Set functions first. */
906 sscreen->b.context_create = si_pipe_create_context;
907 sscreen->b.destroy = si_destroy_screen;
908 sscreen->b.set_max_shader_compiler_threads =
909 si_set_max_shader_compiler_threads;
910 sscreen->b.is_parallel_shader_compilation_finished =
911 si_is_parallel_shader_compilation_finished;
912
913 si_init_screen_get_functions(sscreen);
914 si_init_screen_buffer_functions(sscreen);
915 si_init_screen_fence_functions(sscreen);
916 si_init_screen_state_functions(sscreen);
917 si_init_screen_texture_functions(sscreen);
918 si_init_screen_query_functions(sscreen);
919
920 /* Set these flags in debug_flags early, so that the shader cache takes
921 * them into account.
922 */
923 if (driQueryOptionb(config->options,
924 "glsl_correct_derivatives_after_discard"))
925 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
926 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
927 sscreen->debug_flags |= DBG(SI_SCHED);
928 if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
929 sscreen->debug_flags |= DBG(NIR);
930
931 if (sscreen->debug_flags & DBG(INFO))
932 ac_print_gpu_info(&sscreen->info);
933
934 slab_create_parent(&sscreen->pool_transfers,
935 sizeof(struct si_transfer), 64);
936
937 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
938 if (sscreen->force_aniso >= 0) {
939 printf("radeonsi: Forcing anisotropy filter to %ix\n",
940 /* round down to a power of two */
941 1 << util_logbase2(sscreen->force_aniso));
942 }
943
944 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
945 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
946
947 si_init_gs_info(sscreen);
948 if (!si_init_shader_cache(sscreen)) {
949 FREE(sscreen);
950 return NULL;
951 }
952
953 si_disk_cache_create(sscreen);
954
955 /* Determine the number of shader compiler threads. */
956 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
957
958 if (hw_threads >= 12) {
959 num_comp_hi_threads = hw_threads * 3 / 4;
960 num_comp_lo_threads = hw_threads / 3;
961 } else if (hw_threads >= 6) {
962 num_comp_hi_threads = hw_threads - 2;
963 num_comp_lo_threads = hw_threads / 2;
964 } else if (hw_threads >= 2) {
965 num_comp_hi_threads = hw_threads - 1;
966 num_comp_lo_threads = hw_threads / 2;
967 } else {
968 num_comp_hi_threads = 1;
969 num_comp_lo_threads = 1;
970 }
971
972 num_comp_hi_threads = MIN2(num_comp_hi_threads,
973 ARRAY_SIZE(sscreen->compiler));
974 num_comp_lo_threads = MIN2(num_comp_lo_threads,
975 ARRAY_SIZE(sscreen->compiler_lowp));
976
977 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
978 64, num_comp_hi_threads,
979 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
980 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
981 si_destroy_shader_cache(sscreen);
982 FREE(sscreen);
983 return NULL;
984 }
985
986 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
987 "shlo",
988 64, num_comp_lo_threads,
989 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
990 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
991 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
992 si_destroy_shader_cache(sscreen);
993 FREE(sscreen);
994 return NULL;
995 }
996
997 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
998 si_init_perfcounters(sscreen);
999
1000 /* Determine tessellation ring info. */
1001 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
1002 sscreen->info.family != CHIP_CARRIZO &&
1003 sscreen->info.family != CHIP_STONEY;
1004 /* This must be one less than the maximum number due to a hw limitation.
1005 * Various hardware bugs in SI, CIK, and GFX9 need this.
1006 */
1007 unsigned max_offchip_buffers_per_se;
1008
1009 /* Only certain chips can use the maximum value. */
1010 if (sscreen->info.family == CHIP_VEGA12 ||
1011 sscreen->info.family == CHIP_VEGA20)
1012 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1013 else
1014 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1015
1016 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1017 sscreen->info.max_se;
1018 unsigned offchip_granularity;
1019
1020 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1021 * around by setting 4K granularity.
1022 */
1023 if (sscreen->info.family == CHIP_HAWAII) {
1024 sscreen->tess_offchip_block_dw_size = 4096;
1025 offchip_granularity = V_03093C_X_4K_DWORDS;
1026 } else {
1027 sscreen->tess_offchip_block_dw_size = 8192;
1028 offchip_granularity = V_03093C_X_8K_DWORDS;
1029 }
1030
1031 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1032 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1033 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1034 sscreen->tess_offchip_block_dw_size * 4;
1035
1036 if (sscreen->info.chip_class >= CIK) {
1037 if (sscreen->info.chip_class >= VI)
1038 --max_offchip_buffers;
1039 sscreen->vgt_hs_offchip_param =
1040 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1041 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1042 } else {
1043 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1044 sscreen->vgt_hs_offchip_param =
1045 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1046 }
1047
1048 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1049 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1050 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
1051 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
1052 sscreen->info.drm_major == 3;
1053
1054 sscreen->has_distributed_tess =
1055 sscreen->info.chip_class >= VI &&
1056 sscreen->info.max_se >= 2;
1057
1058 sscreen->has_draw_indirect_multi =
1059 (sscreen->info.family >= CHIP_POLARIS10) ||
1060 (sscreen->info.chip_class == VI &&
1061 sscreen->info.pfp_fw_version >= 121 &&
1062 sscreen->info.me_fw_version >= 87) ||
1063 (sscreen->info.chip_class == CIK &&
1064 sscreen->info.pfp_fw_version >= 211 &&
1065 sscreen->info.me_fw_version >= 173) ||
1066 (sscreen->info.chip_class == SI &&
1067 sscreen->info.pfp_fw_version >= 79 &&
1068 sscreen->info.me_fw_version >= 142);
1069
1070 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1071 sscreen->info.max_se >= 2 &&
1072 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1073 sscreen->assume_no_z_fights =
1074 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1075 sscreen->commutative_blend_add =
1076 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1077 sscreen->clear_db_cache_before_clear =
1078 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1079 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1080 sscreen->info.family <= CHIP_POLARIS12) ||
1081 sscreen->info.family == CHIP_VEGA10 ||
1082 sscreen->info.family == CHIP_RAVEN;
1083 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1084 sscreen->info.family == CHIP_RAVEN;
1085 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1086
1087 /* Only enable primitive binning on APUs by default. */
1088 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1089 sscreen->info.family == CHIP_RAVEN2;
1090
1091 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1092 sscreen->info.family == CHIP_RAVEN2;
1093
1094 /* Process DPBB enable flags. */
1095 if (sscreen->debug_flags & DBG(DPBB)) {
1096 sscreen->dpbb_allowed = true;
1097 if (sscreen->debug_flags & DBG(DFSM))
1098 sscreen->dfsm_allowed = true;
1099 }
1100
1101 /* Process DPBB disable flags. */
1102 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1103 sscreen->dpbb_allowed = false;
1104 sscreen->dfsm_allowed = false;
1105 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1106 sscreen->dfsm_allowed = false;
1107 }
1108
1109 /* While it would be nice not to have this flag, we are constrained
1110 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1111 * on GFX9.
1112 */
1113 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1114
1115 /* Some chips have RB+ registers, but don't support RB+. Those must
1116 * always disable it.
1117 */
1118 if (sscreen->info.family == CHIP_STONEY ||
1119 sscreen->info.chip_class >= GFX9) {
1120 sscreen->has_rbplus = true;
1121
1122 sscreen->rbplus_allowed =
1123 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1124 (sscreen->info.family == CHIP_STONEY ||
1125 sscreen->info.family == CHIP_VEGA12 ||
1126 sscreen->info.family == CHIP_RAVEN ||
1127 sscreen->info.family == CHIP_RAVEN2);
1128 }
1129
1130 sscreen->dcc_msaa_allowed =
1131 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1132
1133 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1134
1135 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1136 sscreen->use_monolithic_shaders =
1137 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1138
1139 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1140 SI_CONTEXT_INV_VMEM_L1;
1141 if (sscreen->info.chip_class <= VI) {
1142 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1143 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1144 }
1145
1146 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1147 sscreen->debug_flags |= DBG_ALL_SHADERS;
1148
1149 /* Syntax:
1150 * EQAA=s,z,c
1151 * Example:
1152 * EQAA=8,4,2
1153
1154 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1155 * Constraints:
1156 * s >= z >= c (ignoring this only wastes memory)
1157 * s = [2..16]
1158 * z = [2..8]
1159 * c = [2..8]
1160 *
1161 * Only MSAA color and depth buffers are overriden.
1162 */
1163 if (sscreen->info.has_eqaa_surface_allocator) {
1164 const char *eqaa = debug_get_option("EQAA", NULL);
1165 unsigned s,z,f;
1166
1167 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1168 sscreen->eqaa_force_coverage_samples = s;
1169 sscreen->eqaa_force_z_samples = z;
1170 sscreen->eqaa_force_color_samples = f;
1171 }
1172 }
1173
1174 for (i = 0; i < num_comp_hi_threads; i++)
1175 si_init_compiler(sscreen, &sscreen->compiler[i]);
1176 for (i = 0; i < num_comp_lo_threads; i++)
1177 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1178
1179 /* Create the auxiliary context. This must be done last. */
1180 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1181
1182 if (sscreen->debug_flags & DBG(TEST_DMA))
1183 si_test_dma(sscreen);
1184
1185 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1186 si_test_dma_perf(sscreen);
1187 }
1188
1189 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1190 DBG(TEST_VMFAULT_SDMA) |
1191 DBG(TEST_VMFAULT_SHADER)))
1192 si_test_vmfault(sscreen);
1193
1194 if (sscreen->debug_flags & DBG(TEST_GDS))
1195 si_test_gds((struct si_context*)sscreen->aux_context);
1196
1197 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1198 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1199 32 * 1024, 4, RADEON_DOMAIN_GDS);
1200 }
1201 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1202 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1203 4, 1, RADEON_DOMAIN_OA);
1204 }
1205
1206 return &sscreen->b;
1207 }