src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_log.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_suballoc.h"
  34 #include "util/u_tests.h"
  35 #include "util/xmlconfig.h"
  36 #include "vl/vl_decoder.h"
  37 #include "../ddebug/dd_util.h"
  38
  39 static const struct debug_named_value debug_options[] = {
  40         /* Shader logging options: */
  41         { "vs", DBG(VS), "Print vertex shaders" },
  42         { "ps", DBG(PS), "Print pixel shaders" },
  43         { "gs", DBG(GS), "Print geometry shaders" },
  44         { "tcs", DBG(TCS), "Print tessellation control shaders" },
  45         { "tes", DBG(TES), "Print tessellation evaluation shaders" },
  46         { "cs", DBG(CS), "Print compute shaders" },
  47         { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
  48         { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
  49         { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
  50         { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
  51
  52         /* Shader compiler options the shader cache should be aware of: */
  53         { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
  54         { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
  55
  56         /* Shader compiler options (with no effect on the shader cache): */
  57         { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
  58         { "precompile", DBG(PRECOMPILE), "Compile one shader variant at shader creation." },
  59         { "nir", DBG(NIR), "Enable experimental NIR shaders" },
  60         { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
  61         { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
  62
  63         /* Information logging options: */
  64         { "info", DBG(INFO), "Print driver information" },
  65         { "tex", DBG(TEX), "Print texture info" },
  66         { "compute", DBG(COMPUTE), "Print compute info" },
  67         { "vm", DBG(VM), "Print virtual addresses when creating resources" },
  68
  69         /* Driver options: */
  70         { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
  71         { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
  72         { "nowc", DBG(NO_WC), "Disable GTT write combining" },
  73         { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
  74         { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
  75
  76         /* 3D engine options: */
  77         { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
  78         { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
  79         { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
  80         { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
  81         { "dpbb", DBG(DPBB), "Enable DPBB." },
  82         { "dfsm", DBG(DFSM), "Enable DFSM." },
  83         { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
  84         { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
  85         { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
  86         { "notiling", DBG(NO_TILING), "Disable tiling" },
  87         { "nodcc", DBG(NO_DCC), "Disable DCC." },
  88         { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
  89         { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
  90         { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
  91         { "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" },
  92
  93         /* Tests: */
  94         { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
  95         { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
  96         { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
  97         { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
  98
  99         DEBUG_NAMED_VALUE_END /* must be last */
 100 };
 101
 102 /*
 103  * pipe_context
 104  */
 105 static void si_destroy_context(struct pipe_context *context)
 106 {
 107         struct si_context *sctx = (struct si_context *)context;
 108         int i;
 109
 110         /* Unreference the framebuffer normally to disable related logic
 111          * properly.
 112          */
 113         struct pipe_framebuffer_state fb = {};
 114         if (context->set_framebuffer_state)
 115                 context->set_framebuffer_state(context, &fb);
 116
 117         si_release_all_descriptors(sctx);
 118
 119         pipe_resource_reference(&sctx->esgs_ring, NULL);
 120         pipe_resource_reference(&sctx->gsvs_ring, NULL);
 121         pipe_resource_reference(&sctx->tf_ring, NULL);
 122         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
 123         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
 124         r600_resource_reference(&sctx->border_color_buffer, NULL);
 125         free(sctx->border_color_table);
 126         r600_resource_reference(&sctx->scratch_buffer, NULL);
 127         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
 128         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
 129
 130         si_pm4_free_state(sctx, sctx->init_config, ~0);
 131         if (sctx->init_config_gs_rings)
 132                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
 133         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
 134                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
 135
 136         if (sctx->fixed_func_tcs_shader.cso)
 137                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
 138         if (sctx->custom_dsa_flush)
 139                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
 140         if (sctx->custom_blend_resolve)
 141                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
 142         if (sctx->custom_blend_fmask_decompress)
 143                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
 144         if (sctx->custom_blend_eliminate_fastclear)
 145                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
 146         if (sctx->custom_blend_dcc_decompress)
 147                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
 148         if (sctx->vs_blit_pos)
 149                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
 150         if (sctx->vs_blit_pos_layered)
 151                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
 152         if (sctx->vs_blit_color)
 153                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
 154         if (sctx->vs_blit_color_layered)
 155                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
 156         if (sctx->vs_blit_texcoord)
 157                 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
 158
 159         if (sctx->blitter)
 160                 util_blitter_destroy(sctx->blitter);
 161
 162         si_common_context_cleanup(&sctx->b);
 163
 164         LLVMDisposeTargetMachine(sctx->tm);
 165
 166         si_saved_cs_reference(&sctx->current_saved_cs, NULL);
 167
 168         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 169         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 170
 171         util_dynarray_fini(&sctx->resident_tex_handles);
 172         util_dynarray_fini(&sctx->resident_img_handles);
 173         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 174         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 175         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 176         FREE(sctx);
 177 }
 178
 179 static enum pipe_reset_status
 180 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 181 {
 182         struct si_context *sctx = (struct si_context *)ctx;
 183
 184         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 185 }
 186
 187 /* Apitrace profiling:
 188  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 189  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 190  *      and remember its number.
 191  *   3) In Mesa, enable queries and performance counters around that draw
 192  *      call and print the results.
 193  *   4) glretrace --benchmark --markers ..
 194  */
 195 static void si_emit_string_marker(struct pipe_context *ctx,
 196                                   const char *string, int len)
 197 {
 198         struct si_context *sctx = (struct si_context *)ctx;
 199
 200         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 201
 202         if (sctx->b.log)
 203                 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
 204 }
 205
 206 static LLVMTargetMachineRef
 207 si_create_llvm_target_machine(struct si_screen *sscreen)
 208 {
 209         enum ac_target_machine_options tm_options =
 210                 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
 211                 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
 212                 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
 213                 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
 214
 215         return ac_create_target_machine(sscreen->info.family, tm_options);
 216 }
 217
 218 static void si_set_debug_callback(struct pipe_context *ctx,
 219                                   const struct pipe_debug_callback *cb)
 220 {
 221         struct si_context *sctx = (struct si_context *)ctx;
 222         struct si_screen *screen = sctx->screen;
 223
 224         util_queue_finish(&screen->shader_compiler_queue);
 225         util_queue_finish(&screen->shader_compiler_queue_low_priority);
 226
 227         if (cb)
 228                 sctx->debug = *cb;
 229         else
 230                 memset(&sctx->debug, 0, sizeof(sctx->debug));
 231 }
 232
 233 static void si_set_log_context(struct pipe_context *ctx,
 234                                struct u_log_context *log)
 235 {
 236         struct si_context *sctx = (struct si_context *)ctx;
 237         sctx->b.log = log;
 238
 239         if (log)
 240                 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
 241 }
 242
 243 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 244                                               unsigned flags)
 245 {
 246         struct si_context *sctx = CALLOC_STRUCT(si_context);
 247         struct si_screen* sscreen = (struct si_screen *)screen;
 248         struct radeon_winsys *ws = sscreen->ws;
 249         int shader, i;
 250
 251         if (!sctx)
 252                 return NULL;
 253
 254         if (flags & PIPE_CONTEXT_DEBUG)
 255                 sscreen->record_llvm_ir = true; /* racy but not critical */
 256
 257         sctx->b.b.screen = screen; /* this must be set first */
 258         sctx->b.b.priv = NULL;
 259         sctx->b.b.destroy = si_destroy_context;
 260         sctx->b.b.emit_string_marker = si_emit_string_marker;
 261         sctx->b.b.set_debug_callback = si_set_debug_callback;
 262         sctx->b.b.set_log_context = si_set_log_context;
 263         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 264         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 265         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 266
 267         if (!si_common_context_init(&sctx->b, sscreen, flags))
 268                 goto fail;
 269
 270         if (sscreen->info.drm_major == 3)
 271                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 272
 273         si_init_buffer_functions(sctx);
 274         si_init_clear_functions(sctx);
 275         si_init_blit_functions(sctx);
 276         si_init_compute_functions(sctx);
 277         si_init_cp_dma_functions(sctx);
 278         si_init_debug_functions(sctx);
 279         si_init_msaa_functions(sctx);
 280         si_init_streamout_functions(sctx);
 281
 282         if (sscreen->info.has_hw_decode) {
 283                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 284                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 285         } else {
 286                 sctx->b.b.create_video_codec = vl_create_decoder;
 287                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 288         }
 289
 290         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 291                                        si_context_gfx_flush, sctx);
 292         sctx->b.gfx.flush = si_context_gfx_flush;
 293
 294         /* Border colors. */
 295         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 296                                           sizeof(*sctx->border_color_table));
 297         if (!sctx->border_color_table)
 298                 goto fail;
 299
 300         sctx->border_color_buffer = (struct r600_resource*)
 301                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 302                                    SI_MAX_BORDER_COLORS *
 303                                    sizeof(*sctx->border_color_table));
 304         if (!sctx->border_color_buffer)
 305                 goto fail;
 306
 307         sctx->border_color_map =
 308                 ws->buffer_map(sctx->border_color_buffer->buf,
 309                                NULL, PIPE_TRANSFER_WRITE);
 310         if (!sctx->border_color_map)
 311                 goto fail;
 312
 313         si_init_all_descriptors(sctx);
 314         si_init_fence_functions(sctx);
 315         si_init_state_functions(sctx);
 316         si_init_shader_functions(sctx);
 317         si_init_viewport_functions(sctx);
 318         si_init_ia_multi_vgt_param_table(sctx);
 319
 320         if (sctx->b.chip_class >= CIK)
 321                 cik_init_sdma_functions(sctx);
 322         else
 323                 si_init_dma_functions(sctx);
 324
 325         if (sscreen->debug_flags & DBG(FORCE_DMA))
 326                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 327
 328         sctx->blitter = util_blitter_create(&sctx->b.b);
 329         if (sctx->blitter == NULL)
 330                 goto fail;
 331         sctx->blitter->draw_rectangle = si_draw_rectangle;
 332         sctx->blitter->skip_viewport_restore = true;
 333
 334         sctx->sample_mask.sample_mask = 0xffff;
 335
 336         /* these must be last */
 337         si_begin_new_cs(sctx);
 338
 339         if (sctx->b.chip_class >= GFX9) {
 340                 sctx->wait_mem_scratch = (struct r600_resource*)
 341                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 342                 if (!sctx->wait_mem_scratch)
 343                         goto fail;
 344
 345                 /* Initialize the memory. */
 346                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 347                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 348                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 349                             S_370_WR_CONFIRM(1) |
 350                             S_370_ENGINE_SEL(V_370_ME));
 351                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 352                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 353                 radeon_emit(cs, sctx->wait_mem_number);
 354         }
 355
 356         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 357          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 358         if (sctx->b.chip_class == CIK) {
 359                 sctx->null_const_buf.buffer =
 360                         si_aligned_buffer_create(screen,
 361                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 362                                                    PIPE_USAGE_DEFAULT, 16,
 363                                                    sctx->screen->info.tcc_cache_line_size);
 364                 if (!sctx->null_const_buf.buffer)
 365                         goto fail;
 366                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 367
 368                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 369                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 370                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 371                                                               &sctx->null_const_buf);
 372                         }
 373                 }
 374
 375                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 376                                  &sctx->null_const_buf);
 377                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 378                                  &sctx->null_const_buf);
 379                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 380                                  &sctx->null_const_buf);
 381                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 382                                  &sctx->null_const_buf);
 383                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 384                                  &sctx->null_const_buf);
 385
 386                 /* Clear the NULL constant buffer, because loads should return zeros. */
 387                 si_clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 388                                 sctx->null_const_buf.buffer->width0, 0,
 389                                 R600_COHERENCY_SHADER);
 390         }
 391
 392         uint64_t max_threads_per_block;
 393         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 394                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 395                                   &max_threads_per_block);
 396
 397         /* The maximum number of scratch waves. Scratch space isn't divided
 398          * evenly between CUs. The number is only a function of the number of CUs.
 399          * We can decrease the constant to decrease the scratch buffer size.
 400          *
 401          * sctx->scratch_waves must be >= the maximum posible size of
 402          * 1 threadgroup, so that the hw doesn't hang from being unable
 403          * to start any.
 404          *
 405          * The recommended value is 4 per CU at most. Higher numbers don't
 406          * bring much benefit, but they still occupy chip resources (think
 407          * async compute). I've seen ~2% performance difference between 4 and 32.
 408          */
 409         sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
 410                                    max_threads_per_block / 64);
 411
 412         sctx->tm = si_create_llvm_target_machine(sscreen);
 413
 414         /* Bindless handles. */
 415         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 416                                                     _mesa_key_pointer_equal);
 417         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 418                                                     _mesa_key_pointer_equal);
 419
 420         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 421         util_dynarray_init(&sctx->resident_img_handles, NULL);
 422         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 423         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 424         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 425
 426         return &sctx->b.b;
 427 fail:
 428         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 429         si_destroy_context(&sctx->b.b);
 430         return NULL;
 431 }
 432
 433 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 434                                                    void *priv, unsigned flags)
 435 {
 436         struct si_screen *sscreen = (struct si_screen *)screen;
 437         struct pipe_context *ctx;
 438
 439         if (sscreen->debug_flags & DBG(CHECK_VM))
 440                 flags |= PIPE_CONTEXT_DEBUG;
 441
 442         ctx = si_create_context(screen, flags);
 443
 444         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 445                 return ctx;
 446
 447         /* Clover (compute-only) is unsupported. */
 448         if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
 449                 return ctx;
 450
 451         /* When shaders are logged to stderr, asynchronous compilation is
 452          * disabled too. */
 453         if (sscreen->debug_flags & DBG_ALL_SHADERS)
 454                 return ctx;
 455
 456         /* Use asynchronous flushes only on amdgpu, since the radeon
 457          * implementation for fence_server_sync is incomplete. */
 458         return threaded_context_create(ctx, &sscreen->pool_transfers,
 459                                        si_replace_buffer_storage,
 460                                        sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
 461                                        &((struct si_context*)ctx)->b.tc);
 462 }
 463
 464 /*
 465  * pipe_screen
 466  */
 467
 468 static void si_destroy_screen(struct pipe_screen* pscreen)
 469 {
 470         struct si_screen *sscreen = (struct si_screen *)pscreen;
 471         struct si_shader_part *parts[] = {
 472                 sscreen->vs_prologs,
 473                 sscreen->tcs_epilogs,
 474                 sscreen->gs_prologs,
 475                 sscreen->ps_prologs,
 476                 sscreen->ps_epilogs
 477         };
 478         unsigned i;
 479
 480         if (!sscreen->ws->unref(sscreen->ws))
 481                 return;
 482
 483         util_queue_destroy(&sscreen->shader_compiler_queue);
 484         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 485
 486         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 487                 if (sscreen->tm[i])
 488                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 489
 490         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 491                 if (sscreen->tm_low_priority[i])
 492                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 493
 494         /* Free shader parts. */
 495         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 496                 while (parts[i]) {
 497                         struct si_shader_part *part = parts[i];
 498
 499                         parts[i] = part->next;
 500                         ac_shader_binary_clean(&part->binary);
 501                         FREE(part);
 502                 }
 503         }
 504         mtx_destroy(&sscreen->shader_parts_mutex);
 505         si_destroy_shader_cache(sscreen);
 506
 507         si_perfcounters_destroy(sscreen);
 508         si_gpu_load_kill_thread(sscreen);
 509
 510         mtx_destroy(&sscreen->gpu_load_mutex);
 511         mtx_destroy(&sscreen->aux_context_lock);
 512         sscreen->aux_context->destroy(sscreen->aux_context);
 513
 514         slab_destroy_parent(&sscreen->pool_transfers);
 515
 516         disk_cache_destroy(sscreen->disk_shader_cache);
 517         sscreen->ws->destroy(sscreen->ws);
 518         FREE(sscreen);
 519 }
 520
 521 static bool si_init_gs_info(struct si_screen *sscreen)
 522 {
 523         /* gs_table_depth is not used by GFX9 */
 524         if (sscreen->info.chip_class >= GFX9)
 525                 return true;
 526
 527         switch (sscreen->info.family) {
 528         case CHIP_OLAND:
 529         case CHIP_HAINAN:
 530         case CHIP_KAVERI:
 531         case CHIP_KABINI:
 532         case CHIP_MULLINS:
 533         case CHIP_ICELAND:
 534         case CHIP_CARRIZO:
 535         case CHIP_STONEY:
 536                 sscreen->gs_table_depth = 16;
 537                 return true;
 538         case CHIP_TAHITI:
 539         case CHIP_PITCAIRN:
 540         case CHIP_VERDE:
 541         case CHIP_BONAIRE:
 542         case CHIP_HAWAII:
 543         case CHIP_TONGA:
 544         case CHIP_FIJI:
 545         case CHIP_POLARIS10:
 546         case CHIP_POLARIS11:
 547         case CHIP_POLARIS12:
 548                 sscreen->gs_table_depth = 32;
 549                 return true;
 550         default:
 551                 return false;
 552         }
 553 }
 554
 555 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 556 {
 557         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 558         unsigned i;
 559
 560         if (!family)
 561                 return;
 562
 563         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 564                 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
 565                         /* Override family and chip_class. */
 566                         sscreen->info.family = i;
 567
 568                         if (i >= CHIP_VEGA10)
 569                                 sscreen->info.chip_class = GFX9;
 570                         else if (i >= CHIP_TONGA)
 571                                 sscreen->info.chip_class = VI;
 572                         else if (i >= CHIP_BONAIRE)
 573                                 sscreen->info.chip_class = CIK;
 574                         else
 575                                 sscreen->info.chip_class = SI;
 576
 577                         /* Don't submit any IBs. */
 578                         setenv("RADEON_NOOP", "1", 1);
 579                         return;
 580                 }
 581         }
 582
 583         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 584         exit(1);
 585 }
 586
 587 static void si_test_vmfault(struct si_screen *sscreen)
 588 {
 589         struct pipe_context *ctx = sscreen->aux_context;
 590         struct si_context *sctx = (struct si_context *)ctx;
 591         struct pipe_resource *buf =
 592                 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
 593
 594         if (!buf) {
 595                 puts("Buffer allocation failed.");
 596                 exit(1);
 597         }
 598
 599         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 600
 601         if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
 602                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 603                 ctx->flush(ctx, NULL, 0);
 604                 puts("VM fault test: CP - done.");
 605         }
 606         if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
 607                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 608                 ctx->flush(ctx, NULL, 0);
 609                 puts("VM fault test: SDMA - done.");
 610         }
 611         if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
 612                 util_test_constant_buffer(ctx, buf);
 613                 puts("VM fault test: Shader - done.");
 614         }
 615         exit(0);
 616 }
 617
 618 static void si_disk_cache_create(struct si_screen *sscreen)
 619 {
 620         /* Don't use the cache if shader dumping is enabled. */
 621         if (sscreen->debug_flags & DBG_ALL_SHADERS)
 622                 return;
 623
 624         /* TODO: remove this once gallium supports a nir cache */
 625         if (sscreen->debug_flags & DBG(NIR))
 626                 return;
 627
 628         uint32_t mesa_timestamp;
 629         if (disk_cache_get_function_timestamp(si_disk_cache_create,
 630                                               &mesa_timestamp)) {
 631                 char *timestamp_str;
 632                 int res = -1;
 633                 uint32_t llvm_timestamp;
 634
 635                 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
 636                                                       &llvm_timestamp)) {
 637                         res = asprintf(&timestamp_str, "%u_%u",
 638                                        mesa_timestamp, llvm_timestamp);
 639                 }
 640
 641                 if (res != -1) {
 642                         /* These flags affect shader compilation. */
 643                         uint64_t shader_debug_flags =
 644                                 sscreen->debug_flags &
 645                                 (DBG(FS_CORRECT_DERIVS_AFTER_KILL) |
 646                                  DBG(SI_SCHED) |
 647                                  DBG(UNSAFE_MATH));
 648
 649                         sscreen->disk_shader_cache =
 650                                 disk_cache_create(si_get_family_name(sscreen),
 651                                                   timestamp_str,
 652                                                   shader_debug_flags);
 653                         free(timestamp_str);
 654                 }
 655         }
 656 }
 657
 658 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 659                                            const struct pipe_screen_config *config)
 660 {
 661         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 662         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 663
 664         if (!sscreen) {
 665                 return NULL;
 666         }
 667
 668         sscreen->ws = ws;
 669         ws->query_info(ws, &sscreen->info);
 670
 671         sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
 672                                                         debug_options, 0);
 673
 674         /* Set functions first. */
 675         sscreen->b.context_create = si_pipe_create_context;
 676         sscreen->b.destroy = si_destroy_screen;
 677
 678         si_init_screen_get_functions(sscreen);
 679         si_init_screen_buffer_functions(sscreen);
 680         si_init_screen_fence_functions(sscreen);
 681         si_init_screen_state_functions(sscreen);
 682         si_init_screen_texture_functions(sscreen);
 683         si_init_screen_query_functions(sscreen);
 684
 685         /* Set these flags in debug_flags early, so that the shader cache takes
 686          * them into account.
 687          */
 688         if (driQueryOptionb(config->options,
 689                             "glsl_correct_derivatives_after_discard"))
 690                 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
 691         if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
 692                 sscreen->debug_flags |= DBG(SI_SCHED);
 693
 694
 695         if (sscreen->debug_flags & DBG(INFO))
 696                 ac_print_gpu_info(&sscreen->info);
 697
 698         slab_create_parent(&sscreen->pool_transfers,
 699                            sizeof(struct r600_transfer), 64);
 700
 701         sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
 702         if (sscreen->force_aniso >= 0) {
 703                 printf("radeonsi: Forcing anisotropy filter to %ix\n",
 704                        /* round down to a power of two */
 705                        1 << util_logbase2(sscreen->force_aniso));
 706         }
 707
 708         (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
 709         (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
 710
 711         if (!si_init_gs_info(sscreen) ||
 712             !si_init_shader_cache(sscreen)) {
 713                 FREE(sscreen);
 714                 return NULL;
 715         }
 716
 717         si_disk_cache_create(sscreen);
 718
 719         /* Only enable as many threads as we have target machines, but at most
 720          * the number of CPUs - 1 if there is more than one.
 721          */
 722         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
 723         num_threads = MAX2(1, num_threads - 1);
 724         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
 725         num_compiler_threads_lowprio =
 726                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
 727
 728         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 729                              32, num_compiler_threads,
 730                              UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 731                 si_destroy_shader_cache(sscreen);
 732                 FREE(sscreen);
 733                 return NULL;
 734         }
 735
 736         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
 737                              "si_shader_low",
 738                              32, num_compiler_threads_lowprio,
 739                              UTIL_QUEUE_INIT_RESIZE_IF_FULL |
 740                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
 741                si_destroy_shader_cache(sscreen);
 742                FREE(sscreen);
 743                return NULL;
 744         }
 745
 746         si_handle_env_var_force_family(sscreen);
 747
 748         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 749                 si_init_perfcounters(sscreen);
 750
 751         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 752          * around by setting 4K granularity.
 753          */
 754         sscreen->tess_offchip_block_dw_size =
 755                 sscreen->info.family == CHIP_HAWAII ? 4096 : 8192;
 756
 757         /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
 758          * on SI. */
 759         sscreen->has_clear_state = sscreen->info.chip_class >= CIK;
 760
 761         sscreen->has_distributed_tess =
 762                 sscreen->info.chip_class >= VI &&
 763                 sscreen->info.max_se >= 2;
 764
 765         sscreen->has_draw_indirect_multi =
 766                 (sscreen->info.family >= CHIP_POLARIS10) ||
 767                 (sscreen->info.chip_class == VI &&
 768                  sscreen->info.pfp_fw_version >= 121 &&
 769                  sscreen->info.me_fw_version >= 87) ||
 770                 (sscreen->info.chip_class == CIK &&
 771                  sscreen->info.pfp_fw_version >= 211 &&
 772                  sscreen->info.me_fw_version >= 173) ||
 773                 (sscreen->info.chip_class == SI &&
 774                  sscreen->info.pfp_fw_version >= 79 &&
 775                  sscreen->info.me_fw_version >= 142);
 776
 777         sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
 778                                          sscreen->info.max_se >= 2 &&
 779                                          !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
 780         sscreen->assume_no_z_fights =
 781                 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
 782         sscreen->commutative_blend_add =
 783                 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
 784         sscreen->clear_db_cache_before_clear =
 785                 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
 786         sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
 787                                             sscreen->info.family <= CHIP_POLARIS12) ||
 788                                            sscreen->info.family == CHIP_VEGA10 ||
 789                                            sscreen->info.family == CHIP_RAVEN;
 790         sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
 791                                         sscreen->info.family == CHIP_RAVEN;
 792
 793         if (sscreen->debug_flags & DBG(DPBB)) {
 794                 sscreen->dpbb_allowed = true;
 795         } else {
 796                 /* Only enable primitive binning on Raven by default. */
 797                 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
 798                                         !(sscreen->debug_flags & DBG(NO_DPBB));
 799         }
 800
 801         if (sscreen->debug_flags & DBG(DFSM)) {
 802                 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
 803         } else {
 804                 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
 805                                         !(sscreen->debug_flags & DBG(NO_DFSM));
 806         }
 807
 808         /* While it would be nice not to have this flag, we are constrained
 809          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 810          * on GFX9.
 811          */
 812         sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
 813
 814         /* Some chips have RB+ registers, but don't support RB+. Those must
 815          * always disable it.
 816          */
 817         if (sscreen->info.family == CHIP_STONEY ||
 818             sscreen->info.chip_class >= GFX9) {
 819                 sscreen->has_rbplus = true;
 820
 821                 sscreen->rbplus_allowed =
 822                         !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
 823                         (sscreen->info.family == CHIP_STONEY ||
 824                          sscreen->info.family == CHIP_RAVEN);
 825         }
 826
 827         sscreen->dcc_msaa_allowed =
 828                 !(sscreen->debug_flags & DBG(NO_DCC_MSAA)) &&
 829                 (sscreen->debug_flags & DBG(DCC_MSAA) ||
 830                  sscreen->info.chip_class == VI);
 831
 832         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
 833         sscreen->use_monolithic_shaders =
 834                 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
 835
 836         sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 837                                             SI_CONTEXT_INV_VMEM_L1;
 838         if (sscreen->info.chip_class <= VI) {
 839                 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
 840                 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 841         }
 842
 843         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 844                 sscreen->debug_flags |= DBG_ALL_SHADERS;
 845
 846         for (i = 0; i < num_compiler_threads; i++)
 847                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 848         for (i = 0; i < num_compiler_threads_lowprio; i++)
 849                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
 850
 851         /* Create the auxiliary context. This must be done last. */
 852         sscreen->aux_context = si_create_context(&sscreen->b, 0);
 853
 854         if (sscreen->debug_flags & DBG(TEST_DMA))
 855                 si_test_dma(sscreen);
 856
 857         if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
 858                                       DBG(TEST_VMFAULT_SDMA) |
 859                                       DBG(TEST_VMFAULT_SHADER)))
 860                 si_test_vmfault(sscreen);
 861
 862         return &sscreen->b;
 863 }