2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 #include <llvm-c/Transforms/IPO.h>
45 #include <llvm-c/Transforms/Scalar.h>
46 #if HAVE_LLVM >= 0x0700
47 #include <llvm-c/Transforms/Utils.h>
50 static const struct debug_named_value debug_options
[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS
), "Print vertex shaders" },
53 { "ps", DBG(PS
), "Print pixel shaders" },
54 { "gs", DBG(GS
), "Print geometry shaders" },
55 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
56 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS
), "Print compute shaders" },
58 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
59 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
60 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
63 /* Shader compiler options the shader cache should be aware of: */
64 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
65 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
69 { "nir", DBG(NIR
), "Enable experimental NIR shaders" },
70 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
71 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
73 /* Information logging options: */
74 { "info", DBG(INFO
), "Print driver information" },
75 { "tex", DBG(TEX
), "Print texture info" },
76 { "compute", DBG(COMPUTE
), "Print compute info" },
77 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
80 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
81 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
82 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
83 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
84 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
85 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
87 /* 3D engine options: */
88 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
89 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
90 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
91 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
92 { "dpbb", DBG(DPBB
), "Enable DPBB." },
93 { "dfsm", DBG(DFSM
), "Enable DFSM." },
94 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
95 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
96 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
97 { "notiling", DBG(NO_TILING
), "Disable tiling" },
98 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
99 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
100 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
101 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
102 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
105 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
106 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
107 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
108 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
110 DEBUG_NAMED_VALUE_END
/* must be last */
113 static void si_init_compiler(struct si_screen
*sscreen
,
114 struct si_compiler
*compiler
)
116 enum ac_target_machine_options tm_options
=
117 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
118 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
119 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
120 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0);
123 compiler
->tm
= ac_create_target_machine(sscreen
->info
.family
,
124 tm_options
, &triple
);
128 compiler
->target_library_info
=
129 gallivm_create_target_library_info(triple
);
130 if (!compiler
->target_library_info
)
133 compiler
->passmgr
= LLVMCreatePassManager();
134 if (!compiler
->passmgr
)
137 LLVMAddTargetLibraryInfo(compiler
->target_library_info
,
140 /* Add LLVM passes into the pass manager. */
141 if (sscreen
->debug_flags
& DBG(CHECK_IR
))
142 LLVMAddVerifierPass(compiler
->passmgr
);
144 LLVMAddAlwaysInlinerPass(compiler
->passmgr
);
145 /* This pass should eliminate all the load and store instructions. */
146 LLVMAddPromoteMemoryToRegisterPass(compiler
->passmgr
);
147 LLVMAddScalarReplAggregatesPass(compiler
->passmgr
);
148 LLVMAddLICMPass(compiler
->passmgr
);
149 LLVMAddAggressiveDCEPass(compiler
->passmgr
);
150 LLVMAddCFGSimplificationPass(compiler
->passmgr
);
151 /* This is recommended by the instruction combining pass. */
152 LLVMAddEarlyCSEMemSSAPass(compiler
->passmgr
);
153 LLVMAddInstructionCombiningPass(compiler
->passmgr
);
156 static void si_destroy_compiler(struct si_compiler
*compiler
)
158 if (compiler
->passmgr
)
159 LLVMDisposePassManager(compiler
->passmgr
);
160 #if HAVE_LLVM >= 0x0700
161 /* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
162 if (compiler
->target_library_info
)
163 gallivm_dispose_target_library_info(compiler
->target_library_info
);
166 LLVMDisposeTargetMachine(compiler
->tm
);
172 static void si_destroy_context(struct pipe_context
*context
)
174 struct si_context
*sctx
= (struct si_context
*)context
;
177 /* Unreference the framebuffer normally to disable related logic
180 struct pipe_framebuffer_state fb
= {};
181 if (context
->set_framebuffer_state
)
182 context
->set_framebuffer_state(context
, &fb
);
184 si_release_all_descriptors(sctx
);
186 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
187 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
188 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
189 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
190 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
191 free(sctx
->border_color_table
);
192 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
193 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
194 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
196 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
197 if (sctx
->init_config_gs_rings
)
198 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
199 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
200 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
202 if (sctx
->fixed_func_tcs_shader
.cso
)
203 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
204 if (sctx
->custom_dsa_flush
)
205 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
206 if (sctx
->custom_blend_resolve
)
207 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
208 if (sctx
->custom_blend_fmask_decompress
)
209 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
210 if (sctx
->custom_blend_eliminate_fastclear
)
211 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
212 if (sctx
->custom_blend_dcc_decompress
)
213 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
214 if (sctx
->vs_blit_pos
)
215 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
216 if (sctx
->vs_blit_pos_layered
)
217 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
218 if (sctx
->vs_blit_color
)
219 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
220 if (sctx
->vs_blit_color_layered
)
221 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
222 if (sctx
->vs_blit_texcoord
)
223 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
226 util_blitter_destroy(sctx
->blitter
);
228 /* Release DCC stats. */
229 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
230 assert(!sctx
->dcc_stats
[i
].query_active
);
232 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
233 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
234 sctx
->b
.destroy_query(&sctx
->b
,
235 sctx
->dcc_stats
[i
].ps_stats
[j
]);
237 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
240 if (sctx
->query_result_shader
)
241 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
244 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
246 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
248 sctx
->ws
->ctx_destroy(sctx
->ctx
);
250 if (sctx
->b
.stream_uploader
)
251 u_upload_destroy(sctx
->b
.stream_uploader
);
252 if (sctx
->b
.const_uploader
)
253 u_upload_destroy(sctx
->b
.const_uploader
);
254 if (sctx
->cached_gtt_allocator
)
255 u_upload_destroy(sctx
->cached_gtt_allocator
);
257 slab_destroy_child(&sctx
->pool_transfers
);
258 slab_destroy_child(&sctx
->pool_transfers_unsync
);
260 if (sctx
->allocator_zeroed_memory
)
261 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
263 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
264 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
265 r600_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
267 si_destroy_compiler(&sctx
->compiler
);
269 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
271 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
272 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
274 util_dynarray_fini(&sctx
->resident_tex_handles
);
275 util_dynarray_fini(&sctx
->resident_img_handles
);
276 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
277 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
278 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
282 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
284 struct si_context
*sctx
= (struct si_context
*)ctx
;
286 if (sctx
->screen
->info
.has_gpu_reset_status_query
)
287 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
289 if (sctx
->screen
->info
.has_gpu_reset_counter_query
) {
290 unsigned latest
= sctx
->ws
->query_value(sctx
->ws
,
291 RADEON_GPU_RESET_COUNTER
);
293 if (sctx
->gpu_reset_counter
== latest
)
294 return PIPE_NO_RESET
;
296 sctx
->gpu_reset_counter
= latest
;
297 return PIPE_UNKNOWN_CONTEXT_RESET
;
300 return PIPE_NO_RESET
;
303 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
304 const struct pipe_device_reset_callback
*cb
)
306 struct si_context
*sctx
= (struct si_context
*)ctx
;
309 sctx
->device_reset_callback
= *cb
;
311 memset(&sctx
->device_reset_callback
, 0,
312 sizeof(sctx
->device_reset_callback
));
315 bool si_check_device_reset(struct si_context
*sctx
)
317 enum pipe_reset_status status
;
319 if (!sctx
->device_reset_callback
.reset
)
322 if (!sctx
->b
.get_device_reset_status
)
325 status
= sctx
->b
.get_device_reset_status(&sctx
->b
);
326 if (status
== PIPE_NO_RESET
)
329 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
333 /* Apitrace profiling:
334 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
335 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
336 * and remember its number.
337 * 3) In Mesa, enable queries and performance counters around that draw
338 * call and print the results.
339 * 4) glretrace --benchmark --markers ..
341 static void si_emit_string_marker(struct pipe_context
*ctx
,
342 const char *string
, int len
)
344 struct si_context
*sctx
= (struct si_context
*)ctx
;
346 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
349 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
352 static void si_set_debug_callback(struct pipe_context
*ctx
,
353 const struct pipe_debug_callback
*cb
)
355 struct si_context
*sctx
= (struct si_context
*)ctx
;
356 struct si_screen
*screen
= sctx
->screen
;
358 util_queue_finish(&screen
->shader_compiler_queue
);
359 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
364 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
367 static void si_set_log_context(struct pipe_context
*ctx
,
368 struct u_log_context
*log
)
370 struct si_context
*sctx
= (struct si_context
*)ctx
;
374 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
377 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
380 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
381 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
382 struct radeon_winsys
*ws
= sscreen
->ws
;
388 if (flags
& PIPE_CONTEXT_DEBUG
)
389 sscreen
->record_llvm_ir
= true; /* racy but not critical */
391 sctx
->b
.screen
= screen
; /* this must be set first */
393 sctx
->b
.destroy
= si_destroy_context
;
394 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
395 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
396 sctx
->b
.set_log_context
= si_set_log_context
;
397 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
398 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
400 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
401 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
403 sctx
->ws
= sscreen
->ws
;
404 sctx
->family
= sscreen
->info
.family
;
405 sctx
->chip_class
= sscreen
->info
.chip_class
;
407 if (sscreen
->info
.has_gpu_reset_counter_query
) {
408 sctx
->gpu_reset_counter
=
409 sctx
->ws
->query_value(sctx
->ws
, RADEON_GPU_RESET_COUNTER
);
412 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
413 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
415 si_init_context_texture_functions(sctx
);
416 si_init_query_functions(sctx
);
418 if (sctx
->chip_class
== CIK
||
419 sctx
->chip_class
== VI
||
420 sctx
->chip_class
== GFX9
) {
421 sctx
->eop_bug_scratch
= r600_resource(
422 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
423 16 * sscreen
->info
.num_render_backends
));
424 if (!sctx
->eop_bug_scratch
)
428 sctx
->allocator_zeroed_memory
=
429 u_suballocator_create(&sctx
->b
, sscreen
->info
.gart_page_size
,
430 0, PIPE_USAGE_DEFAULT
, 0, true);
431 if (!sctx
->allocator_zeroed_memory
)
434 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
435 0, PIPE_USAGE_STREAM
,
436 SI_RESOURCE_FLAG_READ_ONLY
);
437 if (!sctx
->b
.stream_uploader
)
440 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 128 * 1024,
441 0, PIPE_USAGE_DEFAULT
,
442 SI_RESOURCE_FLAG_32BIT
|
443 (sscreen
->cpdma_prefetch_writes_memory
?
444 0 : SI_RESOURCE_FLAG_READ_ONLY
));
445 if (!sctx
->b
.const_uploader
)
448 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
449 0, PIPE_USAGE_STAGING
, 0);
450 if (!sctx
->cached_gtt_allocator
)
453 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
457 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
458 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
459 (void*)si_flush_dma_cs
,
463 si_init_buffer_functions(sctx
);
464 si_init_clear_functions(sctx
);
465 si_init_blit_functions(sctx
);
466 si_init_compute_functions(sctx
);
467 si_init_cp_dma_functions(sctx
);
468 si_init_debug_functions(sctx
);
469 si_init_msaa_functions(sctx
);
470 si_init_streamout_functions(sctx
);
472 if (sscreen
->info
.has_hw_decode
) {
473 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
474 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
476 sctx
->b
.create_video_codec
= vl_create_decoder
;
477 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
480 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, RING_GFX
,
481 (void*)si_flush_gfx_cs
, sctx
);
484 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
485 sizeof(*sctx
->border_color_table
));
486 if (!sctx
->border_color_table
)
489 sctx
->border_color_buffer
= r600_resource(
490 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
491 SI_MAX_BORDER_COLORS
*
492 sizeof(*sctx
->border_color_table
)));
493 if (!sctx
->border_color_buffer
)
496 sctx
->border_color_map
=
497 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
498 NULL
, PIPE_TRANSFER_WRITE
);
499 if (!sctx
->border_color_map
)
502 si_init_all_descriptors(sctx
);
503 si_init_fence_functions(sctx
);
504 si_init_state_functions(sctx
);
505 si_init_shader_functions(sctx
);
506 si_init_viewport_functions(sctx
);
507 si_init_ia_multi_vgt_param_table(sctx
);
509 if (sctx
->chip_class
>= CIK
)
510 cik_init_sdma_functions(sctx
);
512 si_init_dma_functions(sctx
);
514 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
515 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
517 sctx
->blitter
= util_blitter_create(&sctx
->b
);
518 if (sctx
->blitter
== NULL
)
520 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
521 sctx
->blitter
->skip_viewport_restore
= true;
523 sctx
->sample_mask
= 0xffff;
525 if (sctx
->chip_class
>= GFX9
) {
526 sctx
->wait_mem_scratch
= r600_resource(
527 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4));
528 if (!sctx
->wait_mem_scratch
)
531 /* Initialize the memory. */
532 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
533 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
534 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
535 S_370_WR_CONFIRM(1) |
536 S_370_ENGINE_SEL(V_370_ME
));
537 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
538 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
539 radeon_emit(cs
, sctx
->wait_mem_number
);
540 radeon_add_to_buffer_list(sctx
, cs
, sctx
->wait_mem_scratch
,
541 RADEON_USAGE_WRITE
, RADEON_PRIO_FENCE
);
544 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
545 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
546 if (sctx
->chip_class
== CIK
) {
547 sctx
->null_const_buf
.buffer
=
548 pipe_aligned_buffer_create(screen
,
549 SI_RESOURCE_FLAG_32BIT
,
550 PIPE_USAGE_DEFAULT
, 16,
551 sctx
->screen
->info
.tcc_cache_line_size
);
552 if (!sctx
->null_const_buf
.buffer
)
554 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
556 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
557 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
558 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
559 &sctx
->null_const_buf
);
563 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
564 &sctx
->null_const_buf
);
565 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
566 &sctx
->null_const_buf
);
567 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
568 &sctx
->null_const_buf
);
569 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
570 &sctx
->null_const_buf
);
571 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
572 &sctx
->null_const_buf
);
574 /* Clear the NULL constant buffer, because loads should return zeros. */
575 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
576 sctx
->null_const_buf
.buffer
->width0
, 0,
577 SI_COHERENCY_SHADER
);
580 uint64_t max_threads_per_block
;
581 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
582 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
583 &max_threads_per_block
);
585 /* The maximum number of scratch waves. Scratch space isn't divided
586 * evenly between CUs. The number is only a function of the number of CUs.
587 * We can decrease the constant to decrease the scratch buffer size.
589 * sctx->scratch_waves must be >= the maximum posible size of
590 * 1 threadgroup, so that the hw doesn't hang from being unable
593 * The recommended value is 4 per CU at most. Higher numbers don't
594 * bring much benefit, but they still occupy chip resources (think
595 * async compute). I've seen ~2% performance difference between 4 and 32.
597 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
598 max_threads_per_block
/ 64);
600 si_init_compiler(sscreen
, &sctx
->compiler
);
602 /* Bindless handles. */
603 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
604 _mesa_key_pointer_equal
);
605 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
606 _mesa_key_pointer_equal
);
608 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
609 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
610 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
611 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
612 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
614 /* this must be last */
615 si_begin_new_gfx_cs(sctx
);
618 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
619 si_destroy_context(&sctx
->b
);
623 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
624 void *priv
, unsigned flags
)
626 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
627 struct pipe_context
*ctx
;
629 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
630 flags
|= PIPE_CONTEXT_DEBUG
;
632 ctx
= si_create_context(screen
, flags
);
634 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
637 /* Clover (compute-only) is unsupported. */
638 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
641 /* When shaders are logged to stderr, asynchronous compilation is
643 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
646 /* Use asynchronous flushes only on amdgpu, since the radeon
647 * implementation for fence_server_sync is incomplete. */
648 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
649 si_replace_buffer_storage
,
650 sscreen
->info
.drm_major
>= 3 ? si_create_fence
: NULL
,
651 &((struct si_context
*)ctx
)->tc
);
657 static void si_destroy_screen(struct pipe_screen
* pscreen
)
659 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
660 struct si_shader_part
*parts
[] = {
662 sscreen
->tcs_epilogs
,
669 if (!sscreen
->ws
->unref(sscreen
->ws
))
672 util_queue_destroy(&sscreen
->shader_compiler_queue
);
673 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
675 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
676 si_destroy_compiler(&sscreen
->compiler
[i
]);
678 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
679 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
681 /* Free shader parts. */
682 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
684 struct si_shader_part
*part
= parts
[i
];
686 parts
[i
] = part
->next
;
687 ac_shader_binary_clean(&part
->binary
);
691 mtx_destroy(&sscreen
->shader_parts_mutex
);
692 si_destroy_shader_cache(sscreen
);
694 si_perfcounters_destroy(sscreen
);
695 si_gpu_load_kill_thread(sscreen
);
697 mtx_destroy(&sscreen
->gpu_load_mutex
);
698 mtx_destroy(&sscreen
->aux_context_lock
);
699 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
701 slab_destroy_parent(&sscreen
->pool_transfers
);
703 disk_cache_destroy(sscreen
->disk_shader_cache
);
704 sscreen
->ws
->destroy(sscreen
->ws
);
708 static void si_init_gs_info(struct si_screen
*sscreen
)
710 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
711 sscreen
->info
.family
);
714 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
716 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
722 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
723 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
724 /* Override family and chip_class. */
725 sscreen
->info
.family
= i
;
727 if (i
>= CHIP_VEGA10
)
728 sscreen
->info
.chip_class
= GFX9
;
729 else if (i
>= CHIP_TONGA
)
730 sscreen
->info
.chip_class
= VI
;
731 else if (i
>= CHIP_BONAIRE
)
732 sscreen
->info
.chip_class
= CIK
;
734 sscreen
->info
.chip_class
= SI
;
736 /* Don't submit any IBs. */
737 setenv("RADEON_NOOP", "1", 1);
742 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
746 static void si_test_vmfault(struct si_screen
*sscreen
)
748 struct pipe_context
*ctx
= sscreen
->aux_context
;
749 struct si_context
*sctx
= (struct si_context
*)ctx
;
750 struct pipe_resource
*buf
=
751 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
754 puts("Buffer allocation failed.");
758 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
760 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
761 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
762 ctx
->flush(ctx
, NULL
, 0);
763 puts("VM fault test: CP - done.");
765 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
766 sctx
->dma_clear_buffer(sctx
, buf
, 0, 4, 0);
767 ctx
->flush(ctx
, NULL
, 0);
768 puts("VM fault test: SDMA - done.");
770 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
771 util_test_constant_buffer(ctx
, buf
);
772 puts("VM fault test: Shader - done.");
777 static void si_disk_cache_create(struct si_screen
*sscreen
)
779 /* Don't use the cache if shader dumping is enabled. */
780 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
783 uint32_t mesa_timestamp
;
784 if (disk_cache_get_function_timestamp(si_disk_cache_create
,
788 uint32_t llvm_timestamp
;
790 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
,
792 res
= asprintf(×tamp_str
, "%u_%u",
793 mesa_timestamp
, llvm_timestamp
);
797 /* These flags affect shader compilation. */
798 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
802 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
805 /* Add the high bits of 32-bit addresses, which affects
806 * how 32-bit addresses are expanded to 64 bits.
808 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
809 shader_debug_flags
|= (uint64_t)sscreen
->info
.address32_hi
<< 32;
811 sscreen
->disk_shader_cache
=
812 disk_cache_create(si_get_family_name(sscreen
),
820 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
821 const struct pipe_screen_config
*config
)
823 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
824 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
831 ws
->query_info(ws
, &sscreen
->info
);
833 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
836 /* Set functions first. */
837 sscreen
->b
.context_create
= si_pipe_create_context
;
838 sscreen
->b
.destroy
= si_destroy_screen
;
840 si_init_screen_get_functions(sscreen
);
841 si_init_screen_buffer_functions(sscreen
);
842 si_init_screen_fence_functions(sscreen
);
843 si_init_screen_state_functions(sscreen
);
844 si_init_screen_texture_functions(sscreen
);
845 si_init_screen_query_functions(sscreen
);
847 /* Set these flags in debug_flags early, so that the shader cache takes
850 if (driQueryOptionb(config
->options
,
851 "glsl_correct_derivatives_after_discard"))
852 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
853 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
854 sscreen
->debug_flags
|= DBG(SI_SCHED
);
857 if (sscreen
->debug_flags
& DBG(INFO
))
858 ac_print_gpu_info(&sscreen
->info
);
860 slab_create_parent(&sscreen
->pool_transfers
,
861 sizeof(struct si_transfer
), 64);
863 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
864 if (sscreen
->force_aniso
>= 0) {
865 printf("radeonsi: Forcing anisotropy filter to %ix\n",
866 /* round down to a power of two */
867 1 << util_logbase2(sscreen
->force_aniso
));
870 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
871 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
873 si_init_gs_info(sscreen
);
874 if (!si_init_shader_cache(sscreen
)) {
879 si_disk_cache_create(sscreen
);
881 /* Determine the number of shader compiler threads. */
882 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
884 if (hw_threads
>= 12) {
885 num_comp_hi_threads
= hw_threads
* 3 / 4;
886 num_comp_lo_threads
= hw_threads
/ 3;
887 } else if (hw_threads
>= 6) {
888 num_comp_hi_threads
= hw_threads
- 2;
889 num_comp_lo_threads
= hw_threads
/ 2;
890 } else if (hw_threads
>= 2) {
891 num_comp_hi_threads
= hw_threads
- 1;
892 num_comp_lo_threads
= hw_threads
/ 2;
894 num_comp_hi_threads
= 1;
895 num_comp_lo_threads
= 1;
898 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
899 ARRAY_SIZE(sscreen
->compiler
));
900 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
901 ARRAY_SIZE(sscreen
->compiler_lowp
));
903 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
904 64, num_comp_hi_threads
,
905 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
906 si_destroy_shader_cache(sscreen
);
911 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
913 64, num_comp_lo_threads
,
914 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
915 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
916 si_destroy_shader_cache(sscreen
);
921 si_handle_env_var_force_family(sscreen
);
923 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
924 si_init_perfcounters(sscreen
);
926 /* Determine tessellation ring info. */
927 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= CIK
&&
928 sscreen
->info
.family
!= CHIP_CARRIZO
&&
929 sscreen
->info
.family
!= CHIP_STONEY
;
930 /* This must be one less than the maximum number due to a hw limitation.
931 * Various hardware bugs in SI, CIK, and GFX9 need this.
933 unsigned max_offchip_buffers_per_se
;
935 /* Only certain chips can use the maximum value. */
936 if (sscreen
->info
.family
== CHIP_VEGA12
)
937 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
939 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
941 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
942 sscreen
->info
.max_se
;
943 unsigned offchip_granularity
;
945 /* Hawaii has a bug with offchip buffers > 256 that can be worked
946 * around by setting 4K granularity.
948 if (sscreen
->info
.family
== CHIP_HAWAII
) {
949 sscreen
->tess_offchip_block_dw_size
= 4096;
950 offchip_granularity
= V_03093C_X_4K_DWORDS
;
952 sscreen
->tess_offchip_block_dw_size
= 8192;
953 offchip_granularity
= V_03093C_X_8K_DWORDS
;
956 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
957 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
958 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
959 sscreen
->tess_offchip_block_dw_size
* 4;
961 if (sscreen
->info
.chip_class
>= CIK
) {
962 if (sscreen
->info
.chip_class
>= VI
)
963 --max_offchip_buffers
;
964 sscreen
->vgt_hs_offchip_param
=
965 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
966 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
968 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
969 sscreen
->vgt_hs_offchip_param
=
970 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
973 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
975 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= CIK
;
977 sscreen
->has_distributed_tess
=
978 sscreen
->info
.chip_class
>= VI
&&
979 sscreen
->info
.max_se
>= 2;
981 sscreen
->has_draw_indirect_multi
=
982 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
983 (sscreen
->info
.chip_class
== VI
&&
984 sscreen
->info
.pfp_fw_version
>= 121 &&
985 sscreen
->info
.me_fw_version
>= 87) ||
986 (sscreen
->info
.chip_class
== CIK
&&
987 sscreen
->info
.pfp_fw_version
>= 211 &&
988 sscreen
->info
.me_fw_version
>= 173) ||
989 (sscreen
->info
.chip_class
== SI
&&
990 sscreen
->info
.pfp_fw_version
>= 79 &&
991 sscreen
->info
.me_fw_version
>= 142);
993 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= VI
&&
994 sscreen
->info
.max_se
>= 2 &&
995 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
996 sscreen
->assume_no_z_fights
=
997 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
998 sscreen
->commutative_blend_add
=
999 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1000 sscreen
->clear_db_cache_before_clear
=
1001 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
1002 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
1003 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
1004 sscreen
->info
.family
== CHIP_VEGA10
||
1005 sscreen
->info
.family
== CHIP_RAVEN
;
1006 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1007 sscreen
->info
.family
== CHIP_RAVEN
;
1009 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1010 sscreen
->dpbb_allowed
= true;
1012 /* Only enable primitive binning on Raven by default. */
1013 /* TODO: Investigate if binning is profitable on Vega12. */
1014 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
&&
1015 !(sscreen
->debug_flags
& DBG(NO_DPBB
));
1018 if (sscreen
->debug_flags
& DBG(DFSM
)) {
1019 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
;
1021 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
1022 !(sscreen
->debug_flags
& DBG(NO_DFSM
));
1025 /* While it would be nice not to have this flag, we are constrained
1026 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1029 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= VI
;
1031 /* Some chips have RB+ registers, but don't support RB+. Those must
1032 * always disable it.
1034 if (sscreen
->info
.family
== CHIP_STONEY
||
1035 sscreen
->info
.chip_class
>= GFX9
) {
1036 sscreen
->has_rbplus
= true;
1038 sscreen
->rbplus_allowed
=
1039 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
1040 (sscreen
->info
.family
== CHIP_STONEY
||
1041 sscreen
->info
.family
== CHIP_VEGA12
||
1042 sscreen
->info
.family
== CHIP_RAVEN
);
1045 sscreen
->dcc_msaa_allowed
=
1046 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1048 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= VI
;
1050 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1051 sscreen
->use_monolithic_shaders
=
1052 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1054 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
1055 SI_CONTEXT_INV_VMEM_L1
;
1056 if (sscreen
->info
.chip_class
<= VI
) {
1057 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
1058 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1061 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1062 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1069 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1071 * s >= z >= c (ignoring this only wastes memory)
1076 * Only MSAA color and depth buffers are overriden.
1078 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1079 const char *eqaa
= debug_get_option("EQAA", NULL
);
1082 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1083 sscreen
->eqaa_force_coverage_samples
= s
;
1084 sscreen
->eqaa_force_z_samples
= z
;
1085 sscreen
->eqaa_force_color_samples
= f
;
1089 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1090 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1091 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1092 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1094 /* Create the auxiliary context. This must be done last. */
1095 sscreen
->aux_context
= si_create_context(&sscreen
->b
, 0);
1097 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1098 si_test_dma(sscreen
);
1100 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1101 DBG(TEST_VMFAULT_SDMA
) |
1102 DBG(TEST_VMFAULT_SHADER
)))
1103 si_test_vmfault(sscreen
);