src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_uvd.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39
  40         si_release_all_descriptors(sctx);
  41
  42         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  43         r600_resource_reference(&sctx->border_color_table, NULL);
  44
  45         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  46         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  47         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  48
  49         if (sctx->dummy_pixel_shader) {
  50                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  51         }
  52         for (int i = 0; i < 8; i++) {
  53                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  54                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  55                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  56         }
  57         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  58         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  59         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  60         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  61         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  62
  63         util_blitter_destroy(sctx->blitter);
  64
  65         si_pm4_cleanup(sctx);
  66
  67         r600_common_context_cleanup(&sctx->b);
  68         FREE(sctx);
  69 }
  70
  71 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  72 {
  73         struct si_context *sctx = CALLOC_STRUCT(si_context);
  74         struct si_screen* sscreen = (struct si_screen *)screen;
  75         struct radeon_winsys *ws = sscreen->b.ws;
  76         int shader, i;
  77
  78         if (sctx == NULL)
  79                 return NULL;
  80
  81         sctx->b.b.screen = screen; /* this must be set first */
  82         sctx->b.b.priv = priv;
  83         sctx->b.b.destroy = si_destroy_context;
  84         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  85
  86         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  87                 goto fail;
  88
  89         si_init_blit_functions(sctx);
  90         si_init_compute_functions(sctx);
  91
  92         if (sscreen->b.info.has_uvd) {
  93                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  94                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  95         } else {
  96                 sctx->b.b.create_video_codec = vl_create_decoder;
  97                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
  98         }
  99
 100         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 101                                              sctx, NULL);
 102         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 103
 104         si_init_all_descriptors(sctx);
 105
 106         /* Initialize cache_flush. */
 107         sctx->cache_flush = si_atom_cache_flush;
 108         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 109
 110         sctx->msaa_config = si_atom_msaa_config;
 111         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 112
 113         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 114         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 115
 116         switch (sctx->b.chip_class) {
 117         case SI:
 118         case CIK:
 119                 si_init_state_functions(sctx);
 120                 si_init_config(sctx);
 121                 break;
 122         default:
 123                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 124                 goto fail;
 125         }
 126
 127         sctx->blitter = util_blitter_create(&sctx->b.b);
 128         if (sctx->blitter == NULL)
 129                 goto fail;
 130         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 131
 132         sctx->dummy_pixel_shader =
 133                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 134                                                      TGSI_SEMANTIC_GENERIC,
 135                                                      TGSI_INTERPOLATE_CONSTANT);
 136         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 137
 138         /* these must be last */
 139         si_begin_new_cs(sctx);
 140         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 141
 142         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 143          * with a NULL buffer). We need to use a dummy buffer instead. */
 144         if (sctx->b.chip_class == CIK) {
 145                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 146                                                                  PIPE_USAGE_DEFAULT, 16);
 147                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 148
 149                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 150                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 151                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 152                                                               &sctx->null_const_buf);
 153                         }
 154                 }
 155
 156                 /* Clear the NULL constant buffer, because loads should return zeros. */
 157                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 158                                      sctx->null_const_buf.buffer->width0, 0);
 159         }
 160
 161         return &sctx->b.b;
 162 fail:
 163         si_destroy_context(&sctx->b.b);
 164         return NULL;
 165 }
 166
 167 /*
 168  * pipe_screen
 169  */
 170
 171 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 172 {
 173         struct si_screen *sscreen = (struct si_screen *)pscreen;
 174
 175         switch (param) {
 176         /* Supported features (boolean caps). */
 177         case PIPE_CAP_TWO_SIDED_STENCIL:
 178         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 179         case PIPE_CAP_ANISOTROPIC_FILTER:
 180         case PIPE_CAP_POINT_SPRITE:
 181         case PIPE_CAP_OCCLUSION_QUERY:
 182         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 183         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 184         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 185         case PIPE_CAP_TEXTURE_SWIZZLE:
 186         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 187         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 188         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 189         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 190         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 191         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 192         case PIPE_CAP_SM3:
 193         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 194         case PIPE_CAP_PRIMITIVE_RESTART:
 195         case PIPE_CAP_CONDITIONAL_RENDER:
 196         case PIPE_CAP_TEXTURE_BARRIER:
 197         case PIPE_CAP_INDEP_BLEND_ENABLE:
 198         case PIPE_CAP_INDEP_BLEND_FUNC:
 199         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 200         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 201         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 202         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 203         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 204         case PIPE_CAP_USER_INDEX_BUFFERS:
 205         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 206         case PIPE_CAP_START_INSTANCE:
 207         case PIPE_CAP_NPOT_TEXTURES:
 208         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 209         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 210         case PIPE_CAP_TGSI_INSTANCEID:
 211         case PIPE_CAP_COMPUTE:
 212         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 213         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 214         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 215         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 216         case PIPE_CAP_CUBE_MAP_ARRAY:
 217         case PIPE_CAP_SAMPLE_SHADING:
 218         case PIPE_CAP_DRAW_INDIRECT:
 219                 return 1;
 220
 221         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 222                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 223                 return sscreen->b.chip_class < CIK ||
 224                        sscreen->b.info.drm_minor >= 35;
 225
 226         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 227                 return R600_MAP_BUFFER_ALIGNMENT;
 228
 229         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 230         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 231                 return 4;
 232
 233         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 234                 return 330;
 235
 236         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 237                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 238
 239         case PIPE_CAP_TEXTURE_QUERY_LOD:
 240         case PIPE_CAP_TEXTURE_GATHER_SM5:
 241                 return HAVE_LLVM >= 0x0305;
 242         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 243                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 244
 245         /* Unsupported features. */
 246         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 247         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 248         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 249         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 250         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 251         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 252         case PIPE_CAP_USER_VERTEX_BUFFERS:
 253         case PIPE_CAP_TGSI_TEXCOORD:
 254         case PIPE_CAP_FAKE_SW_MSAA:
 255         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 256         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 257         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 258         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 259                 return 0;
 260
 261         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 262                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 263
 264         /* Stream output. */
 265         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 266                 return sscreen->b.has_streamout ? 4 : 0;
 267         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 268                 return sscreen->b.has_streamout ? 1 : 0;
 269         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 270         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 271                 return sscreen->b.has_streamout ? 32*4 : 0;
 272
 273         /* Geometry shader output. */
 274         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 275                 return 1024;
 276         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 277                 return 4095;
 278         case PIPE_CAP_MAX_VERTEX_STREAMS:
 279                 return 1;
 280
 281         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 282                 return 2048;
 283
 284         /* Texturing. */
 285         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 286         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 287                 return 15; /* 16384 */
 288         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 289                 /* textures support 8192, but layered rendering supports 2048 */
 290                 return 12;
 291         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 292                 /* textures support 8192, but layered rendering supports 2048 */
 293                 return 2048;
 294
 295         /* Render targets. */
 296         case PIPE_CAP_MAX_RENDER_TARGETS:
 297                 return 8;
 298
 299         case PIPE_CAP_MAX_VIEWPORTS:
 300                 return 1;
 301
 302         /* Timer queries, present when the clock frequency is non zero. */
 303         case PIPE_CAP_QUERY_TIMESTAMP:
 304         case PIPE_CAP_QUERY_TIME_ELAPSED:
 305                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 306
 307         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 308         case PIPE_CAP_MIN_TEXEL_OFFSET:
 309                 return -32;
 310
 311         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 312         case PIPE_CAP_MAX_TEXEL_OFFSET:
 313                 return 31;
 314
 315         case PIPE_CAP_ENDIANNESS:
 316                 return PIPE_ENDIAN_LITTLE;
 317
 318         case PIPE_CAP_VENDOR_ID:
 319                 return 0x1002;
 320         case PIPE_CAP_DEVICE_ID:
 321                 return sscreen->b.info.pci_id;
 322         case PIPE_CAP_ACCELERATED:
 323                 return 1;
 324         case PIPE_CAP_VIDEO_MEMORY:
 325                 return sscreen->b.info.vram_size >> 20;
 326         case PIPE_CAP_UMA:
 327                 return 0;
 328         }
 329         return 0;
 330 }
 331
 332 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 333 {
 334         switch(shader)
 335         {
 336         case PIPE_SHADER_FRAGMENT:
 337         case PIPE_SHADER_VERTEX:
 338         case PIPE_SHADER_GEOMETRY:
 339                 break;
 340         case PIPE_SHADER_COMPUTE:
 341                 switch (param) {
 342                 case PIPE_SHADER_CAP_PREFERRED_IR:
 343                         return PIPE_SHADER_IR_LLVM;
 344                 case PIPE_SHADER_CAP_DOUBLES:
 345                         return 0; /* XXX: Enable doubles once the compiler can
 346                                      handle them. */
 347                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 348                         uint64_t max_const_buffer_size;
 349                         pscreen->get_compute_param(pscreen,
 350                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 351                                 &max_const_buffer_size);
 352                         return max_const_buffer_size;
 353                 }
 354                 default:
 355                         return 0;
 356                 }
 357         default:
 358                 /* TODO: support tessellation */
 359                 return 0;
 360         }
 361
 362         switch (param) {
 363         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 364         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 365         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 366         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 367                 return 16384;
 368         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 369                 return 32;
 370         case PIPE_SHADER_CAP_MAX_INPUTS:
 371                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 372         case PIPE_SHADER_CAP_MAX_TEMPS:
 373                 return 256; /* Max native temporaries. */
 374         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 375                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 376         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 377                 return SI_NUM_USER_CONST_BUFFERS;
 378         case PIPE_SHADER_CAP_MAX_PREDS:
 379                 return 0; /* FIXME */
 380         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 381                 return 1;
 382         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 383                 return 0;
 384         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 385                 /* Indirection of geometry shader input dimension is not
 386                  * handled yet
 387                  */
 388                 return shader < PIPE_SHADER_GEOMETRY;
 389         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 390         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 391         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 392                 return 1;
 393         case PIPE_SHADER_CAP_INTEGERS:
 394                 return 1;
 395         case PIPE_SHADER_CAP_SUBROUTINES:
 396                 return 0;
 397         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 398         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 399                 return 16;
 400         case PIPE_SHADER_CAP_PREFERRED_IR:
 401                 return PIPE_SHADER_IR_TGSI;
 402         case PIPE_SHADER_CAP_DOUBLES:
 403                 return 0;
 404         }
 405         return 0;
 406 }
 407
 408 static void si_destroy_screen(struct pipe_screen* pscreen)
 409 {
 410         struct si_screen *sscreen = (struct si_screen *)pscreen;
 411
 412         if (sscreen == NULL)
 413                 return;
 414
 415         if (!sscreen->b.ws->unref(sscreen->b.ws))
 416                 return;
 417
 418         r600_destroy_common_screen(&sscreen->b);
 419 }
 420
 421 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 422
 423 /* Initialize pipe config. This is especially important for GPUs
 424  * with 16 pipes and more where it's initialized incorrectly by
 425  * the TILING_CONFIG ioctl. */
 426 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 427 {
 428         unsigned mode2d;
 429
 430         /* This is okay, because there can be no 2D tiling without
 431          * the tile mode array, so we won't need the pipe config.
 432          * Return "success".
 433          */
 434         if (!sscreen->b.info.si_tile_mode_array_valid)
 435                 return true;
 436
 437         /* The same index is used for the 2D mode on CIK too. */
 438         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 439
 440         switch (G_009910_PIPE_CONFIG(mode2d)) {
 441         case V_02803C_ADDR_SURF_P2:
 442                 sscreen->b.tiling_info.num_channels = 2;
 443                 break;
 444         case V_02803C_X_ADDR_SURF_P4_8X16:
 445         case V_02803C_X_ADDR_SURF_P4_16X16:
 446         case V_02803C_X_ADDR_SURF_P4_16X32:
 447         case V_02803C_X_ADDR_SURF_P4_32X32:
 448                 sscreen->b.tiling_info.num_channels = 4;
 449                 break;
 450         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 451         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 452         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 453         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 454         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 455         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 456         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 457                 sscreen->b.tiling_info.num_channels = 8;
 458                 break;
 459         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 460         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 461                 sscreen->b.tiling_info.num_channels = 16;
 462                 break;
 463         default:
 464                 assert(0);
 465                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 466                         G_009910_PIPE_CONFIG(mode2d));
 467                 return false;
 468         }
 469         return true;
 470 }
 471
 472 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 473 {
 474         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 475         if (sscreen == NULL) {
 476                 return NULL;
 477         }
 478
 479         /* Set functions first. */
 480         sscreen->b.b.context_create = si_create_context;
 481         sscreen->b.b.destroy = si_destroy_screen;
 482         sscreen->b.b.get_param = si_get_param;
 483         sscreen->b.b.get_shader_param = si_get_shader_param;
 484         sscreen->b.b.is_format_supported = si_is_format_supported;
 485         sscreen->b.b.resource_create = r600_resource_create_common;
 486
 487         if (!r600_common_screen_init(&sscreen->b, ws) ||
 488             !si_initialize_pipe_config(sscreen)) {
 489                 FREE(sscreen);
 490                 return NULL;
 491         }
 492
 493         sscreen->b.has_cp_dma = true;
 494         sscreen->b.has_streamout = true;
 495
 496         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 497                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 498
 499         /* Create the auxiliary context. This must be done last. */
 500         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 501
 502         return &sscreen->b.b;
 503 }