src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_llvm_emit.h"
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39         int i;
  40
  41         si_release_all_descriptors(sctx);
  42
  43         pipe_resource_reference(&sctx->esgs_ring, NULL);
  44         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  45         pipe_resource_reference(&sctx->tf_ring, NULL);
  46         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  47         r600_resource_reference(&sctx->border_color_buffer, NULL);
  48         free(sctx->border_color_table);
  49         r600_resource_reference(&sctx->scratch_buffer, NULL);
  50         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  51
  52         si_pm4_free_state(sctx, sctx->init_config, ~0);
  53         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  54                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  55
  56         if (sctx->pstipple_sampler_state)
  57                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  58         if (sctx->fixed_func_tcs_shader.cso)
  59                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  60         if (sctx->custom_dsa_flush)
  61                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  62         if (sctx->custom_blend_resolve)
  63                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  64         if (sctx->custom_blend_decompress)
  65                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  66         if (sctx->custom_blend_fastclear)
  67                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  68         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  69
  70         if (sctx->blitter)
  71                 util_blitter_destroy(sctx->blitter);
  72
  73         r600_common_context_cleanup(&sctx->b);
  74
  75 #if HAVE_LLVM >= 0x0306
  76         LLVMDisposeTargetMachine(sctx->tm);
  77 #endif
  78
  79         r600_resource_reference(&sctx->trace_buf, NULL);
  80         r600_resource_reference(&sctx->last_trace_buf, NULL);
  81         free(sctx->last_ib);
  82         if (sctx->last_bo_list) {
  83                 for (i = 0; i < sctx->last_bo_count; i++)
  84                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  85                 free(sctx->last_bo_list);
  86         }
  87         FREE(sctx);
  88 }
  89
  90 static enum pipe_reset_status
  91 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  92 {
  93         struct si_context *sctx = (struct si_context *)ctx;
  94
  95         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  96 }
  97
  98 static struct pipe_context *si_create_context(struct pipe_screen *screen,
  99                                               void *priv, unsigned flags)
 100 {
 101         struct si_context *sctx = CALLOC_STRUCT(si_context);
 102         struct si_screen* sscreen = (struct si_screen *)screen;
 103         struct radeon_winsys *ws = sscreen->b.ws;
 104         LLVMTargetRef r600_target;
 105 #if HAVE_LLVM >= 0x0306
 106         const char *triple = "amdgcn--";
 107 #endif
 108         int shader, i;
 109
 110         if (sctx == NULL)
 111                 return NULL;
 112
 113         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 114                 flags |= PIPE_CONTEXT_DEBUG;
 115
 116         sctx->b.b.screen = screen; /* this must be set first */
 117         sctx->b.b.priv = priv;
 118         sctx->b.b.destroy = si_destroy_context;
 119         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 120         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 121         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 122
 123         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 124                 goto fail;
 125
 126         if (sscreen->b.info.drm_major == 3)
 127                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 128
 129         si_init_blit_functions(sctx);
 130         si_init_compute_functions(sctx);
 131         si_init_cp_dma_functions(sctx);
 132         si_init_debug_functions(sctx);
 133
 134         if (sscreen->b.info.has_uvd) {
 135                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 136                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 137         } else {
 138                 sctx->b.b.create_video_codec = vl_create_decoder;
 139                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 140         }
 141
 142         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
 143                                        sctx, sscreen->b.trace_bo ?
 144                                                sscreen->b.trace_bo->cs_buf : NULL);
 145         sctx->b.gfx.flush = si_context_gfx_flush;
 146
 147         /* Border colors. */
 148         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 149                                           sizeof(*sctx->border_color_table));
 150         if (!sctx->border_color_table)
 151                 goto fail;
 152
 153         sctx->border_color_buffer = (struct r600_resource*)
 154                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 155                                    SI_MAX_BORDER_COLORS *
 156                                    sizeof(*sctx->border_color_table));
 157         if (!sctx->border_color_buffer)
 158                 goto fail;
 159
 160         sctx->border_color_map =
 161                 ws->buffer_map(sctx->border_color_buffer->cs_buf,
 162                                NULL, PIPE_TRANSFER_WRITE);
 163         if (!sctx->border_color_map)
 164                 goto fail;
 165
 166         si_init_all_descriptors(sctx);
 167         si_init_state_functions(sctx);
 168         si_init_shader_functions(sctx);
 169
 170         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 171                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 172
 173         sctx->blitter = util_blitter_create(&sctx->b.b);
 174         if (sctx->blitter == NULL)
 175                 goto fail;
 176         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 177
 178         sctx->sample_mask.sample_mask = 0xffff;
 179
 180         /* these must be last */
 181         si_begin_new_cs(sctx);
 182         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 183
 184         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 185          * with a NULL buffer). We need to use a dummy buffer instead. */
 186         if (sctx->b.chip_class == CIK) {
 187                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 188                                                                  PIPE_USAGE_DEFAULT, 16);
 189                 if (!sctx->null_const_buf.buffer)
 190                         goto fail;
 191                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 192
 193                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 194                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 195                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 196                                                               &sctx->null_const_buf);
 197                         }
 198                 }
 199
 200                 /* Clear the NULL constant buffer, because loads should return zeros. */
 201                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 202                                      sctx->null_const_buf.buffer->width0, 0, false);
 203         }
 204
 205         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 206          * this for non-cs shaders.  Using the wrong value here can result in
 207          * GPU lockups, but the maximum value seems to always work.
 208          */
 209         sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 210
 211 #if HAVE_LLVM >= 0x0306
 212         /* Initialize LLVM TargetMachine */
 213         r600_target = radeon_llvm_get_r600_target(triple);
 214         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 215                                            r600_get_llvm_processor_name(sscreen->b.family),
 216                                            "+DumpCode,+vgpr-spilling",
 217                                            LLVMCodeGenLevelDefault,
 218                                            LLVMRelocDefault,
 219                                            LLVMCodeModelDefault);
 220 #endif
 221
 222         return &sctx->b.b;
 223 fail:
 224         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 225         si_destroy_context(&sctx->b.b);
 226         return NULL;
 227 }
 228
 229 /*
 230  * pipe_screen
 231  */
 232
 233 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 234 {
 235         struct si_screen *sscreen = (struct si_screen *)pscreen;
 236
 237         switch (param) {
 238         /* Supported features (boolean caps). */
 239         case PIPE_CAP_TWO_SIDED_STENCIL:
 240         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 241         case PIPE_CAP_ANISOTROPIC_FILTER:
 242         case PIPE_CAP_POINT_SPRITE:
 243         case PIPE_CAP_OCCLUSION_QUERY:
 244         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 245         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 246         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 247         case PIPE_CAP_TEXTURE_SWIZZLE:
 248         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 249         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 250         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 251         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 252         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 253         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 254         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 255         case PIPE_CAP_SM3:
 256         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 257         case PIPE_CAP_PRIMITIVE_RESTART:
 258         case PIPE_CAP_CONDITIONAL_RENDER:
 259         case PIPE_CAP_TEXTURE_BARRIER:
 260         case PIPE_CAP_INDEP_BLEND_ENABLE:
 261         case PIPE_CAP_INDEP_BLEND_FUNC:
 262         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 263         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 264         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 265         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 266         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_USER_INDEX_BUFFERS:
 268         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 269         case PIPE_CAP_START_INSTANCE:
 270         case PIPE_CAP_NPOT_TEXTURES:
 271         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 272         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 273         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 274         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 275         case PIPE_CAP_TGSI_INSTANCEID:
 276         case PIPE_CAP_COMPUTE:
 277         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 278         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 279         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 280         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 281         case PIPE_CAP_CUBE_MAP_ARRAY:
 282         case PIPE_CAP_SAMPLE_SHADING:
 283         case PIPE_CAP_DRAW_INDIRECT:
 284         case PIPE_CAP_CLIP_HALFZ:
 285         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 286         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 287         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 288         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 289         case PIPE_CAP_TGSI_TEXCOORD:
 290         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 291         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 292         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 293         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 294         case PIPE_CAP_SHAREABLE_SHADERS:
 295         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 296         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 297         case PIPE_CAP_TEXTURE_QUERY_LOD:
 298         case PIPE_CAP_TEXTURE_GATHER_SM5:
 299         case PIPE_CAP_TGSI_TXQS:
 300         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 301         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 302                 return 1;
 303
 304         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 305                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 306
 307         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 308                 return (sscreen->b.info.drm_major == 2 &&
 309                         sscreen->b.info.drm_minor >= 43) ||
 310                        sscreen->b.info.drm_major == 3;
 311
 312         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 313                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 314                 return sscreen->b.chip_class < CIK ||
 315                        (sscreen->b.info.drm_major == 2 &&
 316                         sscreen->b.info.drm_minor >= 35) ||
 317                        sscreen->b.info.drm_major == 3;
 318
 319         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 320                 return R600_MAP_BUFFER_ALIGNMENT;
 321
 322         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 323         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 324         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 325                 return 4;
 326
 327         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 328                 return HAVE_LLVM >= 0x0307 ? 410 : 330;
 329
 330         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 331                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 332
 333         /* Unsupported features. */
 334         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 335         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 336         case PIPE_CAP_USER_VERTEX_BUFFERS:
 337         case PIPE_CAP_FAKE_SW_MSAA:
 338         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 339         case PIPE_CAP_VERTEXID_NOBASE:
 340         case PIPE_CAP_CLEAR_TEXTURE:
 341                 return 0;
 342
 343         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 344                 return 30;
 345
 346         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 347                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 348
 349         /* Stream output. */
 350         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 351                 return sscreen->b.has_streamout ? 4 : 0;
 352         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 353                 return sscreen->b.has_streamout ? 1 : 0;
 354         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 355         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 356                 return sscreen->b.has_streamout ? 32*4 : 0;
 357
 358         /* Geometry shader output. */
 359         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 360                 return 1024;
 361         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 362                 return 4095;
 363         case PIPE_CAP_MAX_VERTEX_STREAMS:
 364                 return 4;
 365
 366         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 367                 return 2048;
 368
 369         /* Texturing. */
 370         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 371         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 372                 return 15; /* 16384 */
 373         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 374                 /* textures support 8192, but layered rendering supports 2048 */
 375                 return 12;
 376         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 377                 /* textures support 8192, but layered rendering supports 2048 */
 378                 return 2048;
 379
 380         /* Render targets. */
 381         case PIPE_CAP_MAX_RENDER_TARGETS:
 382                 return 8;
 383
 384         case PIPE_CAP_MAX_VIEWPORTS:
 385                 return SI_MAX_VIEWPORTS;
 386
 387         /* Timer queries, present when the clock frequency is non zero. */
 388         case PIPE_CAP_QUERY_TIMESTAMP:
 389         case PIPE_CAP_QUERY_TIME_ELAPSED:
 390                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 391
 392         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 393         case PIPE_CAP_MIN_TEXEL_OFFSET:
 394                 return -32;
 395
 396         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 397         case PIPE_CAP_MAX_TEXEL_OFFSET:
 398                 return 31;
 399
 400         case PIPE_CAP_ENDIANNESS:
 401                 return PIPE_ENDIAN_LITTLE;
 402
 403         case PIPE_CAP_VENDOR_ID:
 404                 return 0x1002;
 405         case PIPE_CAP_DEVICE_ID:
 406                 return sscreen->b.info.pci_id;
 407         case PIPE_CAP_ACCELERATED:
 408                 return 1;
 409         case PIPE_CAP_VIDEO_MEMORY:
 410                 return sscreen->b.info.vram_size >> 20;
 411         case PIPE_CAP_UMA:
 412                 return 0;
 413         }
 414         return 0;
 415 }
 416
 417 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 418 {
 419         switch(shader)
 420         {
 421         case PIPE_SHADER_FRAGMENT:
 422         case PIPE_SHADER_VERTEX:
 423         case PIPE_SHADER_GEOMETRY:
 424                 break;
 425         case PIPE_SHADER_TESS_CTRL:
 426         case PIPE_SHADER_TESS_EVAL:
 427                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 428                 if (HAVE_LLVM < 0x0306 ||
 429                     (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
 430                         return 0;
 431                 break;
 432         case PIPE_SHADER_COMPUTE:
 433                 switch (param) {
 434                 case PIPE_SHADER_CAP_PREFERRED_IR:
 435 #if HAVE_LLVM < 0x0306
 436                         return PIPE_SHADER_IR_LLVM;
 437 #else
 438                         return PIPE_SHADER_IR_NATIVE;
 439 #endif
 440                 case PIPE_SHADER_CAP_DOUBLES:
 441                         return HAVE_LLVM >= 0x0307;
 442
 443                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 444                         uint64_t max_const_buffer_size;
 445                         pscreen->get_compute_param(pscreen,
 446                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 447                                 &max_const_buffer_size);
 448                         return max_const_buffer_size;
 449                 }
 450                 default:
 451                         /* If compute shaders don't require a special value
 452                          * for this cap, we can return the same value we
 453                          * do for other shader types. */
 454                         break;
 455                 }
 456                 break;
 457         default:
 458                 return 0;
 459         }
 460
 461         switch (param) {
 462         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 463         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 464         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 465         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 466                 return 16384;
 467         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 468                 return 32;
 469         case PIPE_SHADER_CAP_MAX_INPUTS:
 470                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 471         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 472                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 473         case PIPE_SHADER_CAP_MAX_TEMPS:
 474                 return 256; /* Max native temporaries. */
 475         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 476                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 477         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 478                 return SI_NUM_USER_CONST_BUFFERS;
 479         case PIPE_SHADER_CAP_MAX_PREDS:
 480                 return 0; /* FIXME */
 481         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 482                 return 1;
 483         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 484                 return 1;
 485         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 486                 /* Indirection of geometry shader input dimension is not
 487                  * handled yet
 488                  */
 489                 return shader != PIPE_SHADER_GEOMETRY;
 490         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 491         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 492         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 493                 return 1;
 494         case PIPE_SHADER_CAP_INTEGERS:
 495                 return 1;
 496         case PIPE_SHADER_CAP_SUBROUTINES:
 497                 return 0;
 498         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 499         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 500                 return 16;
 501         case PIPE_SHADER_CAP_PREFERRED_IR:
 502                 return PIPE_SHADER_IR_TGSI;
 503         case PIPE_SHADER_CAP_DOUBLES:
 504                 return HAVE_LLVM >= 0x0307;
 505         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 506         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 507                 return 0;
 508         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 509         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 510                 return 1;
 511         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 512                 return 32;
 513         }
 514         return 0;
 515 }
 516
 517 static void si_destroy_screen(struct pipe_screen* pscreen)
 518 {
 519         struct si_screen *sscreen = (struct si_screen *)pscreen;
 520
 521         if (sscreen == NULL)
 522                 return;
 523
 524         if (!sscreen->b.ws->unref(sscreen->b.ws))
 525                 return;
 526
 527         r600_destroy_common_screen(&sscreen->b);
 528 }
 529
 530 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 531
 532 /* Initialize pipe config. This is especially important for GPUs
 533  * with 16 pipes and more where it's initialized incorrectly by
 534  * the TILING_CONFIG ioctl. */
 535 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 536 {
 537         unsigned mode2d;
 538
 539         /* This is okay, because there can be no 2D tiling without
 540          * the tile mode array, so we won't need the pipe config.
 541          * Return "success".
 542          */
 543         if (!sscreen->b.info.si_tile_mode_array_valid)
 544                 return true;
 545
 546         /* The same index is used for the 2D mode on CIK too. */
 547         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 548
 549         switch (G_009910_PIPE_CONFIG(mode2d)) {
 550         case V_02803C_ADDR_SURF_P2:
 551                 sscreen->b.tiling_info.num_channels = 2;
 552                 break;
 553         case V_02803C_X_ADDR_SURF_P4_8X16:
 554         case V_02803C_X_ADDR_SURF_P4_16X16:
 555         case V_02803C_X_ADDR_SURF_P4_16X32:
 556         case V_02803C_X_ADDR_SURF_P4_32X32:
 557                 sscreen->b.tiling_info.num_channels = 4;
 558                 break;
 559         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 560         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 561         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 562         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 563         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 564         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 565         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 566                 sscreen->b.tiling_info.num_channels = 8;
 567                 break;
 568         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 569         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 570                 sscreen->b.tiling_info.num_channels = 16;
 571                 break;
 572         default:
 573                 assert(0);
 574                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 575                         G_009910_PIPE_CONFIG(mode2d));
 576                 return false;
 577         }
 578         return true;
 579 }
 580
 581 static bool si_init_gs_info(struct si_screen *sscreen)
 582 {
 583         switch (sscreen->b.family) {
 584         case CHIP_OLAND:
 585         case CHIP_HAINAN:
 586         case CHIP_KAVERI:
 587         case CHIP_KABINI:
 588         case CHIP_MULLINS:
 589         case CHIP_ICELAND:
 590         case CHIP_CARRIZO:
 591         case CHIP_STONEY:
 592                 sscreen->gs_table_depth = 16;
 593                 return true;
 594         case CHIP_TAHITI:
 595         case CHIP_PITCAIRN:
 596         case CHIP_VERDE:
 597         case CHIP_BONAIRE:
 598         case CHIP_HAWAII:
 599         case CHIP_TONGA:
 600         case CHIP_FIJI:
 601                 sscreen->gs_table_depth = 32;
 602                 return true;
 603         default:
 604                 return false;
 605         }
 606 }
 607
 608 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 609 {
 610         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 611
 612         if (sscreen == NULL) {
 613                 return NULL;
 614         }
 615
 616         /* Set functions first. */
 617         sscreen->b.b.context_create = si_create_context;
 618         sscreen->b.b.destroy = si_destroy_screen;
 619         sscreen->b.b.get_param = si_get_param;
 620         sscreen->b.b.get_shader_param = si_get_shader_param;
 621         sscreen->b.b.is_format_supported = si_is_format_supported;
 622         sscreen->b.b.resource_create = r600_resource_create_common;
 623
 624         if (!r600_common_screen_init(&sscreen->b, ws) ||
 625             !si_initialize_pipe_config(sscreen) ||
 626             !si_init_gs_info(sscreen)) {
 627                 FREE(sscreen);
 628                 return NULL;
 629         }
 630
 631         sscreen->b.has_cp_dma = true;
 632         sscreen->b.has_streamout = true;
 633
 634         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 635                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 636
 637         /* Create the auxiliary context. This must be done last. */
 638         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 639
 640         return &sscreen->b.b;
 641 }