2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_public.h"
28 #include "radeon/radeon_llvm_emit.h"
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "vl/vl_decoder.h"
36 static void si_destroy_context(struct pipe_context
*context
)
38 struct si_context
*sctx
= (struct si_context
*)context
;
41 si_release_all_descriptors(sctx
);
43 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
44 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
45 pipe_resource_reference(&sctx
->tf_ring
, NULL
);
46 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
47 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
48 free(sctx
->border_color_table
);
49 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
50 sctx
->b
.ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
52 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
53 if (sctx
->init_config_gs_rings
)
54 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
55 for (i
= 0; i
< Elements(sctx
->vgt_shader_config
); i
++)
56 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
58 if (sctx
->pstipple_sampler_state
)
59 sctx
->b
.b
.delete_sampler_state(&sctx
->b
.b
, sctx
->pstipple_sampler_state
);
60 if (sctx
->fixed_func_tcs_shader
.cso
)
61 sctx
->b
.b
.delete_tcs_state(&sctx
->b
.b
, sctx
->fixed_func_tcs_shader
.cso
);
62 if (sctx
->custom_dsa_flush
)
63 sctx
->b
.b
.delete_depth_stencil_alpha_state(&sctx
->b
.b
, sctx
->custom_dsa_flush
);
64 if (sctx
->custom_blend_resolve
)
65 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_resolve
);
66 if (sctx
->custom_blend_decompress
)
67 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_decompress
);
68 if (sctx
->custom_blend_fastclear
)
69 sctx
->b
.b
.delete_blend_state(&sctx
->b
.b
, sctx
->custom_blend_fastclear
);
70 util_unreference_framebuffer_state(&sctx
->framebuffer
.state
);
73 util_blitter_destroy(sctx
->blitter
);
75 r600_common_context_cleanup(&sctx
->b
);
77 #if HAVE_LLVM >= 0x0306
78 LLVMDisposeTargetMachine(sctx
->tm
);
81 r600_resource_reference(&sctx
->trace_buf
, NULL
);
82 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
84 if (sctx
->last_bo_list
) {
85 for (i
= 0; i
< sctx
->last_bo_count
; i
++)
86 pb_reference(&sctx
->last_bo_list
[i
].buf
, NULL
);
87 free(sctx
->last_bo_list
);
92 static enum pipe_reset_status
93 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
95 struct si_context
*sctx
= (struct si_context
*)ctx
;
97 return sctx
->b
.ws
->ctx_query_reset_status(sctx
->b
.ctx
);
100 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
101 void *priv
, unsigned flags
)
103 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
104 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
105 struct radeon_winsys
*ws
= sscreen
->b
.ws
;
106 LLVMTargetRef r600_target
;
107 #if HAVE_LLVM >= 0x0306
108 const char *triple
= "amdgcn--";
115 if (sscreen
->b
.debug_flags
& DBG_CHECK_VM
)
116 flags
|= PIPE_CONTEXT_DEBUG
;
118 sctx
->b
.b
.screen
= screen
; /* this must be set first */
119 sctx
->b
.b
.priv
= priv
;
120 sctx
->b
.b
.destroy
= si_destroy_context
;
121 sctx
->b
.set_atom_dirty
= (void *)si_set_atom_dirty
;
122 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
123 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
125 if (!r600_common_context_init(&sctx
->b
, &sscreen
->b
))
128 if (sscreen
->b
.info
.drm_major
== 3)
129 sctx
->b
.b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
131 si_init_blit_functions(sctx
);
132 si_init_compute_functions(sctx
);
133 si_init_cp_dma_functions(sctx
);
134 si_init_debug_functions(sctx
);
136 if (sscreen
->b
.info
.has_uvd
) {
137 sctx
->b
.b
.create_video_codec
= si_uvd_create_decoder
;
138 sctx
->b
.b
.create_video_buffer
= si_video_buffer_create
;
140 sctx
->b
.b
.create_video_codec
= vl_create_decoder
;
141 sctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
144 sctx
->b
.gfx
.cs
= ws
->cs_create(sctx
->b
.ctx
, RING_GFX
, si_context_gfx_flush
,
145 sctx
, sscreen
->b
.trace_bo
?
146 sscreen
->b
.trace_bo
->buf
: NULL
);
147 sctx
->b
.gfx
.flush
= si_context_gfx_flush
;
150 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
151 sizeof(*sctx
->border_color_table
));
152 if (!sctx
->border_color_table
)
155 sctx
->border_color_buffer
= (struct r600_resource
*)
156 pipe_buffer_create(screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_DEFAULT
,
157 SI_MAX_BORDER_COLORS
*
158 sizeof(*sctx
->border_color_table
));
159 if (!sctx
->border_color_buffer
)
162 sctx
->border_color_map
=
163 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
164 NULL
, PIPE_TRANSFER_WRITE
);
165 if (!sctx
->border_color_map
)
168 si_init_all_descriptors(sctx
);
169 si_init_state_functions(sctx
);
170 si_init_shader_functions(sctx
);
172 if (sscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
173 sctx
->b
.b
.resource_copy_region
= sctx
->b
.dma_copy
;
175 sctx
->blitter
= util_blitter_create(&sctx
->b
.b
);
176 if (sctx
->blitter
== NULL
)
178 sctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
180 sctx
->sample_mask
.sample_mask
= 0xffff;
182 /* these must be last */
183 si_begin_new_cs(sctx
);
184 r600_query_init_backend_mask(&sctx
->b
); /* this emits commands and must be last */
186 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
187 * with a NULL buffer). We need to use a dummy buffer instead. */
188 if (sctx
->b
.chip_class
== CIK
) {
189 sctx
->null_const_buf
.buffer
= pipe_buffer_create(screen
, PIPE_BIND_CONSTANT_BUFFER
,
190 PIPE_USAGE_DEFAULT
, 16);
191 if (!sctx
->null_const_buf
.buffer
)
193 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
195 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
196 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
197 sctx
->b
.b
.set_constant_buffer(&sctx
->b
.b
, shader
, i
,
198 &sctx
->null_const_buf
);
202 /* Clear the NULL constant buffer, because loads should return zeros. */
203 sctx
->b
.clear_buffer(&sctx
->b
.b
, sctx
->null_const_buf
.buffer
, 0,
204 sctx
->null_const_buf
.buffer
->width0
, 0, false);
207 /* XXX: This is the maximum value allowed. I'm not sure how to compute
208 * this for non-cs shaders. Using the wrong value here can result in
209 * GPU lockups, but the maximum value seems to always work.
211 sctx
->scratch_waves
= 32 * sscreen
->b
.info
.max_compute_units
;
213 #if HAVE_LLVM >= 0x0306
214 /* Initialize LLVM TargetMachine */
215 r600_target
= radeon_llvm_get_r600_target(triple
);
216 sctx
->tm
= LLVMCreateTargetMachine(r600_target
, triple
,
217 r600_get_llvm_processor_name(sscreen
->b
.family
),
218 "+DumpCode,+vgpr-spilling",
219 LLVMCodeGenLevelDefault
,
221 LLVMCodeModelDefault
);
226 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
227 si_destroy_context(&sctx
->b
.b
);
235 static int si_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
237 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
240 /* Supported features (boolean caps). */
241 case PIPE_CAP_TWO_SIDED_STENCIL
:
242 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
243 case PIPE_CAP_ANISOTROPIC_FILTER
:
244 case PIPE_CAP_POINT_SPRITE
:
245 case PIPE_CAP_OCCLUSION_QUERY
:
246 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
247 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
248 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
249 case PIPE_CAP_TEXTURE_SWIZZLE
:
250 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
251 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
252 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
253 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
254 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
255 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
256 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
258 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
259 case PIPE_CAP_PRIMITIVE_RESTART
:
260 case PIPE_CAP_CONDITIONAL_RENDER
:
261 case PIPE_CAP_TEXTURE_BARRIER
:
262 case PIPE_CAP_INDEP_BLEND_ENABLE
:
263 case PIPE_CAP_INDEP_BLEND_FUNC
:
264 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
265 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
266 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
267 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
268 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
269 case PIPE_CAP_USER_INDEX_BUFFERS
:
270 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
271 case PIPE_CAP_START_INSTANCE
:
272 case PIPE_CAP_NPOT_TEXTURES
:
273 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
274 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
275 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
276 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
277 case PIPE_CAP_TGSI_INSTANCEID
:
278 case PIPE_CAP_COMPUTE
:
279 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
280 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
281 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
282 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
283 case PIPE_CAP_CUBE_MAP_ARRAY
:
284 case PIPE_CAP_SAMPLE_SHADING
:
285 case PIPE_CAP_DRAW_INDIRECT
:
286 case PIPE_CAP_CLIP_HALFZ
:
287 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
288 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
289 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
290 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
291 case PIPE_CAP_TGSI_TEXCOORD
:
292 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
293 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
294 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
295 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
296 case PIPE_CAP_SHAREABLE_SHADERS
:
297 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
298 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
299 case PIPE_CAP_TEXTURE_QUERY_LOD
:
300 case PIPE_CAP_TEXTURE_GATHER_SM5
:
301 case PIPE_CAP_TGSI_TXQS
:
302 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
303 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
306 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
307 return !SI_BIG_ENDIAN
&& sscreen
->b
.info
.has_userptr
;
309 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
310 return (sscreen
->b
.info
.drm_major
== 2 &&
311 sscreen
->b
.info
.drm_minor
>= 43) ||
312 sscreen
->b
.info
.drm_major
== 3;
314 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
315 /* 2D tiling on CIK is supported since DRM 2.35.0 */
316 return sscreen
->b
.chip_class
< CIK
||
317 (sscreen
->b
.info
.drm_major
== 2 &&
318 sscreen
->b
.info
.drm_minor
>= 35) ||
319 sscreen
->b
.info
.drm_major
== 3;
321 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
322 return R600_MAP_BUFFER_ALIGNMENT
;
324 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
325 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
326 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
329 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
330 return HAVE_LLVM
>= 0x0307 ? 410 : 330;
332 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
333 return MIN2(sscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
335 /* Unsupported features. */
336 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
337 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
338 case PIPE_CAP_USER_VERTEX_BUFFERS
:
339 case PIPE_CAP_FAKE_SW_MSAA
:
340 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
341 case PIPE_CAP_VERTEXID_NOBASE
:
342 case PIPE_CAP_CLEAR_TEXTURE
:
343 case PIPE_CAP_DRAW_PARAMETERS
:
344 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
347 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
350 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
351 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
354 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
355 return sscreen
->b
.has_streamout
? 4 : 0;
356 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
357 return sscreen
->b
.has_streamout
? 1 : 0;
358 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
359 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
360 return sscreen
->b
.has_streamout
? 32*4 : 0;
362 /* Geometry shader output. */
363 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
365 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
367 case PIPE_CAP_MAX_VERTEX_STREAMS
:
370 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
374 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
375 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
376 return 15; /* 16384 */
377 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
378 /* textures support 8192, but layered rendering supports 2048 */
380 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
381 /* textures support 8192, but layered rendering supports 2048 */
384 /* Render targets. */
385 case PIPE_CAP_MAX_RENDER_TARGETS
:
388 case PIPE_CAP_MAX_VIEWPORTS
:
389 return SI_MAX_VIEWPORTS
;
391 /* Timer queries, present when the clock frequency is non zero. */
392 case PIPE_CAP_QUERY_TIMESTAMP
:
393 case PIPE_CAP_QUERY_TIME_ELAPSED
:
394 return sscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
396 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
397 case PIPE_CAP_MIN_TEXEL_OFFSET
:
400 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
401 case PIPE_CAP_MAX_TEXEL_OFFSET
:
404 case PIPE_CAP_ENDIANNESS
:
405 return PIPE_ENDIAN_LITTLE
;
407 case PIPE_CAP_VENDOR_ID
:
409 case PIPE_CAP_DEVICE_ID
:
410 return sscreen
->b
.info
.pci_id
;
411 case PIPE_CAP_ACCELERATED
:
413 case PIPE_CAP_VIDEO_MEMORY
:
414 return sscreen
->b
.info
.vram_size
>> 20;
421 static int si_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
425 case PIPE_SHADER_FRAGMENT
:
426 case PIPE_SHADER_VERTEX
:
427 case PIPE_SHADER_GEOMETRY
:
429 case PIPE_SHADER_TESS_CTRL
:
430 case PIPE_SHADER_TESS_EVAL
:
431 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
432 if (HAVE_LLVM
< 0x0306 ||
433 (HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 2))
436 case PIPE_SHADER_COMPUTE
:
438 case PIPE_SHADER_CAP_PREFERRED_IR
:
439 #if HAVE_LLVM < 0x0306
440 return PIPE_SHADER_IR_LLVM
;
442 return PIPE_SHADER_IR_NATIVE
;
444 case PIPE_SHADER_CAP_DOUBLES
:
445 return HAVE_LLVM
>= 0x0307;
447 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
448 uint64_t max_const_buffer_size
;
449 pscreen
->get_compute_param(pscreen
,
450 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
451 &max_const_buffer_size
);
452 return max_const_buffer_size
;
455 /* If compute shaders don't require a special value
456 * for this cap, we can return the same value we
457 * do for other shader types. */
466 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
467 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
468 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
469 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
471 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
473 case PIPE_SHADER_CAP_MAX_INPUTS
:
474 return shader
== PIPE_SHADER_VERTEX
? SI_NUM_VERTEX_BUFFERS
: 32;
475 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
476 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
477 case PIPE_SHADER_CAP_MAX_TEMPS
:
478 return 256; /* Max native temporaries. */
479 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
480 return 4096 * sizeof(float[4]); /* actually only memory limits this */
481 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
482 return SI_NUM_USER_CONST_BUFFERS
;
483 case PIPE_SHADER_CAP_MAX_PREDS
:
484 return 0; /* FIXME */
485 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
487 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
489 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
490 /* Indirection of geometry shader input dimension is not
493 return shader
!= PIPE_SHADER_GEOMETRY
;
494 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
495 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
496 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
498 case PIPE_SHADER_CAP_INTEGERS
:
500 case PIPE_SHADER_CAP_SUBROUTINES
:
502 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
503 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
505 case PIPE_SHADER_CAP_PREFERRED_IR
:
506 return PIPE_SHADER_IR_TGSI
;
507 case PIPE_SHADER_CAP_DOUBLES
:
508 return HAVE_LLVM
>= 0x0307;
509 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
510 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
512 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
513 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
515 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
521 static void si_destroy_screen(struct pipe_screen
* pscreen
)
523 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
528 if (!sscreen
->b
.ws
->unref(sscreen
->b
.ws
))
531 r600_destroy_common_screen(&sscreen
->b
);
534 #define SI_TILE_MODE_COLOR_2D_8BPP 14
536 /* Initialize pipe config. This is especially important for GPUs
537 * with 16 pipes and more where it's initialized incorrectly by
538 * the TILING_CONFIG ioctl. */
539 static bool si_initialize_pipe_config(struct si_screen
*sscreen
)
543 /* This is okay, because there can be no 2D tiling without
544 * the tile mode array, so we won't need the pipe config.
547 if (!sscreen
->b
.info
.si_tile_mode_array_valid
)
550 /* The same index is used for the 2D mode on CIK too. */
551 mode2d
= sscreen
->b
.info
.si_tile_mode_array
[SI_TILE_MODE_COLOR_2D_8BPP
];
553 switch (G_009910_PIPE_CONFIG(mode2d
)) {
554 case V_02803C_ADDR_SURF_P2
:
555 sscreen
->b
.tiling_info
.num_channels
= 2;
557 case V_02803C_X_ADDR_SURF_P4_8X16
:
558 case V_02803C_X_ADDR_SURF_P4_16X16
:
559 case V_02803C_X_ADDR_SURF_P4_16X32
:
560 case V_02803C_X_ADDR_SURF_P4_32X32
:
561 sscreen
->b
.tiling_info
.num_channels
= 4;
563 case V_02803C_X_ADDR_SURF_P8_16X16_8X16
:
564 case V_02803C_X_ADDR_SURF_P8_16X32_8X16
:
565 case V_02803C_X_ADDR_SURF_P8_32X32_8X16
:
566 case V_02803C_X_ADDR_SURF_P8_16X32_16X16
:
567 case V_02803C_X_ADDR_SURF_P8_32X32_16X16
:
568 case V_02803C_X_ADDR_SURF_P8_32X32_16X32
:
569 case V_02803C_X_ADDR_SURF_P8_32X64_32X32
:
570 sscreen
->b
.tiling_info
.num_channels
= 8;
572 case V_02803C_X_ADDR_SURF_P16_32X32_8X16
:
573 case V_02803C_X_ADDR_SURF_P16_32X32_16X16
:
574 sscreen
->b
.tiling_info
.num_channels
= 16;
578 fprintf(stderr
, "radeonsi: Unknown pipe config %i.\n",
579 G_009910_PIPE_CONFIG(mode2d
));
585 static bool si_init_gs_info(struct si_screen
*sscreen
)
587 switch (sscreen
->b
.family
) {
596 sscreen
->gs_table_depth
= 16;
605 sscreen
->gs_table_depth
= 32;
612 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
614 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
620 /* Set functions first. */
621 sscreen
->b
.b
.context_create
= si_create_context
;
622 sscreen
->b
.b
.destroy
= si_destroy_screen
;
623 sscreen
->b
.b
.get_param
= si_get_param
;
624 sscreen
->b
.b
.get_shader_param
= si_get_shader_param
;
625 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
626 sscreen
->b
.b
.resource_create
= r600_resource_create_common
;
628 if (!r600_common_screen_init(&sscreen
->b
, ws
) ||
629 !si_initialize_pipe_config(sscreen
) ||
630 !si_init_gs_info(sscreen
)) {
635 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE
))
636 si_init_perfcounters(sscreen
);
638 sscreen
->b
.has_cp_dma
= true;
639 sscreen
->b
.has_streamout
= true;
641 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
))
642 sscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
644 /* Create the auxiliary context. This must be done last. */
645 sscreen
->b
.aux_context
= sscreen
->b
.b
.context_create(&sscreen
->b
.b
, NULL
, 0);
647 return &sscreen
->b
.b
;