src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_suballoc.h"
  32 #include "vl/vl_decoder.h"
  33 #include "../ddebug/dd_util.h"
  34
  35 #define SI_LLVM_DEFAULT_FEATURES \
  36         "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
  37
  38 /*
  39  * pipe_context
  40  */
  41 static void si_destroy_context(struct pipe_context *context)
  42 {
  43         struct si_context *sctx = (struct si_context *)context;
  44         int i;
  45
  46         /* Unreference the framebuffer normally to disable related logic
  47          * properly.
  48          */
  49         struct pipe_framebuffer_state fb = {};
  50         context->set_framebuffer_state(context, &fb);
  51
  52         si_release_all_descriptors(sctx);
  53
  54         if (sctx->ce_suballocator)
  55                 u_suballocator_destroy(sctx->ce_suballocator);
  56
  57         pipe_resource_reference(&sctx->esgs_ring, NULL);
  58         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  59         pipe_resource_reference(&sctx->tf_ring, NULL);
  60         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  61         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  62         r600_resource_reference(&sctx->border_color_buffer, NULL);
  63         free(sctx->border_color_table);
  64         r600_resource_reference(&sctx->scratch_buffer, NULL);
  65         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  66
  67         si_pm4_free_state(sctx, sctx->init_config, ~0);
  68         if (sctx->init_config_gs_rings)
  69                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  70         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  71                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  72
  73         if (sctx->fixed_func_tcs_shader.cso)
  74                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  75         if (sctx->custom_dsa_flush)
  76                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  77         if (sctx->custom_blend_resolve)
  78                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  79         if (sctx->custom_blend_decompress)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  81         if (sctx->custom_blend_fastclear)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  83         if (sctx->custom_blend_dcc_decompress)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  85
  86         if (sctx->blitter)
  87                 util_blitter_destroy(sctx->blitter);
  88
  89         r600_common_context_cleanup(&sctx->b);
  90
  91         LLVMDisposeTargetMachine(sctx->tm);
  92
  93         r600_resource_reference(&sctx->trace_buf, NULL);
  94         r600_resource_reference(&sctx->last_trace_buf, NULL);
  95         radeon_clear_saved_cs(&sctx->last_gfx);
  96
  97         FREE(sctx);
  98 }
  99
 100 static enum pipe_reset_status
 101 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 102 {
 103         struct si_context *sctx = (struct si_context *)ctx;
 104
 105         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 106 }
 107
 108 /* Apitrace profiling:
 109  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 110  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 111  *      and remember its number.
 112  *   3) In Mesa, enable queries and performance counters around that draw
 113  *      call and print the results.
 114  *   4) glretrace --benchmark --markers ..
 115  */
 116 static void si_emit_string_marker(struct pipe_context *ctx,
 117                                   const char *string, int len)
 118 {
 119         struct si_context *sctx = (struct si_context *)ctx;
 120
 121         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 122 }
 123
 124 static LLVMTargetMachineRef
 125 si_create_llvm_target_machine(struct si_screen *sscreen)
 126 {
 127         const char *triple = "amdgcn--";
 128
 129         return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
 130                                        r600_get_llvm_processor_name(sscreen->b.family),
 131 #if HAVE_LLVM >= 0x0308
 132                                        sscreen->b.debug_flags & DBG_SI_SCHED ?
 133                                                SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 134 #endif
 135                                                SI_LLVM_DEFAULT_FEATURES,
 136                                        LLVMCodeGenLevelDefault,
 137                                        LLVMRelocDefault,
 138                                        LLVMCodeModelDefault);
 139 }
 140
 141 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 142                                               void *priv, unsigned flags)
 143 {
 144         struct si_context *sctx = CALLOC_STRUCT(si_context);
 145         struct si_screen* sscreen = (struct si_screen *)screen;
 146         struct radeon_winsys *ws = sscreen->b.ws;
 147         int shader, i;
 148
 149         if (!sctx)
 150                 return NULL;
 151
 152         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 153                 flags |= PIPE_CONTEXT_DEBUG;
 154
 155         if (flags & PIPE_CONTEXT_DEBUG)
 156                 sscreen->record_llvm_ir = true; /* racy but not critical */
 157
 158         sctx->b.b.screen = screen; /* this must be set first */
 159         sctx->b.b.priv = priv;
 160         sctx->b.b.destroy = si_destroy_context;
 161         sctx->b.b.emit_string_marker = si_emit_string_marker;
 162         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 163         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 164         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 165
 166         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 167                 goto fail;
 168
 169         if (sscreen->b.info.drm_major == 3)
 170                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 171
 172         si_init_blit_functions(sctx);
 173         si_init_compute_functions(sctx);
 174         si_init_cp_dma_functions(sctx);
 175         si_init_debug_functions(sctx);
 176
 177         if (sscreen->b.info.has_uvd) {
 178                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 179                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 180         } else {
 181                 sctx->b.b.create_video_codec = vl_create_decoder;
 182                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 183         }
 184
 185         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 186                                        si_context_gfx_flush, sctx);
 187
 188         /* SI + AMDGPU + CE = GPU hang */
 189         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 190             sscreen->b.chip_class != SI &&
 191             /* These can't use CE due to a power gating bug in the kernel. */
 192             sscreen->b.family != CHIP_CARRIZO &&
 193             sscreen->b.family != CHIP_STONEY) {
 194                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 195                 if (!sctx->ce_ib)
 196                         goto fail;
 197
 198                 if (ws->cs_add_const_preamble_ib) {
 199                         sctx->ce_preamble_ib =
 200                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 201
 202                         if (!sctx->ce_preamble_ib)
 203                                 goto fail;
 204                 }
 205
 206                 sctx->ce_suballocator =
 207                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 208                                               PIPE_USAGE_DEFAULT,
 209                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 210                 if (!sctx->ce_suballocator)
 211                         goto fail;
 212         }
 213
 214         sctx->b.gfx.flush = si_context_gfx_flush;
 215
 216         /* Border colors. */
 217         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 218                                           sizeof(*sctx->border_color_table));
 219         if (!sctx->border_color_table)
 220                 goto fail;
 221
 222         sctx->border_color_buffer = (struct r600_resource*)
 223                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 224                                    SI_MAX_BORDER_COLORS *
 225                                    sizeof(*sctx->border_color_table));
 226         if (!sctx->border_color_buffer)
 227                 goto fail;
 228
 229         sctx->border_color_map =
 230                 ws->buffer_map(sctx->border_color_buffer->buf,
 231                                NULL, PIPE_TRANSFER_WRITE);
 232         if (!sctx->border_color_map)
 233                 goto fail;
 234
 235         si_init_all_descriptors(sctx);
 236         si_init_state_functions(sctx);
 237         si_init_shader_functions(sctx);
 238         si_init_ia_multi_vgt_param_table(sctx);
 239
 240         if (sctx->b.chip_class >= CIK)
 241                 cik_init_sdma_functions(sctx);
 242         else
 243                 si_init_dma_functions(sctx);
 244
 245         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 246                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 247
 248         sctx->blitter = util_blitter_create(&sctx->b.b);
 249         if (sctx->blitter == NULL)
 250                 goto fail;
 251         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 252
 253         sctx->sample_mask.sample_mask = 0xffff;
 254
 255         /* these must be last */
 256         si_begin_new_cs(sctx);
 257
 258         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 259          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 260         if (sctx->b.chip_class == CIK) {
 261                 sctx->null_const_buf.buffer =
 262                         r600_aligned_buffer_create(screen,
 263                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 264                                                    PIPE_USAGE_DEFAULT, 16,
 265                                                    sctx->screen->b.info.tcc_cache_line_size);
 266                 if (!sctx->null_const_buf.buffer)
 267                         goto fail;
 268                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 269
 270                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 271                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 272                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 273                                                               &sctx->null_const_buf);
 274                         }
 275                 }
 276
 277                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 278                                  &sctx->null_const_buf);
 279                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 280                                  &sctx->null_const_buf);
 281                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 282                                  &sctx->null_const_buf);
 283                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 284                                  &sctx->null_const_buf);
 285
 286                 /* Clear the NULL constant buffer, because loads should return zeros. */
 287                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 288                                      sctx->null_const_buf.buffer->width0, 0,
 289                                      R600_COHERENCY_SHADER);
 290         }
 291
 292         uint64_t max_threads_per_block;
 293         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 294                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 295                                   &max_threads_per_block);
 296
 297         /* The maximum number of scratch waves. Scratch space isn't divided
 298          * evenly between CUs. The number is only a function of the number of CUs.
 299          * We can decrease the constant to decrease the scratch buffer size.
 300          *
 301          * sctx->scratch_waves must be >= the maximum posible size of
 302          * 1 threadgroup, so that the hw doesn't hang from being unable
 303          * to start any.
 304          *
 305          * The recommended value is 4 per CU at most. Higher numbers don't
 306          * bring much benefit, but they still occupy chip resources (think
 307          * async compute). I've seen ~2% performance difference between 4 and 32.
 308          */
 309         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 310                                    max_threads_per_block / 64);
 311
 312         sctx->tm = si_create_llvm_target_machine(sscreen);
 313
 314         return &sctx->b.b;
 315 fail:
 316         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 317         si_destroy_context(&sctx->b.b);
 318         return NULL;
 319 }
 320
 321 /*
 322  * pipe_screen
 323  */
 324 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 325 {
 326         /* Old kernels disallowed some register writes for SI
 327          * that are used for indirect dispatches. */
 328         return HAVE_LLVM >= 0x309 &&
 329                (sscreen->b.chip_class >= CIK ||
 330                 sscreen->b.info.drm_major == 3 ||
 331                 (sscreen->b.info.drm_major == 2 &&
 332                  sscreen->b.info.drm_minor >= 45));
 333 }
 334
 335 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 336 {
 337         struct si_screen *sscreen = (struct si_screen *)pscreen;
 338
 339         switch (param) {
 340         /* Supported features (boolean caps). */
 341         case PIPE_CAP_ACCELERATED:
 342         case PIPE_CAP_TWO_SIDED_STENCIL:
 343         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 344         case PIPE_CAP_ANISOTROPIC_FILTER:
 345         case PIPE_CAP_POINT_SPRITE:
 346         case PIPE_CAP_OCCLUSION_QUERY:
 347         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 348         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 349         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 350         case PIPE_CAP_TEXTURE_SWIZZLE:
 351         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 352         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 353         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 354         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 355         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 356         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 357         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 358         case PIPE_CAP_SM3:
 359         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 360         case PIPE_CAP_PRIMITIVE_RESTART:
 361         case PIPE_CAP_CONDITIONAL_RENDER:
 362         case PIPE_CAP_TEXTURE_BARRIER:
 363         case PIPE_CAP_INDEP_BLEND_ENABLE:
 364         case PIPE_CAP_INDEP_BLEND_FUNC:
 365         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 366         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 367         case PIPE_CAP_USER_INDEX_BUFFERS:
 368         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 369         case PIPE_CAP_START_INSTANCE:
 370         case PIPE_CAP_NPOT_TEXTURES:
 371         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 372         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 373         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 374         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 375         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 376         case PIPE_CAP_TGSI_INSTANCEID:
 377         case PIPE_CAP_COMPUTE:
 378         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 379         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 380         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 381         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 382         case PIPE_CAP_CUBE_MAP_ARRAY:
 383         case PIPE_CAP_SAMPLE_SHADING:
 384         case PIPE_CAP_DRAW_INDIRECT:
 385         case PIPE_CAP_CLIP_HALFZ:
 386         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 387         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 388         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 389         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 390         case PIPE_CAP_TGSI_TEXCOORD:
 391         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 392         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 393         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 394         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 395         case PIPE_CAP_SHAREABLE_SHADERS:
 396         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 397         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 398         case PIPE_CAP_TEXTURE_QUERY_LOD:
 399         case PIPE_CAP_TEXTURE_GATHER_SM5:
 400         case PIPE_CAP_TGSI_TXQS:
 401         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 402         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 403         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 404         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 405         case PIPE_CAP_INVALIDATE_BUFFER:
 406         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 407         case PIPE_CAP_QUERY_MEMORY_INFO:
 408         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 409         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 410         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 411         case PIPE_CAP_GENERATE_MIPMAP:
 412         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 413         case PIPE_CAP_STRING_MARKER:
 414         case PIPE_CAP_CLEAR_TEXTURE:
 415         case PIPE_CAP_CULL_DISTANCE:
 416         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 417         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 418         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 419         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 420         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 421                 return 1;
 422
 423         case PIPE_CAP_DOUBLES:
 424                 return HAVE_LLVM >= 0x0307;
 425         case PIPE_CAP_INT64:
 426         case PIPE_CAP_INT64_DIVMOD:
 427                 return HAVE_LLVM >= 0x0309;
 428
 429         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 430                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 431
 432         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 433                 return (sscreen->b.info.drm_major == 2 &&
 434                         sscreen->b.info.drm_minor >= 43) ||
 435                        sscreen->b.info.drm_major == 3;
 436
 437         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 438                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 439                 return sscreen->b.chip_class < CIK ||
 440                        (sscreen->b.info.drm_major == 2 &&
 441                         sscreen->b.info.drm_minor >= 35) ||
 442                        sscreen->b.info.drm_major == 3;
 443
 444         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 445                 return R600_MAP_BUFFER_ALIGNMENT;
 446
 447         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 448         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 449         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 450         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 451         case PIPE_CAP_MAX_VERTEX_STREAMS:
 452                 return 4;
 453
 454         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 455                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 456
 457         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 458                 if (si_have_tgsi_compute(sscreen))
 459                         return 450;
 460                 return HAVE_LLVM >= 0x0309 ? 420 :
 461                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 462
 463         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 464                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 465
 466         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 467         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 468         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 469                 /* SI doesn't support unaligned loads.
 470                  * CIK needs DRM 2.50.0 on radeon. */
 471                 return sscreen->b.chip_class == SI ||
 472                        (sscreen->b.info.drm_major == 2 &&
 473                         sscreen->b.info.drm_minor < 50);
 474
 475         /* Unsupported features. */
 476         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 477         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 478         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 479         case PIPE_CAP_USER_VERTEX_BUFFERS:
 480         case PIPE_CAP_FAKE_SW_MSAA:
 481         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 482         case PIPE_CAP_VERTEXID_NOBASE:
 483         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 484         case PIPE_CAP_TGSI_VOTE:
 485         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 486         case PIPE_CAP_NATIVE_FENCE_FD:
 487         case PIPE_CAP_TGSI_FS_FBFETCH:
 488         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 489         case PIPE_CAP_UMA:
 490                 return 0;
 491
 492         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 493                 return si_have_tgsi_compute(sscreen);
 494
 495         case PIPE_CAP_DRAW_PARAMETERS:
 496         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 497         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 498                 return sscreen->has_draw_indirect_multi;
 499
 500         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 501                 return 30;
 502
 503         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 504                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 505
 506         /* Stream output. */
 507         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 508         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 509                 return 32*4;
 510
 511         /* Geometry shader output. */
 512         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 513                 return 1024;
 514         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 515                 return 4095;
 516
 517         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 518                 return 2048;
 519
 520         /* Texturing. */
 521         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 522         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 523                 return 15; /* 16384 */
 524         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 525                 /* textures support 8192, but layered rendering supports 2048 */
 526                 return 12;
 527         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 528                 /* textures support 8192, but layered rendering supports 2048 */
 529                 return 2048;
 530
 531         /* Viewports and render targets. */
 532         case PIPE_CAP_MAX_VIEWPORTS:
 533                 return R600_MAX_VIEWPORTS;
 534         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 535         case PIPE_CAP_MAX_RENDER_TARGETS:
 536                 return 8;
 537
 538         /* Timer queries, present when the clock frequency is non zero. */
 539         case PIPE_CAP_QUERY_TIMESTAMP:
 540         case PIPE_CAP_QUERY_TIME_ELAPSED:
 541                 return sscreen->b.info.clock_crystal_freq != 0;
 542
 543         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 544         case PIPE_CAP_MIN_TEXEL_OFFSET:
 545                 return -32;
 546
 547         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 548         case PIPE_CAP_MAX_TEXEL_OFFSET:
 549                 return 31;
 550
 551         case PIPE_CAP_ENDIANNESS:
 552                 return PIPE_ENDIAN_LITTLE;
 553
 554         case PIPE_CAP_VENDOR_ID:
 555                 return ATI_VENDOR_ID;
 556         case PIPE_CAP_DEVICE_ID:
 557                 return sscreen->b.info.pci_id;
 558         case PIPE_CAP_VIDEO_MEMORY:
 559                 return sscreen->b.info.vram_size >> 20;
 560         case PIPE_CAP_PCI_GROUP:
 561                 return sscreen->b.info.pci_domain;
 562         case PIPE_CAP_PCI_BUS:
 563                 return sscreen->b.info.pci_bus;
 564         case PIPE_CAP_PCI_DEVICE:
 565                 return sscreen->b.info.pci_dev;
 566         case PIPE_CAP_PCI_FUNCTION:
 567                 return sscreen->b.info.pci_func;
 568         }
 569         return 0;
 570 }
 571
 572 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 573 {
 574         struct si_screen *sscreen = (struct si_screen *)pscreen;
 575
 576         switch(shader)
 577         {
 578         case PIPE_SHADER_FRAGMENT:
 579         case PIPE_SHADER_VERTEX:
 580         case PIPE_SHADER_GEOMETRY:
 581                 break;
 582         case PIPE_SHADER_TESS_CTRL:
 583         case PIPE_SHADER_TESS_EVAL:
 584                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 585                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 586                         return 0;
 587                 break;
 588         case PIPE_SHADER_COMPUTE:
 589                 switch (param) {
 590                 case PIPE_SHADER_CAP_PREFERRED_IR:
 591                         return PIPE_SHADER_IR_NATIVE;
 592
 593                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 594                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 595
 596                         if (si_have_tgsi_compute(sscreen))
 597                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 598
 599                         return ir;
 600                 }
 601
 602                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 603                         uint64_t max_const_buffer_size;
 604                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 605                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 606                                 &max_const_buffer_size);
 607                         return MIN2(max_const_buffer_size, INT_MAX);
 608                 }
 609                 default:
 610                         /* If compute shaders don't require a special value
 611                          * for this cap, we can return the same value we
 612                          * do for other shader types. */
 613                         break;
 614                 }
 615                 break;
 616         default:
 617                 return 0;
 618         }
 619
 620         switch (param) {
 621         /* Shader limits. */
 622         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 623         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 624         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 625         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 626         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 627                 return 16384;
 628         case PIPE_SHADER_CAP_MAX_INPUTS:
 629                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 630         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 631                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 632         case PIPE_SHADER_CAP_MAX_TEMPS:
 633                 return 256; /* Max native temporaries. */
 634         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 635                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 636         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 637                 return SI_NUM_CONST_BUFFERS;
 638         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 639         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 640                 return SI_NUM_SAMPLERS;
 641         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 642                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 643         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 644                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 645         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 646                 return 32;
 647         case PIPE_SHADER_CAP_PREFERRED_IR:
 648                 return PIPE_SHADER_IR_TGSI;
 649         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 650                 return 3;
 651
 652         /* Supported boolean features. */
 653         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 654         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 655         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 656         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 657         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 658         case PIPE_SHADER_CAP_INTEGERS:
 659         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 660         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 661                 return 1;
 662
 663         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 664                 /* TODO: Indirection of geometry shader input dimension is not
 665                  * handled yet
 666                  */
 667                 return shader != PIPE_SHADER_GEOMETRY;
 668
 669         /* Unsupported boolean features. */
 670         case PIPE_SHADER_CAP_MAX_PREDS:
 671         case PIPE_SHADER_CAP_SUBROUTINES:
 672         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 673         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 674         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 675                 return 0;
 676         }
 677         return 0;
 678 }
 679
 680 static void si_destroy_screen(struct pipe_screen* pscreen)
 681 {
 682         struct si_screen *sscreen = (struct si_screen *)pscreen;
 683         struct si_shader_part *parts[] = {
 684                 sscreen->vs_prologs,
 685                 sscreen->vs_epilogs,
 686                 sscreen->tcs_epilogs,
 687                 sscreen->gs_prologs,
 688                 sscreen->ps_prologs,
 689                 sscreen->ps_epilogs
 690         };
 691         unsigned i;
 692
 693         if (!sscreen)
 694                 return;
 695
 696         if (!sscreen->b.ws->unref(sscreen->b.ws))
 697                 return;
 698
 699         if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
 700                 util_queue_destroy(&sscreen->shader_compiler_queue);
 701
 702         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 703                 if (sscreen->tm[i])
 704                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 705
 706         /* Free shader parts. */
 707         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 708                 while (parts[i]) {
 709                         struct si_shader_part *part = parts[i];
 710
 711                         parts[i] = part->next;
 712                         radeon_shader_binary_clean(&part->binary);
 713                         FREE(part);
 714                 }
 715         }
 716         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 717         si_destroy_shader_cache(sscreen);
 718         r600_destroy_common_screen(&sscreen->b);
 719 }
 720
 721 static bool si_init_gs_info(struct si_screen *sscreen)
 722 {
 723         switch (sscreen->b.family) {
 724         case CHIP_OLAND:
 725         case CHIP_HAINAN:
 726         case CHIP_KAVERI:
 727         case CHIP_KABINI:
 728         case CHIP_MULLINS:
 729         case CHIP_ICELAND:
 730         case CHIP_CARRIZO:
 731         case CHIP_STONEY:
 732                 sscreen->gs_table_depth = 16;
 733                 return true;
 734         case CHIP_TAHITI:
 735         case CHIP_PITCAIRN:
 736         case CHIP_VERDE:
 737         case CHIP_BONAIRE:
 738         case CHIP_HAWAII:
 739         case CHIP_TONGA:
 740         case CHIP_FIJI:
 741         case CHIP_POLARIS10:
 742         case CHIP_POLARIS11:
 743         case CHIP_POLARIS12:
 744                 sscreen->gs_table_depth = 32;
 745                 return true;
 746         default:
 747                 return false;
 748         }
 749 }
 750
 751 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 752 {
 753         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 754         unsigned i;
 755
 756         if (!family)
 757                 return;
 758
 759         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 760                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 761                         /* Override family and chip_class. */
 762                         sscreen->b.family = sscreen->b.info.family = i;
 763
 764                         if (i >= CHIP_TONGA)
 765                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 766                         else if (i >= CHIP_BONAIRE)
 767                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 768                         else
 769                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 770
 771                         /* Don't submit any IBs. */
 772                         setenv("RADEON_NOOP", "1", 1);
 773                         return;
 774                 }
 775         }
 776
 777         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 778         exit(1);
 779 }
 780
 781 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 782 {
 783         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 784         unsigned num_cpus, num_compiler_threads, i;
 785
 786         if (!sscreen) {
 787                 return NULL;
 788         }
 789
 790         /* Set functions first. */
 791         sscreen->b.b.context_create = si_create_context;
 792         sscreen->b.b.destroy = si_destroy_screen;
 793         sscreen->b.b.get_param = si_get_param;
 794         sscreen->b.b.get_shader_param = si_get_shader_param;
 795         sscreen->b.b.resource_create = r600_resource_create_common;
 796
 797         si_init_screen_state_functions(sscreen);
 798
 799         if (!r600_common_screen_init(&sscreen->b, ws) ||
 800             !si_init_gs_info(sscreen) ||
 801             !si_init_shader_cache(sscreen)) {
 802                 FREE(sscreen);
 803                 return NULL;
 804         }
 805
 806         si_handle_env_var_force_family(sscreen);
 807
 808         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 809                 si_init_perfcounters(sscreen);
 810
 811         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 812          * around by setting 4K granularity.
 813          */
 814         sscreen->tess_offchip_block_dw_size =
 815                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 816
 817         sscreen->has_distributed_tess =
 818                 sscreen->b.chip_class >= VI &&
 819                 sscreen->b.info.max_se >= 2;
 820
 821         sscreen->has_draw_indirect_multi =
 822                 (sscreen->b.family >= CHIP_POLARIS10) ||
 823                 (sscreen->b.chip_class == VI &&
 824                  sscreen->b.info.pfp_fw_version >= 121 &&
 825                  sscreen->b.info.me_fw_version >= 87) ||
 826                 (sscreen->b.chip_class == CIK &&
 827                  sscreen->b.info.pfp_fw_version >= 211 &&
 828                  sscreen->b.info.me_fw_version >= 173) ||
 829                 (sscreen->b.chip_class == SI &&
 830                  sscreen->b.info.pfp_fw_version >= 121 &&
 831                  sscreen->b.info.me_fw_version >= 87);
 832
 833         sscreen->has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
 834                                    sscreen->b.chip_class >= VI;
 835
 836         sscreen->b.has_cp_dma = true;
 837         sscreen->b.has_streamout = true;
 838         pipe_mutex_init(sscreen->shader_parts_mutex);
 839         sscreen->use_monolithic_shaders =
 840                 HAVE_LLVM < 0x0308 ||
 841                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 842
 843         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
 844                                             SI_CONTEXT_INV_VMEM_L1 |
 845                                             SI_CONTEXT_INV_GLOBAL_L2;
 846         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
 847
 848         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 849                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 850
 851         /* Only enable as many threads as we have target machines and CPUs. */
 852         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 853         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 854
 855         for (i = 0; i < num_compiler_threads; i++)
 856                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 857
 858         util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 859                         32, num_compiler_threads);
 860
 861         /* Create the auxiliary context. This must be done last. */
 862         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 863
 864         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 865                 r600_test_dma(&sscreen->b);
 866
 867         return &sscreen->b.b;
 868 }