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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "util/u_suballoc.h"
32 #include "vl/vl_decoder.h"
33 #include "../ddebug/dd_util.h"
34
35 #define SI_LLVM_DEFAULT_FEATURES \
36 "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
37
38 /*
39 * pipe_context
40 */
41 static void si_destroy_context(struct pipe_context *context)
42 {
43 struct si_context *sctx = (struct si_context *)context;
44 int i;
45
46 /* Unreference the framebuffer normally to disable related logic
47 * properly.
48 */
49 struct pipe_framebuffer_state fb = {};
50 context->set_framebuffer_state(context, &fb);
51
52 si_release_all_descriptors(sctx);
53
54 if (sctx->ce_suballocator)
55 u_suballocator_destroy(sctx->ce_suballocator);
56
57 pipe_resource_reference(&sctx->esgs_ring, NULL);
58 pipe_resource_reference(&sctx->gsvs_ring, NULL);
59 pipe_resource_reference(&sctx->tf_ring, NULL);
60 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
61 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
62 r600_resource_reference(&sctx->border_color_buffer, NULL);
63 free(sctx->border_color_table);
64 r600_resource_reference(&sctx->scratch_buffer, NULL);
65 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
66
67 si_pm4_free_state(sctx, sctx->init_config, ~0);
68 if (sctx->init_config_gs_rings)
69 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
70 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
71 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
72
73 if (sctx->fixed_func_tcs_shader.cso)
74 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
75 if (sctx->custom_dsa_flush)
76 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
77 if (sctx->custom_blend_resolve)
78 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
79 if (sctx->custom_blend_decompress)
80 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
81 if (sctx->custom_blend_fastclear)
82 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
83 if (sctx->custom_blend_dcc_decompress)
84 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
85
86 if (sctx->blitter)
87 util_blitter_destroy(sctx->blitter);
88
89 r600_common_context_cleanup(&sctx->b);
90
91 LLVMDisposeTargetMachine(sctx->tm);
92
93 r600_resource_reference(&sctx->trace_buf, NULL);
94 r600_resource_reference(&sctx->last_trace_buf, NULL);
95 radeon_clear_saved_cs(&sctx->last_gfx);
96
97 FREE(sctx);
98 }
99
100 static enum pipe_reset_status
101 si_amdgpu_get_reset_status(struct pipe_context *ctx)
102 {
103 struct si_context *sctx = (struct si_context *)ctx;
104
105 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
106 }
107
108 /* Apitrace profiling:
109 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
110 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
111 * and remember its number.
112 * 3) In Mesa, enable queries and performance counters around that draw
113 * call and print the results.
114 * 4) glretrace --benchmark --markers ..
115 */
116 static void si_emit_string_marker(struct pipe_context *ctx,
117 const char *string, int len)
118 {
119 struct si_context *sctx = (struct si_context *)ctx;
120
121 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
122 }
123
124 static LLVMTargetMachineRef
125 si_create_llvm_target_machine(struct si_screen *sscreen)
126 {
127 const char *triple = "amdgcn--";
128
129 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
130 r600_get_llvm_processor_name(sscreen->b.family),
131 sscreen->b.debug_flags & DBG_SI_SCHED ?
132 SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
133 SI_LLVM_DEFAULT_FEATURES,
134 LLVMCodeGenLevelDefault,
135 LLVMRelocDefault,
136 LLVMCodeModelDefault);
137 }
138
139 static struct pipe_context *si_create_context(struct pipe_screen *screen,
140 void *priv, unsigned flags)
141 {
142 struct si_context *sctx = CALLOC_STRUCT(si_context);
143 struct si_screen* sscreen = (struct si_screen *)screen;
144 struct radeon_winsys *ws = sscreen->b.ws;
145 int shader, i;
146
147 if (!sctx)
148 return NULL;
149
150 if (sscreen->b.debug_flags & DBG_CHECK_VM)
151 flags |= PIPE_CONTEXT_DEBUG;
152
153 if (flags & PIPE_CONTEXT_DEBUG)
154 sscreen->record_llvm_ir = true; /* racy but not critical */
155
156 sctx->b.b.screen = screen; /* this must be set first */
157 sctx->b.b.priv = priv;
158 sctx->b.b.destroy = si_destroy_context;
159 sctx->b.b.emit_string_marker = si_emit_string_marker;
160 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
161 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
162 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
163
164 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
165 goto fail;
166
167 if (sscreen->b.info.drm_major == 3)
168 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
169
170 si_init_blit_functions(sctx);
171 si_init_compute_functions(sctx);
172 si_init_cp_dma_functions(sctx);
173 si_init_debug_functions(sctx);
174
175 if (sscreen->b.info.has_uvd) {
176 sctx->b.b.create_video_codec = si_uvd_create_decoder;
177 sctx->b.b.create_video_buffer = si_video_buffer_create;
178 } else {
179 sctx->b.b.create_video_codec = vl_create_decoder;
180 sctx->b.b.create_video_buffer = vl_video_buffer_create;
181 }
182
183 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
184 si_context_gfx_flush, sctx);
185
186 /* SI + AMDGPU + CE = GPU hang */
187 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
188 sscreen->b.chip_class != SI &&
189 /* These can't use CE due to a power gating bug in the kernel. */
190 sscreen->b.family != CHIP_CARRIZO &&
191 sscreen->b.family != CHIP_STONEY) {
192 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
193 if (!sctx->ce_ib)
194 goto fail;
195
196 if (ws->cs_add_const_preamble_ib) {
197 sctx->ce_preamble_ib =
198 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
199
200 if (!sctx->ce_preamble_ib)
201 goto fail;
202 }
203
204 sctx->ce_suballocator =
205 u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
206 PIPE_USAGE_DEFAULT,
207 R600_RESOURCE_FLAG_UNMAPPABLE, false);
208 if (!sctx->ce_suballocator)
209 goto fail;
210 }
211
212 sctx->b.gfx.flush = si_context_gfx_flush;
213
214 /* Border colors. */
215 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
216 sizeof(*sctx->border_color_table));
217 if (!sctx->border_color_table)
218 goto fail;
219
220 sctx->border_color_buffer = (struct r600_resource*)
221 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
222 SI_MAX_BORDER_COLORS *
223 sizeof(*sctx->border_color_table));
224 if (!sctx->border_color_buffer)
225 goto fail;
226
227 sctx->border_color_map =
228 ws->buffer_map(sctx->border_color_buffer->buf,
229 NULL, PIPE_TRANSFER_WRITE);
230 if (!sctx->border_color_map)
231 goto fail;
232
233 si_init_all_descriptors(sctx);
234 si_init_state_functions(sctx);
235 si_init_shader_functions(sctx);
236 si_init_ia_multi_vgt_param_table(sctx);
237
238 if (sctx->b.chip_class >= CIK)
239 cik_init_sdma_functions(sctx);
240 else
241 si_init_dma_functions(sctx);
242
243 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
244 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
245
246 sctx->blitter = util_blitter_create(&sctx->b.b);
247 if (sctx->blitter == NULL)
248 goto fail;
249 sctx->blitter->draw_rectangle = r600_draw_rectangle;
250
251 sctx->sample_mask.sample_mask = 0xffff;
252
253 /* these must be last */
254 si_begin_new_cs(sctx);
255
256 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
257 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
258 if (sctx->b.chip_class == CIK) {
259 sctx->null_const_buf.buffer =
260 r600_aligned_buffer_create(screen,
261 R600_RESOURCE_FLAG_UNMAPPABLE,
262 PIPE_USAGE_DEFAULT, 16,
263 sctx->screen->b.info.tcc_cache_line_size);
264 if (!sctx->null_const_buf.buffer)
265 goto fail;
266 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
267
268 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
269 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
270 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
271 &sctx->null_const_buf);
272 }
273 }
274
275 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
276 &sctx->null_const_buf);
277 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
278 &sctx->null_const_buf);
279 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
280 &sctx->null_const_buf);
281 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
282 &sctx->null_const_buf);
283
284 /* Clear the NULL constant buffer, because loads should return zeros. */
285 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
286 sctx->null_const_buf.buffer->width0, 0,
287 R600_COHERENCY_SHADER);
288 }
289
290 uint64_t max_threads_per_block;
291 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
292 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
293 &max_threads_per_block);
294
295 /* The maximum number of scratch waves. Scratch space isn't divided
296 * evenly between CUs. The number is only a function of the number of CUs.
297 * We can decrease the constant to decrease the scratch buffer size.
298 *
299 * sctx->scratch_waves must be >= the maximum posible size of
300 * 1 threadgroup, so that the hw doesn't hang from being unable
301 * to start any.
302 *
303 * The recommended value is 4 per CU at most. Higher numbers don't
304 * bring much benefit, but they still occupy chip resources (think
305 * async compute). I've seen ~2% performance difference between 4 and 32.
306 */
307 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
308 max_threads_per_block / 64);
309
310 sctx->tm = si_create_llvm_target_machine(sscreen);
311
312 return &sctx->b.b;
313 fail:
314 fprintf(stderr, "radeonsi: Failed to create a context.\n");
315 si_destroy_context(&sctx->b.b);
316 return NULL;
317 }
318
319 /*
320 * pipe_screen
321 */
322 static bool si_have_tgsi_compute(struct si_screen *sscreen)
323 {
324 /* Old kernels disallowed some register writes for SI
325 * that are used for indirect dispatches. */
326 return HAVE_LLVM >= 0x309 &&
327 (sscreen->b.chip_class >= CIK ||
328 sscreen->b.info.drm_major == 3 ||
329 (sscreen->b.info.drm_major == 2 &&
330 sscreen->b.info.drm_minor >= 45));
331 }
332
333 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
334 {
335 struct si_screen *sscreen = (struct si_screen *)pscreen;
336
337 switch (param) {
338 /* Supported features (boolean caps). */
339 case PIPE_CAP_ACCELERATED:
340 case PIPE_CAP_TWO_SIDED_STENCIL:
341 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
342 case PIPE_CAP_ANISOTROPIC_FILTER:
343 case PIPE_CAP_POINT_SPRITE:
344 case PIPE_CAP_OCCLUSION_QUERY:
345 case PIPE_CAP_TEXTURE_SHADOW_MAP:
346 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
347 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
348 case PIPE_CAP_TEXTURE_SWIZZLE:
349 case PIPE_CAP_DEPTH_CLIP_DISABLE:
350 case PIPE_CAP_SHADER_STENCIL_EXPORT:
351 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
352 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
353 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
354 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
355 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
356 case PIPE_CAP_SM3:
357 case PIPE_CAP_SEAMLESS_CUBE_MAP:
358 case PIPE_CAP_PRIMITIVE_RESTART:
359 case PIPE_CAP_CONDITIONAL_RENDER:
360 case PIPE_CAP_TEXTURE_BARRIER:
361 case PIPE_CAP_INDEP_BLEND_ENABLE:
362 case PIPE_CAP_INDEP_BLEND_FUNC:
363 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
364 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
365 case PIPE_CAP_USER_CONSTANT_BUFFERS:
366 case PIPE_CAP_START_INSTANCE:
367 case PIPE_CAP_NPOT_TEXTURES:
368 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
369 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
370 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
371 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
372 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
373 case PIPE_CAP_TGSI_INSTANCEID:
374 case PIPE_CAP_COMPUTE:
375 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
376 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
377 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
378 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
379 case PIPE_CAP_CUBE_MAP_ARRAY:
380 case PIPE_CAP_SAMPLE_SHADING:
381 case PIPE_CAP_DRAW_INDIRECT:
382 case PIPE_CAP_CLIP_HALFZ:
383 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
384 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
385 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
386 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
387 case PIPE_CAP_TGSI_TEXCOORD:
388 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
389 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
390 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
391 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
392 case PIPE_CAP_SHAREABLE_SHADERS:
393 case PIPE_CAP_DEPTH_BOUNDS_TEST:
394 case PIPE_CAP_SAMPLER_VIEW_TARGET:
395 case PIPE_CAP_TEXTURE_QUERY_LOD:
396 case PIPE_CAP_TEXTURE_GATHER_SM5:
397 case PIPE_CAP_TGSI_TXQS:
398 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
399 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
400 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
401 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
402 case PIPE_CAP_INVALIDATE_BUFFER:
403 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
404 case PIPE_CAP_QUERY_MEMORY_INFO:
405 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
406 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
407 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
408 case PIPE_CAP_GENERATE_MIPMAP:
409 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
410 case PIPE_CAP_STRING_MARKER:
411 case PIPE_CAP_CLEAR_TEXTURE:
412 case PIPE_CAP_CULL_DISTANCE:
413 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
414 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
415 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
416 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
417 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
418 case PIPE_CAP_DOUBLES:
419 case PIPE_CAP_TGSI_TEX_TXF_LZ:
420 return 1;
421
422 case PIPE_CAP_INT64:
423 case PIPE_CAP_INT64_DIVMOD:
424 case PIPE_CAP_TGSI_CLOCK:
425 return HAVE_LLVM >= 0x0309;
426
427 case PIPE_CAP_TGSI_VOTE:
428 return HAVE_LLVM >= 0x0400;
429
430 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
431 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
432
433 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
434 return (sscreen->b.info.drm_major == 2 &&
435 sscreen->b.info.drm_minor >= 43) ||
436 sscreen->b.info.drm_major == 3;
437
438 case PIPE_CAP_TEXTURE_MULTISAMPLE:
439 /* 2D tiling on CIK is supported since DRM 2.35.0 */
440 return sscreen->b.chip_class < CIK ||
441 (sscreen->b.info.drm_major == 2 &&
442 sscreen->b.info.drm_minor >= 35) ||
443 sscreen->b.info.drm_major == 3;
444
445 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
446 return R600_MAP_BUFFER_ALIGNMENT;
447
448 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
449 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
450 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
451 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
452 case PIPE_CAP_MAX_VERTEX_STREAMS:
453 return 4;
454
455 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
456 return HAVE_LLVM >= 0x0309 ? 4 : 0;
457
458 case PIPE_CAP_GLSL_FEATURE_LEVEL:
459 if (sscreen->b.chip_class >= GFX9)
460 return 140;
461 if (si_have_tgsi_compute(sscreen))
462 return 450;
463 return HAVE_LLVM >= 0x0309 ? 420 : 410;
464
465 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
466 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
467
468 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
469 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
470 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
471 /* SI doesn't support unaligned loads.
472 * CIK needs DRM 2.50.0 on radeon. */
473 return sscreen->b.chip_class == SI ||
474 (sscreen->b.info.drm_major == 2 &&
475 sscreen->b.info.drm_minor < 50);
476
477 /* Unsupported features. */
478 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
479 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
480 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
481 case PIPE_CAP_USER_VERTEX_BUFFERS:
482 case PIPE_CAP_FAKE_SW_MSAA:
483 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
484 case PIPE_CAP_VERTEXID_NOBASE:
485 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
486 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
487 case PIPE_CAP_NATIVE_FENCE_FD:
488 case PIPE_CAP_TGSI_FS_FBFETCH:
489 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
490 case PIPE_CAP_UMA:
491 return 0;
492
493 case PIPE_CAP_QUERY_BUFFER_OBJECT:
494 return si_have_tgsi_compute(sscreen);
495
496 case PIPE_CAP_DRAW_PARAMETERS:
497 case PIPE_CAP_MULTI_DRAW_INDIRECT:
498 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
499 return sscreen->has_draw_indirect_multi;
500
501 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
502 return 30;
503
504 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
505 return sscreen->b.chip_class <= VI ?
506 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
507
508 /* Stream output. */
509 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
510 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
511 return 32*4;
512
513 /* Geometry shader output. */
514 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
515 return 1024;
516 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
517 return 4095;
518
519 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
520 return 2048;
521
522 /* Texturing. */
523 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
524 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
525 return 15; /* 16384 */
526 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
527 /* textures support 8192, but layered rendering supports 2048 */
528 return 12;
529 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
530 /* textures support 8192, but layered rendering supports 2048 */
531 return 2048;
532
533 /* Viewports and render targets. */
534 case PIPE_CAP_MAX_VIEWPORTS:
535 return R600_MAX_VIEWPORTS;
536 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
537 case PIPE_CAP_MAX_RENDER_TARGETS:
538 return 8;
539
540 /* Timer queries, present when the clock frequency is non zero. */
541 case PIPE_CAP_QUERY_TIMESTAMP:
542 case PIPE_CAP_QUERY_TIME_ELAPSED:
543 return sscreen->b.info.clock_crystal_freq != 0;
544
545 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
546 case PIPE_CAP_MIN_TEXEL_OFFSET:
547 return -32;
548
549 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
550 case PIPE_CAP_MAX_TEXEL_OFFSET:
551 return 31;
552
553 case PIPE_CAP_ENDIANNESS:
554 return PIPE_ENDIAN_LITTLE;
555
556 case PIPE_CAP_VENDOR_ID:
557 return ATI_VENDOR_ID;
558 case PIPE_CAP_DEVICE_ID:
559 return sscreen->b.info.pci_id;
560 case PIPE_CAP_VIDEO_MEMORY:
561 return sscreen->b.info.vram_size >> 20;
562 case PIPE_CAP_PCI_GROUP:
563 return sscreen->b.info.pci_domain;
564 case PIPE_CAP_PCI_BUS:
565 return sscreen->b.info.pci_bus;
566 case PIPE_CAP_PCI_DEVICE:
567 return sscreen->b.info.pci_dev;
568 case PIPE_CAP_PCI_FUNCTION:
569 return sscreen->b.info.pci_func;
570 }
571 return 0;
572 }
573
574 static int si_get_shader_param(struct pipe_screen* pscreen,
575 enum pipe_shader_type shader,
576 enum pipe_shader_cap param)
577 {
578 struct si_screen *sscreen = (struct si_screen *)pscreen;
579
580 switch(shader)
581 {
582 case PIPE_SHADER_FRAGMENT:
583 case PIPE_SHADER_VERTEX:
584 break;
585 case PIPE_SHADER_GEOMETRY:
586 case PIPE_SHADER_TESS_CTRL:
587 case PIPE_SHADER_TESS_EVAL:
588 if (sscreen->b.chip_class >= GFX9)
589 return 0;
590 break;
591 case PIPE_SHADER_COMPUTE:
592 switch (param) {
593 case PIPE_SHADER_CAP_PREFERRED_IR:
594 return PIPE_SHADER_IR_NATIVE;
595
596 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
597 int ir = 1 << PIPE_SHADER_IR_NATIVE;
598
599 if (si_have_tgsi_compute(sscreen))
600 ir |= 1 << PIPE_SHADER_IR_TGSI;
601
602 return ir;
603 }
604
605 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
606 uint64_t max_const_buffer_size;
607 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
608 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
609 &max_const_buffer_size);
610 return MIN2(max_const_buffer_size, INT_MAX);
611 }
612 default:
613 /* If compute shaders don't require a special value
614 * for this cap, we can return the same value we
615 * do for other shader types. */
616 break;
617 }
618 break;
619 default:
620 return 0;
621 }
622
623 switch (param) {
624 /* Shader limits. */
625 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
626 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
627 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
628 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
629 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
630 return 16384;
631 case PIPE_SHADER_CAP_MAX_INPUTS:
632 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
633 case PIPE_SHADER_CAP_MAX_OUTPUTS:
634 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
635 case PIPE_SHADER_CAP_MAX_TEMPS:
636 return 256; /* Max native temporaries. */
637 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
638 return 4096 * sizeof(float[4]); /* actually only memory limits this */
639 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
640 return SI_NUM_CONST_BUFFERS;
641 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
642 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
643 return SI_NUM_SAMPLERS;
644 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
645 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
646 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
647 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
648 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
649 return 32;
650 case PIPE_SHADER_CAP_PREFERRED_IR:
651 return PIPE_SHADER_IR_TGSI;
652 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
653 return 3;
654
655 /* Supported boolean features. */
656 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
657 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
658 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
659 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
660 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
661 case PIPE_SHADER_CAP_INTEGERS:
662 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
663 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
664 return 1;
665
666 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
667 /* TODO: Indirection of geometry shader input dimension is not
668 * handled yet
669 */
670 return shader != PIPE_SHADER_GEOMETRY;
671
672 /* Unsupported boolean features. */
673 case PIPE_SHADER_CAP_MAX_PREDS:
674 case PIPE_SHADER_CAP_SUBROUTINES:
675 case PIPE_SHADER_CAP_SUPPORTED_IRS:
676 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
677 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
678 return 0;
679 }
680 return 0;
681 }
682
683 static void si_destroy_screen(struct pipe_screen* pscreen)
684 {
685 struct si_screen *sscreen = (struct si_screen *)pscreen;
686 struct si_shader_part *parts[] = {
687 sscreen->vs_prologs,
688 sscreen->vs_epilogs,
689 sscreen->tcs_epilogs,
690 sscreen->gs_prologs,
691 sscreen->ps_prologs,
692 sscreen->ps_epilogs
693 };
694 unsigned i;
695
696 if (!sscreen->b.ws->unref(sscreen->b.ws))
697 return;
698
699 util_queue_destroy(&sscreen->shader_compiler_queue);
700
701 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
702 if (sscreen->tm[i])
703 LLVMDisposeTargetMachine(sscreen->tm[i]);
704
705 /* Free shader parts. */
706 for (i = 0; i < ARRAY_SIZE(parts); i++) {
707 while (parts[i]) {
708 struct si_shader_part *part = parts[i];
709
710 parts[i] = part->next;
711 radeon_shader_binary_clean(&part->binary);
712 FREE(part);
713 }
714 }
715 mtx_destroy(&sscreen->shader_parts_mutex);
716 si_destroy_shader_cache(sscreen);
717 r600_destroy_common_screen(&sscreen->b);
718 }
719
720 static bool si_init_gs_info(struct si_screen *sscreen)
721 {
722 switch (sscreen->b.family) {
723 case CHIP_OLAND:
724 case CHIP_HAINAN:
725 case CHIP_KAVERI:
726 case CHIP_KABINI:
727 case CHIP_MULLINS:
728 case CHIP_ICELAND:
729 case CHIP_CARRIZO:
730 case CHIP_STONEY:
731 sscreen->gs_table_depth = 16;
732 return true;
733 case CHIP_TAHITI:
734 case CHIP_PITCAIRN:
735 case CHIP_VERDE:
736 case CHIP_BONAIRE:
737 case CHIP_HAWAII:
738 case CHIP_TONGA:
739 case CHIP_FIJI:
740 case CHIP_POLARIS10:
741 case CHIP_POLARIS11:
742 case CHIP_POLARIS12:
743 case CHIP_VEGA10:
744 sscreen->gs_table_depth = 32;
745 return true;
746 default:
747 return false;
748 }
749 }
750
751 static void si_handle_env_var_force_family(struct si_screen *sscreen)
752 {
753 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
754 unsigned i;
755
756 if (!family)
757 return;
758
759 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
760 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
761 /* Override family and chip_class. */
762 sscreen->b.family = sscreen->b.info.family = i;
763
764 if (i >= CHIP_VEGA10)
765 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
766 else if (i >= CHIP_TONGA)
767 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
768 else if (i >= CHIP_BONAIRE)
769 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
770 else
771 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
772
773 /* Don't submit any IBs. */
774 setenv("RADEON_NOOP", "1", 1);
775 return;
776 }
777 }
778
779 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
780 exit(1);
781 }
782
783 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
784 {
785 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
786 unsigned num_cpus, num_compiler_threads, i;
787
788 if (!sscreen) {
789 return NULL;
790 }
791
792 /* Set functions first. */
793 sscreen->b.b.context_create = si_create_context;
794 sscreen->b.b.destroy = si_destroy_screen;
795 sscreen->b.b.get_param = si_get_param;
796 sscreen->b.b.get_shader_param = si_get_shader_param;
797 sscreen->b.b.resource_create = r600_resource_create_common;
798
799 si_init_screen_state_functions(sscreen);
800
801 if (!r600_common_screen_init(&sscreen->b, ws) ||
802 !si_init_gs_info(sscreen) ||
803 !si_init_shader_cache(sscreen)) {
804 FREE(sscreen);
805 return NULL;
806 }
807
808 /* Only enable as many threads as we have target machines and CPUs. */
809 num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
810 num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
811
812 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
813 32, num_compiler_threads)) {
814 si_destroy_shader_cache(sscreen);
815 FREE(sscreen);
816 return NULL;
817 }
818
819 si_handle_env_var_force_family(sscreen);
820
821 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
822 si_init_perfcounters(sscreen);
823
824 /* Hawaii has a bug with offchip buffers > 256 that can be worked
825 * around by setting 4K granularity.
826 */
827 sscreen->tess_offchip_block_dw_size =
828 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
829
830 sscreen->has_distributed_tess =
831 sscreen->b.chip_class >= VI &&
832 sscreen->b.info.max_se >= 2;
833
834 sscreen->has_draw_indirect_multi =
835 (sscreen->b.family >= CHIP_POLARIS10) ||
836 (sscreen->b.chip_class == VI &&
837 sscreen->b.info.pfp_fw_version >= 121 &&
838 sscreen->b.info.me_fw_version >= 87) ||
839 (sscreen->b.chip_class == CIK &&
840 sscreen->b.info.pfp_fw_version >= 211 &&
841 sscreen->b.info.me_fw_version >= 173) ||
842 (sscreen->b.chip_class == SI &&
843 sscreen->b.info.pfp_fw_version >= 121 &&
844 sscreen->b.info.me_fw_version >= 87);
845
846 sscreen->has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
847 sscreen->b.chip_class >= VI;
848
849 sscreen->b.has_cp_dma = true;
850 sscreen->b.has_streamout = true;
851
852 /* Some chips have RB+ registers, but don't support RB+. Those must
853 * always disable it.
854 */
855 if (sscreen->b.family == CHIP_STONEY ||
856 sscreen->b.chip_class >= GFX9) {
857 sscreen->b.has_rbplus = true;
858
859 sscreen->b.rbplus_allowed =
860 !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
861 sscreen->b.family == CHIP_STONEY;
862 }
863
864 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
865 sscreen->use_monolithic_shaders =
866 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
867
868 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
869 SI_CONTEXT_INV_VMEM_L1 |
870 SI_CONTEXT_INV_GLOBAL_L2;
871 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
872
873 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
874 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
875
876 for (i = 0; i < num_compiler_threads; i++)
877 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
878
879 /* Create the auxiliary context. This must be done last. */
880 sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
881
882 if (sscreen->b.debug_flags & DBG_TEST_DMA)
883 r600_test_dma(&sscreen->b);
884
885 return &sscreen->b.b;
886 }