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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_shader.h"
26 #include "si_public.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_llvm_emit.h"
30 #include "radeon/radeon_uvd.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "vl/vl_decoder.h"
34 #include "../ddebug/dd_util.h"
35
36 #define SI_LLVM_DEFAULT_FEATURES \
37 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
38
39 /*
40 * pipe_context
41 */
42 static void si_destroy_context(struct pipe_context *context)
43 {
44 struct si_context *sctx = (struct si_context *)context;
45 int i;
46
47 /* Unreference the framebuffer normally to disable related logic
48 * properly.
49 */
50 struct pipe_framebuffer_state fb = {};
51 context->set_framebuffer_state(context, &fb);
52
53 si_release_all_descriptors(sctx);
54
55 if (sctx->ce_suballocator)
56 u_suballocator_destroy(sctx->ce_suballocator);
57
58 pipe_resource_reference(&sctx->esgs_ring, NULL);
59 pipe_resource_reference(&sctx->gsvs_ring, NULL);
60 pipe_resource_reference(&sctx->tf_ring, NULL);
61 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
62 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
63 r600_resource_reference(&sctx->border_color_buffer, NULL);
64 free(sctx->border_color_table);
65 r600_resource_reference(&sctx->scratch_buffer, NULL);
66 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
67
68 si_pm4_free_state(sctx, sctx->init_config, ~0);
69 if (sctx->init_config_gs_rings)
70 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
71 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
72 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
73
74 if (sctx->fixed_func_tcs_shader.cso)
75 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
76 if (sctx->custom_dsa_flush)
77 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
78 if (sctx->custom_blend_resolve)
79 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
80 if (sctx->custom_blend_decompress)
81 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
82 if (sctx->custom_blend_fastclear)
83 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
84 if (sctx->custom_blend_dcc_decompress)
85 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
86
87 if (sctx->blitter)
88 util_blitter_destroy(sctx->blitter);
89
90 r600_common_context_cleanup(&sctx->b);
91
92 LLVMDisposeTargetMachine(sctx->tm);
93
94 r600_resource_reference(&sctx->trace_buf, NULL);
95 r600_resource_reference(&sctx->last_trace_buf, NULL);
96 radeon_clear_saved_cs(&sctx->last_gfx);
97
98 FREE(sctx);
99 }
100
101 static enum pipe_reset_status
102 si_amdgpu_get_reset_status(struct pipe_context *ctx)
103 {
104 struct si_context *sctx = (struct si_context *)ctx;
105
106 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
107 }
108
109 /* Apitrace profiling:
110 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
111 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
112 * and remember its number.
113 * 3) In Mesa, enable queries and performance counters around that draw
114 * call and print the results.
115 * 4) glretrace --benchmark --markers ..
116 */
117 static void si_emit_string_marker(struct pipe_context *ctx,
118 const char *string, int len)
119 {
120 struct si_context *sctx = (struct si_context *)ctx;
121
122 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
123 }
124
125 static LLVMTargetMachineRef
126 si_create_llvm_target_machine(struct si_screen *sscreen)
127 {
128 const char *triple = "amdgcn--";
129
130 return LLVMCreateTargetMachine(radeon_llvm_get_r600_target(triple), triple,
131 r600_get_llvm_processor_name(sscreen->b.family),
132 #if HAVE_LLVM >= 0x0308
133 sscreen->b.debug_flags & DBG_SI_SCHED ?
134 SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
135 #endif
136 SI_LLVM_DEFAULT_FEATURES,
137 LLVMCodeGenLevelDefault,
138 LLVMRelocDefault,
139 LLVMCodeModelDefault);
140 }
141
142 static struct pipe_context *si_create_context(struct pipe_screen *screen,
143 void *priv, unsigned flags)
144 {
145 struct si_context *sctx = CALLOC_STRUCT(si_context);
146 struct si_screen* sscreen = (struct si_screen *)screen;
147 struct radeon_winsys *ws = sscreen->b.ws;
148 int shader, i;
149
150 if (!sctx)
151 return NULL;
152
153 if (sscreen->b.debug_flags & DBG_CHECK_VM)
154 flags |= PIPE_CONTEXT_DEBUG;
155
156 if (flags & PIPE_CONTEXT_DEBUG)
157 sscreen->record_llvm_ir = true; /* racy but not critical */
158
159 sctx->b.b.screen = screen; /* this must be set first */
160 sctx->b.b.priv = priv;
161 sctx->b.b.destroy = si_destroy_context;
162 sctx->b.b.emit_string_marker = si_emit_string_marker;
163 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
164 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
165 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
166
167 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
168 goto fail;
169
170 if (sscreen->b.info.drm_major == 3)
171 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
172
173 si_init_blit_functions(sctx);
174 si_init_compute_functions(sctx);
175 si_init_cp_dma_functions(sctx);
176 si_init_debug_functions(sctx);
177
178 if (sscreen->b.info.has_uvd) {
179 sctx->b.b.create_video_codec = si_uvd_create_decoder;
180 sctx->b.b.create_video_buffer = si_video_buffer_create;
181 } else {
182 sctx->b.b.create_video_codec = vl_create_decoder;
183 sctx->b.b.create_video_buffer = vl_video_buffer_create;
184 }
185
186 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
187 si_context_gfx_flush, sctx);
188
189 /* SI + AMDGPU + CE = GPU hang */
190 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
191 sscreen->b.chip_class != SI) {
192 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
193 if (!sctx->ce_ib)
194 goto fail;
195
196 if (ws->cs_add_const_preamble_ib) {
197 sctx->ce_preamble_ib =
198 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
199
200 if (!sctx->ce_preamble_ib)
201 goto fail;
202 }
203
204 sctx->ce_suballocator =
205 u_suballocator_create(&sctx->b.b, 1024 * 1024,
206 PIPE_BIND_CUSTOM,
207 PIPE_USAGE_DEFAULT, false);
208 if (!sctx->ce_suballocator)
209 goto fail;
210 }
211
212 sctx->b.gfx.flush = si_context_gfx_flush;
213
214 /* Border colors. */
215 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
216 sizeof(*sctx->border_color_table));
217 if (!sctx->border_color_table)
218 goto fail;
219
220 sctx->border_color_buffer = (struct r600_resource*)
221 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
222 SI_MAX_BORDER_COLORS *
223 sizeof(*sctx->border_color_table));
224 if (!sctx->border_color_buffer)
225 goto fail;
226
227 sctx->border_color_map =
228 ws->buffer_map(sctx->border_color_buffer->buf,
229 NULL, PIPE_TRANSFER_WRITE);
230 if (!sctx->border_color_map)
231 goto fail;
232
233 si_init_all_descriptors(sctx);
234 si_init_state_functions(sctx);
235 si_init_shader_functions(sctx);
236
237 if (sctx->b.chip_class >= CIK)
238 cik_init_sdma_functions(sctx);
239 else
240 si_init_dma_functions(sctx);
241
242 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
243 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
244
245 sctx->blitter = util_blitter_create(&sctx->b.b);
246 if (sctx->blitter == NULL)
247 goto fail;
248 sctx->blitter->draw_rectangle = r600_draw_rectangle;
249
250 sctx->sample_mask.sample_mask = 0xffff;
251
252 /* these must be last */
253 si_begin_new_cs(sctx);
254 r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
255
256 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
257 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
258 if (sctx->b.chip_class == CIK) {
259 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
260 PIPE_USAGE_DEFAULT, 16);
261 if (!sctx->null_const_buf.buffer)
262 goto fail;
263 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
264
265 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
266 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
267 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
268 &sctx->null_const_buf);
269 }
270 }
271
272 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
273 &sctx->null_const_buf);
274 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
275 &sctx->null_const_buf);
276 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
277 &sctx->null_const_buf);
278 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
279 &sctx->null_const_buf);
280
281 /* Clear the NULL constant buffer, because loads should return zeros. */
282 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
283 sctx->null_const_buf.buffer->width0, 0,
284 R600_COHERENCY_SHADER);
285 }
286
287 uint64_t max_threads_per_block;
288 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
289 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
290 &max_threads_per_block);
291
292 /* The maximum number of scratch waves. Scratch space isn't divided
293 * evenly between CUs. The number is only a function of the number of CUs.
294 * We can decrease the constant to decrease the scratch buffer size.
295 *
296 * sctx->scratch_waves must be >= the maximum posible size of
297 * 1 threadgroup, so that the hw doesn't hang from being unable
298 * to start any.
299 *
300 * The recommended value is 4 per CU at most. Higher numbers don't
301 * bring much benefit, but they still occupy chip resources (think
302 * async compute). I've seen ~2% performance difference between 4 and 32.
303 */
304 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
305 max_threads_per_block / 64);
306
307 sctx->tm = si_create_llvm_target_machine(sscreen);
308
309 return &sctx->b.b;
310 fail:
311 fprintf(stderr, "radeonsi: Failed to create a context.\n");
312 si_destroy_context(&sctx->b.b);
313 return NULL;
314 }
315
316 /*
317 * pipe_screen
318 */
319
320 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
321 {
322 struct si_screen *sscreen = (struct si_screen *)pscreen;
323
324 switch (param) {
325 /* Supported features (boolean caps). */
326 case PIPE_CAP_TWO_SIDED_STENCIL:
327 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
328 case PIPE_CAP_ANISOTROPIC_FILTER:
329 case PIPE_CAP_POINT_SPRITE:
330 case PIPE_CAP_OCCLUSION_QUERY:
331 case PIPE_CAP_TEXTURE_SHADOW_MAP:
332 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
333 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
334 case PIPE_CAP_TEXTURE_SWIZZLE:
335 case PIPE_CAP_DEPTH_CLIP_DISABLE:
336 case PIPE_CAP_SHADER_STENCIL_EXPORT:
337 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
338 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
339 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
340 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
341 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
342 case PIPE_CAP_SM3:
343 case PIPE_CAP_SEAMLESS_CUBE_MAP:
344 case PIPE_CAP_PRIMITIVE_RESTART:
345 case PIPE_CAP_CONDITIONAL_RENDER:
346 case PIPE_CAP_TEXTURE_BARRIER:
347 case PIPE_CAP_INDEP_BLEND_ENABLE:
348 case PIPE_CAP_INDEP_BLEND_FUNC:
349 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
350 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
351 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
352 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
353 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
354 case PIPE_CAP_USER_INDEX_BUFFERS:
355 case PIPE_CAP_USER_CONSTANT_BUFFERS:
356 case PIPE_CAP_START_INSTANCE:
357 case PIPE_CAP_NPOT_TEXTURES:
358 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
359 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
360 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
361 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
362 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
363 case PIPE_CAP_TGSI_INSTANCEID:
364 case PIPE_CAP_COMPUTE:
365 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
366 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
367 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
368 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
369 case PIPE_CAP_CUBE_MAP_ARRAY:
370 case PIPE_CAP_SAMPLE_SHADING:
371 case PIPE_CAP_DRAW_INDIRECT:
372 case PIPE_CAP_CLIP_HALFZ:
373 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
374 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
375 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
376 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
377 case PIPE_CAP_TGSI_TEXCOORD:
378 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
379 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
380 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
381 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
382 case PIPE_CAP_SHAREABLE_SHADERS:
383 case PIPE_CAP_DEPTH_BOUNDS_TEST:
384 case PIPE_CAP_SAMPLER_VIEW_TARGET:
385 case PIPE_CAP_TEXTURE_QUERY_LOD:
386 case PIPE_CAP_TEXTURE_GATHER_SM5:
387 case PIPE_CAP_TGSI_TXQS:
388 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
389 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
390 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
391 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
392 case PIPE_CAP_INVALIDATE_BUFFER:
393 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
394 case PIPE_CAP_QUERY_MEMORY_INFO:
395 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
396 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
397 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
398 case PIPE_CAP_GENERATE_MIPMAP:
399 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
400 case PIPE_CAP_STRING_MARKER:
401 case PIPE_CAP_CLEAR_TEXTURE:
402 return 1;
403
404 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
405 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
406
407 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
408 return (sscreen->b.info.drm_major == 2 &&
409 sscreen->b.info.drm_minor >= 43) ||
410 sscreen->b.info.drm_major == 3;
411
412 case PIPE_CAP_TEXTURE_MULTISAMPLE:
413 /* 2D tiling on CIK is supported since DRM 2.35.0 */
414 return sscreen->b.chip_class < CIK ||
415 (sscreen->b.info.drm_major == 2 &&
416 sscreen->b.info.drm_minor >= 35) ||
417 sscreen->b.info.drm_major == 3;
418
419 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
420 return R600_MAP_BUFFER_ALIGNMENT;
421
422 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
423 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
424 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
425 return 4;
426 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
427 return HAVE_LLVM >= 0x0309 ? 4 : 0;
428
429 case PIPE_CAP_GLSL_FEATURE_LEVEL:
430 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
431 PIPE_SHADER_CAP_SUPPORTED_IRS) &
432 (1 << PIPE_SHADER_IR_TGSI))
433 return 430;
434 return HAVE_LLVM >= 0x0309 ? 420 :
435 HAVE_LLVM >= 0x0307 ? 410 : 330;
436
437 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
438 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
439
440 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
441 return 0;
442
443 /* Unsupported features. */
444 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
445 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
446 case PIPE_CAP_USER_VERTEX_BUFFERS:
447 case PIPE_CAP_FAKE_SW_MSAA:
448 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
449 case PIPE_CAP_VERTEXID_NOBASE:
450 case PIPE_CAP_QUERY_BUFFER_OBJECT:
451 case PIPE_CAP_CULL_DISTANCE:
452 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
453 case PIPE_CAP_TGSI_VOTE:
454 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
455 return 0;
456
457 case PIPE_CAP_DRAW_PARAMETERS:
458 case PIPE_CAP_MULTI_DRAW_INDIRECT:
459 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
460 return sscreen->has_draw_indirect_multi;
461
462 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
463 return 30;
464
465 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
466 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
467
468 /* Stream output. */
469 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
470 return sscreen->b.has_streamout ? 4 : 0;
471 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
472 return sscreen->b.has_streamout ? 1 : 0;
473 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
474 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
475 return sscreen->b.has_streamout ? 32*4 : 0;
476
477 /* Geometry shader output. */
478 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
479 return 1024;
480 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
481 return 4095;
482 case PIPE_CAP_MAX_VERTEX_STREAMS:
483 return 4;
484
485 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
486 return 2048;
487
488 /* Texturing. */
489 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
490 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
491 return 15; /* 16384 */
492 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
493 /* textures support 8192, but layered rendering supports 2048 */
494 return 12;
495 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
496 /* textures support 8192, but layered rendering supports 2048 */
497 return 2048;
498
499 /* Render targets. */
500 case PIPE_CAP_MAX_RENDER_TARGETS:
501 return 8;
502
503 case PIPE_CAP_MAX_VIEWPORTS:
504 return R600_MAX_VIEWPORTS;
505 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
506 return 8;
507
508 /* Timer queries, present when the clock frequency is non zero. */
509 case PIPE_CAP_QUERY_TIMESTAMP:
510 case PIPE_CAP_QUERY_TIME_ELAPSED:
511 return sscreen->b.info.clock_crystal_freq != 0;
512
513 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
514 case PIPE_CAP_MIN_TEXEL_OFFSET:
515 return -32;
516
517 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
518 case PIPE_CAP_MAX_TEXEL_OFFSET:
519 return 31;
520
521 case PIPE_CAP_ENDIANNESS:
522 return PIPE_ENDIAN_LITTLE;
523
524 case PIPE_CAP_VENDOR_ID:
525 return ATI_VENDOR_ID;
526 case PIPE_CAP_DEVICE_ID:
527 return sscreen->b.info.pci_id;
528 case PIPE_CAP_ACCELERATED:
529 return 1;
530 case PIPE_CAP_VIDEO_MEMORY:
531 return sscreen->b.info.vram_size >> 20;
532 case PIPE_CAP_UMA:
533 return 0;
534 case PIPE_CAP_PCI_GROUP:
535 return sscreen->b.info.pci_domain;
536 case PIPE_CAP_PCI_BUS:
537 return sscreen->b.info.pci_bus;
538 case PIPE_CAP_PCI_DEVICE:
539 return sscreen->b.info.pci_dev;
540 case PIPE_CAP_PCI_FUNCTION:
541 return sscreen->b.info.pci_func;
542 }
543 return 0;
544 }
545
546 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
547 {
548 struct si_screen *sscreen = (struct si_screen *)pscreen;
549
550 switch(shader)
551 {
552 case PIPE_SHADER_FRAGMENT:
553 case PIPE_SHADER_VERTEX:
554 case PIPE_SHADER_GEOMETRY:
555 break;
556 case PIPE_SHADER_TESS_CTRL:
557 case PIPE_SHADER_TESS_EVAL:
558 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
559 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
560 return 0;
561 break;
562 case PIPE_SHADER_COMPUTE:
563 switch (param) {
564 case PIPE_SHADER_CAP_PREFERRED_IR:
565 return PIPE_SHADER_IR_NATIVE;
566
567 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
568 int ir = 1 << PIPE_SHADER_IR_NATIVE;
569
570 /* Old kernels disallowed some register writes for SI
571 * that are used for indirect dispatches. */
572 if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
573 sscreen->b.info.drm_major == 3 ||
574 (sscreen->b.info.drm_major == 2 &&
575 sscreen->b.info.drm_minor >= 45)))
576 ir |= 1 << PIPE_SHADER_IR_TGSI;
577
578 return ir;
579 }
580 case PIPE_SHADER_CAP_DOUBLES:
581 return HAVE_LLVM >= 0x0307;
582
583 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
584 uint64_t max_const_buffer_size;
585 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
586 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
587 &max_const_buffer_size);
588 return MIN2(max_const_buffer_size, INT_MAX);
589 }
590 default:
591 /* If compute shaders don't require a special value
592 * for this cap, we can return the same value we
593 * do for other shader types. */
594 break;
595 }
596 break;
597 default:
598 return 0;
599 }
600
601 switch (param) {
602 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
603 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
604 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
605 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
606 return 16384;
607 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
608 return 32;
609 case PIPE_SHADER_CAP_MAX_INPUTS:
610 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
611 case PIPE_SHADER_CAP_MAX_OUTPUTS:
612 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
613 case PIPE_SHADER_CAP_MAX_TEMPS:
614 return 256; /* Max native temporaries. */
615 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
616 return 4096 * sizeof(float[4]); /* actually only memory limits this */
617 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
618 return SI_NUM_CONST_BUFFERS;
619 case PIPE_SHADER_CAP_MAX_PREDS:
620 return 0; /* FIXME */
621 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
622 return 1;
623 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
624 return 1;
625 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
626 /* Indirection of geometry shader input dimension is not
627 * handled yet
628 */
629 return shader != PIPE_SHADER_GEOMETRY;
630 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
631 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
632 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
633 return 1;
634 case PIPE_SHADER_CAP_INTEGERS:
635 return 1;
636 case PIPE_SHADER_CAP_SUBROUTINES:
637 return 0;
638 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
639 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
640 return SI_NUM_SAMPLERS;
641 case PIPE_SHADER_CAP_PREFERRED_IR:
642 return PIPE_SHADER_IR_TGSI;
643 case PIPE_SHADER_CAP_SUPPORTED_IRS:
644 return 0;
645 case PIPE_SHADER_CAP_DOUBLES:
646 return HAVE_LLVM >= 0x0307;
647 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
648 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
649 return 0;
650 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
651 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
652 return 1;
653 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
654 return 32;
655 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
656 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
657 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
658 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
659 }
660 return 0;
661 }
662
663 static void si_destroy_screen(struct pipe_screen* pscreen)
664 {
665 struct si_screen *sscreen = (struct si_screen *)pscreen;
666 struct si_shader_part *parts[] = {
667 sscreen->vs_prologs,
668 sscreen->vs_epilogs,
669 sscreen->tcs_epilogs,
670 sscreen->ps_prologs,
671 sscreen->ps_epilogs
672 };
673 unsigned i;
674
675 if (!sscreen)
676 return;
677
678 if (!sscreen->b.ws->unref(sscreen->b.ws))
679 return;
680
681 if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
682 util_queue_destroy(&sscreen->shader_compiler_queue);
683
684 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
685 if (sscreen->tm[i])
686 LLVMDisposeTargetMachine(sscreen->tm[i]);
687
688 /* Free shader parts. */
689 for (i = 0; i < ARRAY_SIZE(parts); i++) {
690 while (parts[i]) {
691 struct si_shader_part *part = parts[i];
692
693 parts[i] = part->next;
694 radeon_shader_binary_clean(&part->binary);
695 FREE(part);
696 }
697 }
698 pipe_mutex_destroy(sscreen->shader_parts_mutex);
699 si_destroy_shader_cache(sscreen);
700 r600_destroy_common_screen(&sscreen->b);
701 }
702
703 static bool si_init_gs_info(struct si_screen *sscreen)
704 {
705 switch (sscreen->b.family) {
706 case CHIP_OLAND:
707 case CHIP_HAINAN:
708 case CHIP_KAVERI:
709 case CHIP_KABINI:
710 case CHIP_MULLINS:
711 case CHIP_ICELAND:
712 case CHIP_CARRIZO:
713 case CHIP_STONEY:
714 sscreen->gs_table_depth = 16;
715 return true;
716 case CHIP_TAHITI:
717 case CHIP_PITCAIRN:
718 case CHIP_VERDE:
719 case CHIP_BONAIRE:
720 case CHIP_HAWAII:
721 case CHIP_TONGA:
722 case CHIP_FIJI:
723 case CHIP_POLARIS10:
724 case CHIP_POLARIS11:
725 sscreen->gs_table_depth = 32;
726 return true;
727 default:
728 return false;
729 }
730 }
731
732 static void si_handle_env_var_force_family(struct si_screen *sscreen)
733 {
734 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
735 unsigned i;
736
737 if (!family)
738 return;
739
740 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
741 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
742 /* Override family and chip_class. */
743 sscreen->b.family = sscreen->b.info.family = i;
744
745 if (i >= CHIP_TONGA)
746 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
747 else if (i >= CHIP_BONAIRE)
748 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
749 else
750 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
751
752 /* Don't submit any IBs. */
753 setenv("RADEON_NOOP", "1", 1);
754 return;
755 }
756 }
757
758 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
759 exit(1);
760 }
761
762 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
763 {
764 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
765 unsigned num_cpus, num_compiler_threads, i;
766
767 if (!sscreen) {
768 return NULL;
769 }
770
771 /* Set functions first. */
772 sscreen->b.b.context_create = si_create_context;
773 sscreen->b.b.destroy = si_destroy_screen;
774 sscreen->b.b.get_param = si_get_param;
775 sscreen->b.b.get_shader_param = si_get_shader_param;
776 sscreen->b.b.resource_create = r600_resource_create_common;
777
778 si_init_screen_state_functions(sscreen);
779
780 if (!r600_common_screen_init(&sscreen->b, ws) ||
781 !si_init_gs_info(sscreen) ||
782 !si_init_shader_cache(sscreen)) {
783 FREE(sscreen);
784 return NULL;
785 }
786
787 si_handle_env_var_force_family(sscreen);
788
789 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
790 si_init_perfcounters(sscreen);
791
792 /* Hawaii has a bug with offchip buffers > 256 that can be worked
793 * around by setting 4K granularity.
794 */
795 sscreen->tess_offchip_block_dw_size =
796 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
797
798 sscreen->has_distributed_tess =
799 sscreen->b.chip_class >= VI &&
800 sscreen->b.info.max_se >= 2;
801
802 sscreen->has_draw_indirect_multi =
803 (sscreen->b.family >= CHIP_POLARIS10) ||
804 (sscreen->b.chip_class == VI &&
805 sscreen->b.info.pfp_fw_version >= 121 &&
806 sscreen->b.info.me_fw_version >= 87) ||
807 (sscreen->b.chip_class == CIK &&
808 sscreen->b.info.pfp_fw_version >= 211 &&
809 sscreen->b.info.me_fw_version >= 173) ||
810 (sscreen->b.chip_class == SI &&
811 sscreen->b.info.pfp_fw_version >= 121 &&
812 sscreen->b.info.me_fw_version >= 87);
813
814 sscreen->b.has_cp_dma = true;
815 sscreen->b.has_streamout = true;
816 pipe_mutex_init(sscreen->shader_parts_mutex);
817 sscreen->use_monolithic_shaders =
818 HAVE_LLVM < 0x0308 ||
819 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
820
821 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
822 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
823
824 /* Only enable as many threads as we have target machines and CPUs. */
825 num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
826 num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
827
828 for (i = 0; i < num_compiler_threads; i++)
829 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
830
831 util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
832 32, num_compiler_threads);
833
834 /* Create the auxiliary context. This must be done last. */
835 sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
836
837 if (sscreen->b.debug_flags & DBG_TEST_DMA)
838 r600_test_dma(&sscreen->b);
839
840 return &sscreen->b.b;
841 }