projects / mesa.git / blob
? search:


9f6e3c26f43fe034ecc5effc04bb57c8b48f8dc3
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "util/u_tests.h"
34 #include "vl/vl_decoder.h"
35 #include "../ddebug/dd_util.h"
36
37 /*
38 * pipe_context
39 */
40 static void si_destroy_context(struct pipe_context *context)
41 {
42 struct si_context *sctx = (struct si_context *)context;
43 int i;
44
45 /* Unreference the framebuffer normally to disable related logic
46 * properly.
47 */
48 struct pipe_framebuffer_state fb = {};
49 if (context->set_framebuffer_state)
50 context->set_framebuffer_state(context, &fb);
51
52 si_release_all_descriptors(sctx);
53
54 if (sctx->ce_suballocator)
55 u_suballocator_destroy(sctx->ce_suballocator);
56
57 r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
58 pipe_resource_reference(&sctx->esgs_ring, NULL);
59 pipe_resource_reference(&sctx->gsvs_ring, NULL);
60 pipe_resource_reference(&sctx->tf_ring, NULL);
61 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
62 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
63 r600_resource_reference(&sctx->border_color_buffer, NULL);
64 free(sctx->border_color_table);
65 r600_resource_reference(&sctx->scratch_buffer, NULL);
66 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
67
68 si_pm4_free_state(sctx, sctx->init_config, ~0);
69 if (sctx->init_config_gs_rings)
70 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
71 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
72 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
73
74 if (sctx->fixed_func_tcs_shader.cso)
75 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
76 if (sctx->custom_dsa_flush)
77 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
78 if (sctx->custom_blend_resolve)
79 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
80 if (sctx->custom_blend_fmask_decompress)
81 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
82 if (sctx->custom_blend_eliminate_fastclear)
83 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
84 if (sctx->custom_blend_dcc_decompress)
85 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
86
87 if (sctx->blitter)
88 util_blitter_destroy(sctx->blitter);
89
90 r600_common_context_cleanup(&sctx->b);
91
92 LLVMDisposeTargetMachine(sctx->tm);
93
94 r600_resource_reference(&sctx->trace_buf, NULL);
95 r600_resource_reference(&sctx->last_trace_buf, NULL);
96 radeon_clear_saved_cs(&sctx->last_gfx);
97
98 pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
99 util_dynarray_fini(&sctx->bindless_descriptors);
100
101 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
102 _mesa_hash_table_destroy(sctx->img_handles, NULL);
103
104 util_dynarray_fini(&sctx->resident_tex_handles);
105 util_dynarray_fini(&sctx->resident_img_handles);
106 FREE(sctx);
107 }
108
109 static enum pipe_reset_status
110 si_amdgpu_get_reset_status(struct pipe_context *ctx)
111 {
112 struct si_context *sctx = (struct si_context *)ctx;
113
114 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
115 }
116
117 /* Apitrace profiling:
118 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
119 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
120 * and remember its number.
121 * 3) In Mesa, enable queries and performance counters around that draw
122 * call and print the results.
123 * 4) glretrace --benchmark --markers ..
124 */
125 static void si_emit_string_marker(struct pipe_context *ctx,
126 const char *string, int len)
127 {
128 struct si_context *sctx = (struct si_context *)ctx;
129
130 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
131 }
132
133 static LLVMTargetMachineRef
134 si_create_llvm_target_machine(struct si_screen *sscreen)
135 {
136 const char *triple = "amdgcn--";
137 char features[256];
138
139 snprintf(features, sizeof(features),
140 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s",
141 sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
142 sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
143
144 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
145 r600_get_llvm_processor_name(sscreen->b.family),
146 features,
147 LLVMCodeGenLevelDefault,
148 LLVMRelocDefault,
149 LLVMCodeModelDefault);
150 }
151
152 static struct pipe_context *si_create_context(struct pipe_screen *screen,
153 unsigned flags)
154 {
155 struct si_context *sctx = CALLOC_STRUCT(si_context);
156 struct si_screen* sscreen = (struct si_screen *)screen;
157 struct radeon_winsys *ws = sscreen->b.ws;
158 int shader, i;
159
160 if (!sctx)
161 return NULL;
162
163 if (sscreen->b.debug_flags & DBG_CHECK_VM)
164 flags |= PIPE_CONTEXT_DEBUG;
165
166 if (flags & PIPE_CONTEXT_DEBUG)
167 sscreen->record_llvm_ir = true; /* racy but not critical */
168
169 sctx->b.b.screen = screen; /* this must be set first */
170 sctx->b.b.priv = NULL;
171 sctx->b.b.destroy = si_destroy_context;
172 sctx->b.b.emit_string_marker = si_emit_string_marker;
173 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
174 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
175 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
176
177 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
178 goto fail;
179
180 if (sscreen->b.info.drm_major == 3)
181 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
182
183 si_init_blit_functions(sctx);
184 si_init_compute_functions(sctx);
185 si_init_cp_dma_functions(sctx);
186 si_init_debug_functions(sctx);
187
188 if (sscreen->b.info.has_hw_decode) {
189 sctx->b.b.create_video_codec = si_uvd_create_decoder;
190 sctx->b.b.create_video_buffer = si_video_buffer_create;
191 } else {
192 sctx->b.b.create_video_codec = vl_create_decoder;
193 sctx->b.b.create_video_buffer = vl_video_buffer_create;
194 }
195
196 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
197 si_context_gfx_flush, sctx);
198
199 /* SI + AMDGPU + CE = GPU hang */
200 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
201 sscreen->b.chip_class != SI &&
202 /* These can't use CE due to a power gating bug in the kernel. */
203 sscreen->b.family != CHIP_CARRIZO &&
204 sscreen->b.family != CHIP_STONEY &&
205 /* Some CE bug is causing green screen corruption w/ MPV video
206 * playback and occasional corruption w/ 3D. */
207 sscreen->b.chip_class != GFX9) {
208 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
209 if (!sctx->ce_ib)
210 goto fail;
211
212 if (ws->cs_add_const_preamble_ib) {
213 sctx->ce_preamble_ib =
214 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
215
216 if (!sctx->ce_preamble_ib)
217 goto fail;
218 }
219
220 sctx->ce_suballocator =
221 u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
222 PIPE_USAGE_DEFAULT,
223 R600_RESOURCE_FLAG_UNMAPPABLE, false);
224 if (!sctx->ce_suballocator)
225 goto fail;
226 }
227
228 sctx->b.gfx.flush = si_context_gfx_flush;
229
230 /* Border colors. */
231 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
232 sizeof(*sctx->border_color_table));
233 if (!sctx->border_color_table)
234 goto fail;
235
236 sctx->border_color_buffer = (struct r600_resource*)
237 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
238 SI_MAX_BORDER_COLORS *
239 sizeof(*sctx->border_color_table));
240 if (!sctx->border_color_buffer)
241 goto fail;
242
243 sctx->border_color_map =
244 ws->buffer_map(sctx->border_color_buffer->buf,
245 NULL, PIPE_TRANSFER_WRITE);
246 if (!sctx->border_color_map)
247 goto fail;
248
249 si_init_all_descriptors(sctx);
250 si_init_state_functions(sctx);
251 si_init_shader_functions(sctx);
252 si_init_ia_multi_vgt_param_table(sctx);
253
254 if (sctx->b.chip_class >= CIK)
255 cik_init_sdma_functions(sctx);
256 else
257 si_init_dma_functions(sctx);
258
259 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
260 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
261
262 sctx->blitter = util_blitter_create(&sctx->b.b);
263 if (sctx->blitter == NULL)
264 goto fail;
265 sctx->blitter->draw_rectangle = r600_draw_rectangle;
266
267 sctx->sample_mask.sample_mask = 0xffff;
268
269 /* these must be last */
270 si_begin_new_cs(sctx);
271
272 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
273 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
274 if (sctx->b.chip_class == CIK) {
275 sctx->null_const_buf.buffer =
276 r600_aligned_buffer_create(screen,
277 R600_RESOURCE_FLAG_UNMAPPABLE,
278 PIPE_USAGE_DEFAULT, 16,
279 sctx->screen->b.info.tcc_cache_line_size);
280 if (!sctx->null_const_buf.buffer)
281 goto fail;
282 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
283
284 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
285 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
286 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
287 &sctx->null_const_buf);
288 }
289 }
290
291 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
292 &sctx->null_const_buf);
293 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
294 &sctx->null_const_buf);
295 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
296 &sctx->null_const_buf);
297 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
298 &sctx->null_const_buf);
299
300 /* Clear the NULL constant buffer, because loads should return zeros. */
301 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
302 sctx->null_const_buf.buffer->width0, 0,
303 R600_COHERENCY_SHADER);
304 }
305
306 uint64_t max_threads_per_block;
307 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
308 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
309 &max_threads_per_block);
310
311 /* The maximum number of scratch waves. Scratch space isn't divided
312 * evenly between CUs. The number is only a function of the number of CUs.
313 * We can decrease the constant to decrease the scratch buffer size.
314 *
315 * sctx->scratch_waves must be >= the maximum posible size of
316 * 1 threadgroup, so that the hw doesn't hang from being unable
317 * to start any.
318 *
319 * The recommended value is 4 per CU at most. Higher numbers don't
320 * bring much benefit, but they still occupy chip resources (think
321 * async compute). I've seen ~2% performance difference between 4 and 32.
322 */
323 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
324 max_threads_per_block / 64);
325
326 sctx->tm = si_create_llvm_target_machine(sscreen);
327
328 /* Create a slab allocator for all bindless descriptors. */
329 if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
330 si_bindless_descriptor_can_reclaim_slab,
331 si_bindless_descriptor_slab_alloc,
332 si_bindless_descriptor_slab_free))
333 goto fail;
334
335 util_dynarray_init(&sctx->bindless_descriptors, NULL);
336
337 /* Bindless handles. */
338 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
339 _mesa_key_pointer_equal);
340 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
341 _mesa_key_pointer_equal);
342
343 util_dynarray_init(&sctx->resident_tex_handles, NULL);
344 util_dynarray_init(&sctx->resident_img_handles, NULL);
345
346 return &sctx->b.b;
347 fail:
348 fprintf(stderr, "radeonsi: Failed to create a context.\n");
349 si_destroy_context(&sctx->b.b);
350 return NULL;
351 }
352
353 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
354 void *priv, unsigned flags)
355 {
356 struct si_screen *sscreen = (struct si_screen *)screen;
357 struct pipe_context *ctx = si_create_context(screen, flags);
358
359 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
360 return ctx;
361
362 /* Clover (compute-only) is unsupported.
363 *
364 * Since the threaded context creates shader states from the non-driver
365 * thread, asynchronous compilation is required for create_{shader}_-
366 * state not to use pipe_context. Debug contexts (ddebug) disable
367 * asynchronous compilation, so don't use the threaded context with
368 * those.
369 */
370 if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
371 return ctx;
372
373 /* When shaders are logged to stderr, asynchronous compilation is
374 * disabled too. */
375 if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
376 DBG_PS | DBG_CS))
377 return ctx;
378
379 return threaded_context_create(ctx, &sscreen->b.pool_transfers,
380 r600_replace_buffer_storage,
381 &((struct si_context*)ctx)->b.tc);
382 }
383
384 /*
385 * pipe_screen
386 */
387 static bool si_have_tgsi_compute(struct si_screen *sscreen)
388 {
389 /* Old kernels disallowed some register writes for SI
390 * that are used for indirect dispatches. */
391 return (sscreen->b.chip_class >= CIK ||
392 sscreen->b.info.drm_major == 3 ||
393 (sscreen->b.info.drm_major == 2 &&
394 sscreen->b.info.drm_minor >= 45));
395 }
396
397 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
398 {
399 struct si_screen *sscreen = (struct si_screen *)pscreen;
400
401 switch (param) {
402 /* Supported features (boolean caps). */
403 case PIPE_CAP_ACCELERATED:
404 case PIPE_CAP_TWO_SIDED_STENCIL:
405 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
406 case PIPE_CAP_ANISOTROPIC_FILTER:
407 case PIPE_CAP_POINT_SPRITE:
408 case PIPE_CAP_OCCLUSION_QUERY:
409 case PIPE_CAP_TEXTURE_SHADOW_MAP:
410 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
411 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
412 case PIPE_CAP_TEXTURE_SWIZZLE:
413 case PIPE_CAP_DEPTH_CLIP_DISABLE:
414 case PIPE_CAP_SHADER_STENCIL_EXPORT:
415 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
416 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
417 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
418 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
419 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
420 case PIPE_CAP_SM3:
421 case PIPE_CAP_SEAMLESS_CUBE_MAP:
422 case PIPE_CAP_PRIMITIVE_RESTART:
423 case PIPE_CAP_CONDITIONAL_RENDER:
424 case PIPE_CAP_TEXTURE_BARRIER:
425 case PIPE_CAP_INDEP_BLEND_ENABLE:
426 case PIPE_CAP_INDEP_BLEND_FUNC:
427 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
428 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
429 case PIPE_CAP_USER_CONSTANT_BUFFERS:
430 case PIPE_CAP_START_INSTANCE:
431 case PIPE_CAP_NPOT_TEXTURES:
432 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
433 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
434 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
435 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
436 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
437 case PIPE_CAP_TGSI_INSTANCEID:
438 case PIPE_CAP_COMPUTE:
439 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
440 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
441 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
442 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
443 case PIPE_CAP_CUBE_MAP_ARRAY:
444 case PIPE_CAP_SAMPLE_SHADING:
445 case PIPE_CAP_DRAW_INDIRECT:
446 case PIPE_CAP_CLIP_HALFZ:
447 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
448 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
449 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
450 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
451 case PIPE_CAP_TGSI_TEXCOORD:
452 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
453 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
454 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
455 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
456 case PIPE_CAP_SHAREABLE_SHADERS:
457 case PIPE_CAP_DEPTH_BOUNDS_TEST:
458 case PIPE_CAP_SAMPLER_VIEW_TARGET:
459 case PIPE_CAP_TEXTURE_QUERY_LOD:
460 case PIPE_CAP_TEXTURE_GATHER_SM5:
461 case PIPE_CAP_TGSI_TXQS:
462 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
463 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
464 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
465 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
466 case PIPE_CAP_INVALIDATE_BUFFER:
467 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
468 case PIPE_CAP_QUERY_MEMORY_INFO:
469 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
470 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
471 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
472 case PIPE_CAP_GENERATE_MIPMAP:
473 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
474 case PIPE_CAP_STRING_MARKER:
475 case PIPE_CAP_CLEAR_TEXTURE:
476 case PIPE_CAP_CULL_DISTANCE:
477 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
478 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
479 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
480 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
481 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
482 case PIPE_CAP_DOUBLES:
483 case PIPE_CAP_TGSI_TEX_TXF_LZ:
484 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
485 case PIPE_CAP_BINDLESS_TEXTURE:
486 return 1;
487
488 case PIPE_CAP_INT64:
489 case PIPE_CAP_INT64_DIVMOD:
490 case PIPE_CAP_TGSI_CLOCK:
491 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
492 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
493 return 1;
494
495 case PIPE_CAP_TGSI_VOTE:
496 return HAVE_LLVM >= 0x0400;
497
498 case PIPE_CAP_TGSI_BALLOT:
499 return HAVE_LLVM >= 0x0500;
500
501 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
502 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
503
504 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
505 return (sscreen->b.info.drm_major == 2 &&
506 sscreen->b.info.drm_minor >= 43) ||
507 sscreen->b.info.drm_major == 3;
508
509 case PIPE_CAP_TEXTURE_MULTISAMPLE:
510 /* 2D tiling on CIK is supported since DRM 2.35.0 */
511 return sscreen->b.chip_class < CIK ||
512 (sscreen->b.info.drm_major == 2 &&
513 sscreen->b.info.drm_minor >= 35) ||
514 sscreen->b.info.drm_major == 3;
515
516 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
517 return R600_MAP_BUFFER_ALIGNMENT;
518
519 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
520 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
521 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
522 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
523 case PIPE_CAP_MAX_VERTEX_STREAMS:
524 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
525 return 4;
526
527 case PIPE_CAP_GLSL_FEATURE_LEVEL:
528 if (si_have_tgsi_compute(sscreen))
529 return 450;
530 return 420;
531
532 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
533 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
534
535 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
536 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
537 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
538 /* SI doesn't support unaligned loads.
539 * CIK needs DRM 2.50.0 on radeon. */
540 return sscreen->b.chip_class == SI ||
541 (sscreen->b.info.drm_major == 2 &&
542 sscreen->b.info.drm_minor < 50);
543
544 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
545 /* Disable on SI due to VM faults in CP DMA. Enable once these
546 * faults are mitigated in software.
547 */
548 if (sscreen->b.chip_class >= CIK &&
549 sscreen->b.info.drm_major == 3 &&
550 sscreen->b.info.drm_minor >= 13)
551 return RADEON_SPARSE_PAGE_SIZE;
552 return 0;
553
554 /* Unsupported features. */
555 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
556 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
557 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
558 case PIPE_CAP_USER_VERTEX_BUFFERS:
559 case PIPE_CAP_FAKE_SW_MSAA:
560 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
561 case PIPE_CAP_VERTEXID_NOBASE:
562 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
563 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
564 case PIPE_CAP_NATIVE_FENCE_FD:
565 case PIPE_CAP_TGSI_FS_FBFETCH:
566 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
567 case PIPE_CAP_UMA:
568 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
569 case PIPE_CAP_POST_DEPTH_COVERAGE:
570 return 0;
571
572 case PIPE_CAP_QUERY_BUFFER_OBJECT:
573 return si_have_tgsi_compute(sscreen);
574
575 case PIPE_CAP_DRAW_PARAMETERS:
576 case PIPE_CAP_MULTI_DRAW_INDIRECT:
577 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
578 return sscreen->has_draw_indirect_multi;
579
580 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
581 return 30;
582
583 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
584 return sscreen->b.chip_class <= VI ?
585 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
586
587 /* Stream output. */
588 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
589 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
590 return 32*4;
591
592 /* Geometry shader output. */
593 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
594 return 1024;
595 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
596 return 4095;
597
598 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
599 return 2048;
600
601 /* Texturing. */
602 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
603 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
604 return 15; /* 16384 */
605 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
606 /* textures support 8192, but layered rendering supports 2048 */
607 return 12;
608 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
609 /* textures support 8192, but layered rendering supports 2048 */
610 return 2048;
611
612 /* Viewports and render targets. */
613 case PIPE_CAP_MAX_VIEWPORTS:
614 return R600_MAX_VIEWPORTS;
615 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
616 case PIPE_CAP_MAX_RENDER_TARGETS:
617 return 8;
618
619 /* Timer queries, present when the clock frequency is non zero. */
620 case PIPE_CAP_QUERY_TIMESTAMP:
621 case PIPE_CAP_QUERY_TIME_ELAPSED:
622 return sscreen->b.info.clock_crystal_freq != 0;
623
624 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
625 case PIPE_CAP_MIN_TEXEL_OFFSET:
626 return -32;
627
628 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
629 case PIPE_CAP_MAX_TEXEL_OFFSET:
630 return 31;
631
632 case PIPE_CAP_ENDIANNESS:
633 return PIPE_ENDIAN_LITTLE;
634
635 case PIPE_CAP_VENDOR_ID:
636 return ATI_VENDOR_ID;
637 case PIPE_CAP_DEVICE_ID:
638 return sscreen->b.info.pci_id;
639 case PIPE_CAP_VIDEO_MEMORY:
640 return sscreen->b.info.vram_size >> 20;
641 case PIPE_CAP_PCI_GROUP:
642 return sscreen->b.info.pci_domain;
643 case PIPE_CAP_PCI_BUS:
644 return sscreen->b.info.pci_bus;
645 case PIPE_CAP_PCI_DEVICE:
646 return sscreen->b.info.pci_dev;
647 case PIPE_CAP_PCI_FUNCTION:
648 return sscreen->b.info.pci_func;
649 }
650 return 0;
651 }
652
653 static int si_get_shader_param(struct pipe_screen* pscreen,
654 enum pipe_shader_type shader,
655 enum pipe_shader_cap param)
656 {
657 struct si_screen *sscreen = (struct si_screen *)pscreen;
658
659 switch(shader)
660 {
661 case PIPE_SHADER_FRAGMENT:
662 case PIPE_SHADER_VERTEX:
663 case PIPE_SHADER_GEOMETRY:
664 case PIPE_SHADER_TESS_CTRL:
665 case PIPE_SHADER_TESS_EVAL:
666 break;
667 case PIPE_SHADER_COMPUTE:
668 switch (param) {
669 case PIPE_SHADER_CAP_PREFERRED_IR:
670 return PIPE_SHADER_IR_NATIVE;
671
672 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
673 int ir = 1 << PIPE_SHADER_IR_NATIVE;
674
675 if (si_have_tgsi_compute(sscreen))
676 ir |= 1 << PIPE_SHADER_IR_TGSI;
677
678 return ir;
679 }
680
681 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
682 uint64_t max_const_buffer_size;
683 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
684 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
685 &max_const_buffer_size);
686 return MIN2(max_const_buffer_size, INT_MAX);
687 }
688 default:
689 /* If compute shaders don't require a special value
690 * for this cap, we can return the same value we
691 * do for other shader types. */
692 break;
693 }
694 break;
695 default:
696 return 0;
697 }
698
699 switch (param) {
700 /* Shader limits. */
701 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
702 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
703 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
704 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
705 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
706 return 16384;
707 case PIPE_SHADER_CAP_MAX_INPUTS:
708 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
709 case PIPE_SHADER_CAP_MAX_OUTPUTS:
710 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
711 case PIPE_SHADER_CAP_MAX_TEMPS:
712 return 256; /* Max native temporaries. */
713 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
714 return 4096 * sizeof(float[4]); /* actually only memory limits this */
715 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
716 return SI_NUM_CONST_BUFFERS;
717 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
718 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
719 return SI_NUM_SAMPLERS;
720 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
721 return SI_NUM_SHADER_BUFFERS;
722 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
723 return SI_NUM_IMAGES;
724 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
725 return 32;
726 case PIPE_SHADER_CAP_PREFERRED_IR:
727 return PIPE_SHADER_IR_TGSI;
728 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
729 return 3;
730
731 /* Supported boolean features. */
732 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
733 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
734 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
735 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
736 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
737 case PIPE_SHADER_CAP_INTEGERS:
738 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
739 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
740 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
741 return 1;
742
743 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
744 /* TODO: Indirection of geometry shader input dimension is not
745 * handled yet
746 */
747 return shader != PIPE_SHADER_GEOMETRY;
748
749 /* Unsupported boolean features. */
750 case PIPE_SHADER_CAP_SUBROUTINES:
751 case PIPE_SHADER_CAP_SUPPORTED_IRS:
752 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
753 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
754 return 0;
755 }
756 return 0;
757 }
758
759 static void si_destroy_screen(struct pipe_screen* pscreen)
760 {
761 struct si_screen *sscreen = (struct si_screen *)pscreen;
762 struct si_shader_part *parts[] = {
763 sscreen->vs_prologs,
764 sscreen->tcs_epilogs,
765 sscreen->gs_prologs,
766 sscreen->ps_prologs,
767 sscreen->ps_epilogs
768 };
769 unsigned i;
770
771 if (!sscreen->b.ws->unref(sscreen->b.ws))
772 return;
773
774 util_queue_destroy(&sscreen->shader_compiler_queue);
775 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
776
777 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
778 if (sscreen->tm[i])
779 LLVMDisposeTargetMachine(sscreen->tm[i]);
780
781 for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
782 if (sscreen->tm_low_priority[i])
783 LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
784
785 /* Free shader parts. */
786 for (i = 0; i < ARRAY_SIZE(parts); i++) {
787 while (parts[i]) {
788 struct si_shader_part *part = parts[i];
789
790 parts[i] = part->next;
791 radeon_shader_binary_clean(&part->binary);
792 FREE(part);
793 }
794 }
795 mtx_destroy(&sscreen->shader_parts_mutex);
796 si_destroy_shader_cache(sscreen);
797 r600_destroy_common_screen(&sscreen->b);
798 }
799
800 static bool si_init_gs_info(struct si_screen *sscreen)
801 {
802 switch (sscreen->b.family) {
803 case CHIP_OLAND:
804 case CHIP_HAINAN:
805 case CHIP_KAVERI:
806 case CHIP_KABINI:
807 case CHIP_MULLINS:
808 case CHIP_ICELAND:
809 case CHIP_CARRIZO:
810 case CHIP_STONEY:
811 sscreen->gs_table_depth = 16;
812 return true;
813 case CHIP_TAHITI:
814 case CHIP_PITCAIRN:
815 case CHIP_VERDE:
816 case CHIP_BONAIRE:
817 case CHIP_HAWAII:
818 case CHIP_TONGA:
819 case CHIP_FIJI:
820 case CHIP_POLARIS10:
821 case CHIP_POLARIS11:
822 case CHIP_POLARIS12:
823 case CHIP_VEGA10:
824 case CHIP_RAVEN:
825 sscreen->gs_table_depth = 32;
826 return true;
827 default:
828 return false;
829 }
830 }
831
832 static void si_handle_env_var_force_family(struct si_screen *sscreen)
833 {
834 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
835 unsigned i;
836
837 if (!family)
838 return;
839
840 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
841 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
842 /* Override family and chip_class. */
843 sscreen->b.family = sscreen->b.info.family = i;
844
845 if (i >= CHIP_VEGA10)
846 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
847 else if (i >= CHIP_TONGA)
848 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
849 else if (i >= CHIP_BONAIRE)
850 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
851 else
852 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
853
854 /* Don't submit any IBs. */
855 setenv("RADEON_NOOP", "1", 1);
856 return;
857 }
858 }
859
860 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
861 exit(1);
862 }
863
864 static void si_test_vmfault(struct si_screen *sscreen)
865 {
866 struct pipe_context *ctx = sscreen->b.aux_context;
867 struct si_context *sctx = (struct si_context *)ctx;
868 struct pipe_resource *buf =
869 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
870
871 if (!buf) {
872 puts("Buffer allocation failed.");
873 exit(1);
874 }
875
876 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
877
878 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
879 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
880 ctx->flush(ctx, NULL, 0);
881 puts("VM fault test: CP - done.");
882 }
883 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
884 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
885 ctx->flush(ctx, NULL, 0);
886 puts("VM fault test: SDMA - done.");
887 }
888 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
889 util_test_constant_buffer(ctx, buf);
890 puts("VM fault test: Shader - done.");
891 }
892 exit(0);
893 }
894
895 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
896 {
897 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
898 unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
899
900 if (!sscreen) {
901 return NULL;
902 }
903
904 /* Set functions first. */
905 sscreen->b.b.context_create = si_pipe_create_context;
906 sscreen->b.b.destroy = si_destroy_screen;
907 sscreen->b.b.get_param = si_get_param;
908 sscreen->b.b.get_shader_param = si_get_shader_param;
909 sscreen->b.b.resource_create = r600_resource_create_common;
910
911 si_init_screen_state_functions(sscreen);
912
913 if (!r600_common_screen_init(&sscreen->b, ws) ||
914 !si_init_gs_info(sscreen) ||
915 !si_init_shader_cache(sscreen)) {
916 FREE(sscreen);
917 return NULL;
918 }
919
920 /* Only enable as many threads as we have target machines, but at most
921 * the number of CPUs - 1 if there is more than one.
922 */
923 num_threads = sysconf(_SC_NPROCESSORS_ONLN);
924 num_threads = MAX2(1, num_threads - 1);
925 num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
926 num_compiler_threads_lowprio =
927 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
928
929 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
930 32, num_compiler_threads, 0)) {
931 si_destroy_shader_cache(sscreen);
932 FREE(sscreen);
933 return NULL;
934 }
935
936 /* The queue must be large enough so that adding optimized shaders
937 * doesn't stall draw calls when the queue is full. Especially varying
938 * packing generates a very high volume of optimized shader compilation
939 * jobs.
940 */
941 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
942 "si_shader_low",
943 1024, num_compiler_threads,
944 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
945 si_destroy_shader_cache(sscreen);
946 FREE(sscreen);
947 return NULL;
948 }
949
950 si_handle_env_var_force_family(sscreen);
951
952 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
953 si_init_perfcounters(sscreen);
954
955 /* Hawaii has a bug with offchip buffers > 256 that can be worked
956 * around by setting 4K granularity.
957 */
958 sscreen->tess_offchip_block_dw_size =
959 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
960
961 sscreen->has_distributed_tess =
962 sscreen->b.chip_class >= VI &&
963 sscreen->b.info.max_se >= 2;
964
965 sscreen->has_draw_indirect_multi =
966 (sscreen->b.family >= CHIP_POLARIS10) ||
967 (sscreen->b.chip_class == VI &&
968 sscreen->b.info.pfp_fw_version >= 121 &&
969 sscreen->b.info.me_fw_version >= 87) ||
970 (sscreen->b.chip_class == CIK &&
971 sscreen->b.info.pfp_fw_version >= 211 &&
972 sscreen->b.info.me_fw_version >= 173) ||
973 (sscreen->b.chip_class == SI &&
974 sscreen->b.info.pfp_fw_version >= 121 &&
975 sscreen->b.info.me_fw_version >= 87);
976
977 sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
978 sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
979 sscreen->b.family <= CHIP_POLARIS12) ||
980 sscreen->b.family == CHIP_VEGA10 ||
981 sscreen->b.family == CHIP_RAVEN;
982
983 sscreen->b.has_cp_dma = true;
984 sscreen->b.has_streamout = true;
985
986 /* Some chips have RB+ registers, but don't support RB+. Those must
987 * always disable it.
988 */
989 if (sscreen->b.family == CHIP_STONEY ||
990 sscreen->b.chip_class >= GFX9) {
991 sscreen->b.has_rbplus = true;
992
993 sscreen->b.rbplus_allowed =
994 !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
995 (sscreen->b.family == CHIP_STONEY ||
996 sscreen->b.family == CHIP_RAVEN);
997 }
998
999 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1000 sscreen->use_monolithic_shaders =
1001 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1002
1003 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1004 SI_CONTEXT_INV_VMEM_L1 |
1005 SI_CONTEXT_INV_GLOBAL_L2;
1006 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1007
1008 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1009 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1010
1011 for (i = 0; i < num_compiler_threads; i++)
1012 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1013 for (i = 0; i < num_compiler_threads_lowprio; i++)
1014 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1015
1016 /* Create the auxiliary context. This must be done last. */
1017 sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1018
1019 if (sscreen->b.debug_flags & DBG_TEST_DMA)
1020 r600_test_dma(&sscreen->b);
1021
1022 if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1023 DBG_TEST_VMFAULT_SDMA |
1024 DBG_TEST_VMFAULT_SHADER))
1025 si_test_vmfault(sscreen);
1026
1027 return &sscreen->b.b;
1028 }