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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "util/u_tests.h"
34 #include "vl/vl_decoder.h"
35 #include "../ddebug/dd_util.h"
36
37 /*
38 * pipe_context
39 */
40 static void si_destroy_context(struct pipe_context *context)
41 {
42 struct si_context *sctx = (struct si_context *)context;
43 int i;
44
45 /* Unreference the framebuffer normally to disable related logic
46 * properly.
47 */
48 struct pipe_framebuffer_state fb = {};
49 if (context->set_framebuffer_state)
50 context->set_framebuffer_state(context, &fb);
51
52 si_release_all_descriptors(sctx);
53
54 if (sctx->ce_suballocator)
55 u_suballocator_destroy(sctx->ce_suballocator);
56
57 r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
58 pipe_resource_reference(&sctx->esgs_ring, NULL);
59 pipe_resource_reference(&sctx->gsvs_ring, NULL);
60 pipe_resource_reference(&sctx->tf_ring, NULL);
61 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
62 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
63 r600_resource_reference(&sctx->border_color_buffer, NULL);
64 free(sctx->border_color_table);
65 r600_resource_reference(&sctx->scratch_buffer, NULL);
66 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
67
68 si_pm4_free_state(sctx, sctx->init_config, ~0);
69 if (sctx->init_config_gs_rings)
70 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
71 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
72 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
73
74 if (sctx->fixed_func_tcs_shader.cso)
75 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
76 if (sctx->custom_dsa_flush)
77 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
78 if (sctx->custom_blend_resolve)
79 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
80 if (sctx->custom_blend_fmask_decompress)
81 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
82 if (sctx->custom_blend_eliminate_fastclear)
83 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
84 if (sctx->custom_blend_dcc_decompress)
85 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
86
87 if (sctx->blitter)
88 util_blitter_destroy(sctx->blitter);
89
90 r600_common_context_cleanup(&sctx->b);
91
92 LLVMDisposeTargetMachine(sctx->tm);
93
94 r600_resource_reference(&sctx->trace_buf, NULL);
95 r600_resource_reference(&sctx->last_trace_buf, NULL);
96 radeon_clear_saved_cs(&sctx->last_gfx);
97
98 pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
99 util_dynarray_fini(&sctx->bindless_descriptors);
100
101 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
102 _mesa_hash_table_destroy(sctx->img_handles, NULL);
103
104 util_dynarray_fini(&sctx->resident_tex_handles);
105 util_dynarray_fini(&sctx->resident_img_handles);
106 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
107 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
108 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
109 FREE(sctx);
110 }
111
112 static enum pipe_reset_status
113 si_amdgpu_get_reset_status(struct pipe_context *ctx)
114 {
115 struct si_context *sctx = (struct si_context *)ctx;
116
117 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
118 }
119
120 /* Apitrace profiling:
121 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
122 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
123 * and remember its number.
124 * 3) In Mesa, enable queries and performance counters around that draw
125 * call and print the results.
126 * 4) glretrace --benchmark --markers ..
127 */
128 static void si_emit_string_marker(struct pipe_context *ctx,
129 const char *string, int len)
130 {
131 struct si_context *sctx = (struct si_context *)ctx;
132
133 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
134 }
135
136 static LLVMTargetMachineRef
137 si_create_llvm_target_machine(struct si_screen *sscreen)
138 {
139 const char *triple = "amdgcn--";
140 char features[256];
141
142 snprintf(features, sizeof(features),
143 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s",
144 sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
145 sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
146
147 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
148 r600_get_llvm_processor_name(sscreen->b.family),
149 features,
150 LLVMCodeGenLevelDefault,
151 LLVMRelocDefault,
152 LLVMCodeModelDefault);
153 }
154
155 static struct pipe_context *si_create_context(struct pipe_screen *screen,
156 unsigned flags)
157 {
158 struct si_context *sctx = CALLOC_STRUCT(si_context);
159 struct si_screen* sscreen = (struct si_screen *)screen;
160 struct radeon_winsys *ws = sscreen->b.ws;
161 int shader, i;
162
163 if (!sctx)
164 return NULL;
165
166 if (sscreen->b.debug_flags & DBG_CHECK_VM)
167 flags |= PIPE_CONTEXT_DEBUG;
168
169 if (flags & PIPE_CONTEXT_DEBUG)
170 sscreen->record_llvm_ir = true; /* racy but not critical */
171
172 sctx->b.b.screen = screen; /* this must be set first */
173 sctx->b.b.priv = NULL;
174 sctx->b.b.destroy = si_destroy_context;
175 sctx->b.b.emit_string_marker = si_emit_string_marker;
176 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
177 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
178 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
179
180 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
181 goto fail;
182
183 if (sscreen->b.info.drm_major == 3)
184 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
185
186 si_init_blit_functions(sctx);
187 si_init_compute_functions(sctx);
188 si_init_cp_dma_functions(sctx);
189 si_init_debug_functions(sctx);
190
191 if (sscreen->b.info.has_hw_decode) {
192 sctx->b.b.create_video_codec = si_uvd_create_decoder;
193 sctx->b.b.create_video_buffer = si_video_buffer_create;
194 } else {
195 sctx->b.b.create_video_codec = vl_create_decoder;
196 sctx->b.b.create_video_buffer = vl_video_buffer_create;
197 }
198
199 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
200 si_context_gfx_flush, sctx);
201
202 /* SI + AMDGPU + CE = GPU hang */
203 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
204 sscreen->b.chip_class != SI &&
205 /* These can't use CE due to a power gating bug in the kernel. */
206 sscreen->b.family != CHIP_CARRIZO &&
207 sscreen->b.family != CHIP_STONEY) {
208 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
209 if (!sctx->ce_ib)
210 goto fail;
211
212 if (ws->cs_add_const_preamble_ib) {
213 sctx->ce_preamble_ib =
214 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
215
216 if (!sctx->ce_preamble_ib)
217 goto fail;
218 }
219
220 sctx->ce_suballocator =
221 u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
222 PIPE_USAGE_DEFAULT,
223 R600_RESOURCE_FLAG_UNMAPPABLE, false);
224 if (!sctx->ce_suballocator)
225 goto fail;
226 }
227
228 sctx->b.gfx.flush = si_context_gfx_flush;
229
230 /* Border colors. */
231 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
232 sizeof(*sctx->border_color_table));
233 if (!sctx->border_color_table)
234 goto fail;
235
236 sctx->border_color_buffer = (struct r600_resource*)
237 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
238 SI_MAX_BORDER_COLORS *
239 sizeof(*sctx->border_color_table));
240 if (!sctx->border_color_buffer)
241 goto fail;
242
243 sctx->border_color_map =
244 ws->buffer_map(sctx->border_color_buffer->buf,
245 NULL, PIPE_TRANSFER_WRITE);
246 if (!sctx->border_color_map)
247 goto fail;
248
249 si_init_all_descriptors(sctx);
250 si_init_state_functions(sctx);
251 si_init_shader_functions(sctx);
252 si_init_ia_multi_vgt_param_table(sctx);
253
254 if (sctx->b.chip_class >= CIK)
255 cik_init_sdma_functions(sctx);
256 else
257 si_init_dma_functions(sctx);
258
259 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
260 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
261
262 sctx->blitter = util_blitter_create(&sctx->b.b);
263 if (sctx->blitter == NULL)
264 goto fail;
265 sctx->blitter->draw_rectangle = r600_draw_rectangle;
266
267 sctx->sample_mask.sample_mask = 0xffff;
268
269 /* these must be last */
270 si_begin_new_cs(sctx);
271
272 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
273 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
274 if (sctx->b.chip_class == CIK) {
275 sctx->null_const_buf.buffer =
276 r600_aligned_buffer_create(screen,
277 R600_RESOURCE_FLAG_UNMAPPABLE,
278 PIPE_USAGE_DEFAULT, 16,
279 sctx->screen->b.info.tcc_cache_line_size);
280 if (!sctx->null_const_buf.buffer)
281 goto fail;
282 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
283
284 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
285 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
286 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
287 &sctx->null_const_buf);
288 }
289 }
290
291 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
292 &sctx->null_const_buf);
293 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
294 &sctx->null_const_buf);
295 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
296 &sctx->null_const_buf);
297 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
298 &sctx->null_const_buf);
299
300 /* Clear the NULL constant buffer, because loads should return zeros. */
301 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
302 sctx->null_const_buf.buffer->width0, 0,
303 R600_COHERENCY_SHADER);
304 }
305
306 uint64_t max_threads_per_block;
307 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
308 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
309 &max_threads_per_block);
310
311 /* The maximum number of scratch waves. Scratch space isn't divided
312 * evenly between CUs. The number is only a function of the number of CUs.
313 * We can decrease the constant to decrease the scratch buffer size.
314 *
315 * sctx->scratch_waves must be >= the maximum posible size of
316 * 1 threadgroup, so that the hw doesn't hang from being unable
317 * to start any.
318 *
319 * The recommended value is 4 per CU at most. Higher numbers don't
320 * bring much benefit, but they still occupy chip resources (think
321 * async compute). I've seen ~2% performance difference between 4 and 32.
322 */
323 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
324 max_threads_per_block / 64);
325
326 sctx->tm = si_create_llvm_target_machine(sscreen);
327
328 /* Create a slab allocator for all bindless descriptors. */
329 if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
330 si_bindless_descriptor_can_reclaim_slab,
331 si_bindless_descriptor_slab_alloc,
332 si_bindless_descriptor_slab_free))
333 goto fail;
334
335 util_dynarray_init(&sctx->bindless_descriptors, NULL);
336
337 /* Bindless handles. */
338 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
339 _mesa_key_pointer_equal);
340 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
341 _mesa_key_pointer_equal);
342
343 util_dynarray_init(&sctx->resident_tex_handles, NULL);
344 util_dynarray_init(&sctx->resident_img_handles, NULL);
345 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
346 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
347 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
348
349 return &sctx->b.b;
350 fail:
351 fprintf(stderr, "radeonsi: Failed to create a context.\n");
352 si_destroy_context(&sctx->b.b);
353 return NULL;
354 }
355
356 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
357 void *priv, unsigned flags)
358 {
359 struct si_screen *sscreen = (struct si_screen *)screen;
360 struct pipe_context *ctx = si_create_context(screen, flags);
361
362 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
363 return ctx;
364
365 /* Clover (compute-only) is unsupported.
366 *
367 * Since the threaded context creates shader states from the non-driver
368 * thread, asynchronous compilation is required for create_{shader}_-
369 * state not to use pipe_context. Debug contexts (ddebug) disable
370 * asynchronous compilation, so don't use the threaded context with
371 * those.
372 */
373 if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
374 return ctx;
375
376 /* When shaders are logged to stderr, asynchronous compilation is
377 * disabled too. */
378 if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
379 DBG_PS | DBG_CS))
380 return ctx;
381
382 return threaded_context_create(ctx, &sscreen->b.pool_transfers,
383 r600_replace_buffer_storage,
384 &((struct si_context*)ctx)->b.tc);
385 }
386
387 /*
388 * pipe_screen
389 */
390 static bool si_have_tgsi_compute(struct si_screen *sscreen)
391 {
392 /* Old kernels disallowed some register writes for SI
393 * that are used for indirect dispatches. */
394 return (sscreen->b.chip_class >= CIK ||
395 sscreen->b.info.drm_major == 3 ||
396 (sscreen->b.info.drm_major == 2 &&
397 sscreen->b.info.drm_minor >= 45));
398 }
399
400 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
401 {
402 struct si_screen *sscreen = (struct si_screen *)pscreen;
403
404 switch (param) {
405 /* Supported features (boolean caps). */
406 case PIPE_CAP_ACCELERATED:
407 case PIPE_CAP_TWO_SIDED_STENCIL:
408 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
409 case PIPE_CAP_ANISOTROPIC_FILTER:
410 case PIPE_CAP_POINT_SPRITE:
411 case PIPE_CAP_OCCLUSION_QUERY:
412 case PIPE_CAP_TEXTURE_SHADOW_MAP:
413 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
414 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
415 case PIPE_CAP_TEXTURE_SWIZZLE:
416 case PIPE_CAP_DEPTH_CLIP_DISABLE:
417 case PIPE_CAP_SHADER_STENCIL_EXPORT:
418 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
419 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
420 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
421 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
422 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
423 case PIPE_CAP_SM3:
424 case PIPE_CAP_SEAMLESS_CUBE_MAP:
425 case PIPE_CAP_PRIMITIVE_RESTART:
426 case PIPE_CAP_CONDITIONAL_RENDER:
427 case PIPE_CAP_TEXTURE_BARRIER:
428 case PIPE_CAP_INDEP_BLEND_ENABLE:
429 case PIPE_CAP_INDEP_BLEND_FUNC:
430 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
431 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
432 case PIPE_CAP_USER_CONSTANT_BUFFERS:
433 case PIPE_CAP_START_INSTANCE:
434 case PIPE_CAP_NPOT_TEXTURES:
435 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
436 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
437 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
438 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
439 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
440 case PIPE_CAP_TGSI_INSTANCEID:
441 case PIPE_CAP_COMPUTE:
442 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
443 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
444 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
445 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
446 case PIPE_CAP_CUBE_MAP_ARRAY:
447 case PIPE_CAP_SAMPLE_SHADING:
448 case PIPE_CAP_DRAW_INDIRECT:
449 case PIPE_CAP_CLIP_HALFZ:
450 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
451 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
452 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
453 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
454 case PIPE_CAP_TGSI_TEXCOORD:
455 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
456 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
457 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
458 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
459 case PIPE_CAP_SHAREABLE_SHADERS:
460 case PIPE_CAP_DEPTH_BOUNDS_TEST:
461 case PIPE_CAP_SAMPLER_VIEW_TARGET:
462 case PIPE_CAP_TEXTURE_QUERY_LOD:
463 case PIPE_CAP_TEXTURE_GATHER_SM5:
464 case PIPE_CAP_TGSI_TXQS:
465 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
466 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
467 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
468 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
469 case PIPE_CAP_INVALIDATE_BUFFER:
470 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
471 case PIPE_CAP_QUERY_MEMORY_INFO:
472 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
473 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
474 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
475 case PIPE_CAP_GENERATE_MIPMAP:
476 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
477 case PIPE_CAP_STRING_MARKER:
478 case PIPE_CAP_CLEAR_TEXTURE:
479 case PIPE_CAP_CULL_DISTANCE:
480 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
481 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
482 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
483 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
484 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
485 case PIPE_CAP_DOUBLES:
486 case PIPE_CAP_TGSI_TEX_TXF_LZ:
487 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
488 case PIPE_CAP_BINDLESS_TEXTURE:
489 return 1;
490
491 case PIPE_CAP_INT64:
492 case PIPE_CAP_INT64_DIVMOD:
493 case PIPE_CAP_TGSI_CLOCK:
494 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
495 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
496 return 1;
497
498 case PIPE_CAP_TGSI_VOTE:
499 return HAVE_LLVM >= 0x0400;
500
501 case PIPE_CAP_TGSI_BALLOT:
502 return HAVE_LLVM >= 0x0500;
503
504 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
505 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
506
507 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
508 return (sscreen->b.info.drm_major == 2 &&
509 sscreen->b.info.drm_minor >= 43) ||
510 sscreen->b.info.drm_major == 3;
511
512 case PIPE_CAP_TEXTURE_MULTISAMPLE:
513 /* 2D tiling on CIK is supported since DRM 2.35.0 */
514 return sscreen->b.chip_class < CIK ||
515 (sscreen->b.info.drm_major == 2 &&
516 sscreen->b.info.drm_minor >= 35) ||
517 sscreen->b.info.drm_major == 3;
518
519 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
520 return R600_MAP_BUFFER_ALIGNMENT;
521
522 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
523 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
524 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
525 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
526 case PIPE_CAP_MAX_VERTEX_STREAMS:
527 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
528 return 4;
529
530 case PIPE_CAP_GLSL_FEATURE_LEVEL:
531 if (si_have_tgsi_compute(sscreen))
532 return 450;
533 return 420;
534
535 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
536 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
537
538 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
539 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
540 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
541 /* SI doesn't support unaligned loads.
542 * CIK needs DRM 2.50.0 on radeon. */
543 return sscreen->b.chip_class == SI ||
544 (sscreen->b.info.drm_major == 2 &&
545 sscreen->b.info.drm_minor < 50);
546
547 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
548 /* TODO: GFX9 hangs. */
549 if (sscreen->b.chip_class >= GFX9)
550 return 0;
551 /* Disable on SI due to VM faults in CP DMA. Enable once these
552 * faults are mitigated in software.
553 */
554 if (sscreen->b.chip_class >= CIK &&
555 sscreen->b.info.drm_major == 3 &&
556 sscreen->b.info.drm_minor >= 13)
557 return RADEON_SPARSE_PAGE_SIZE;
558 return 0;
559
560 /* Unsupported features. */
561 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
562 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
563 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
564 case PIPE_CAP_USER_VERTEX_BUFFERS:
565 case PIPE_CAP_FAKE_SW_MSAA:
566 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
567 case PIPE_CAP_VERTEXID_NOBASE:
568 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
569 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
570 case PIPE_CAP_NATIVE_FENCE_FD:
571 case PIPE_CAP_TGSI_FS_FBFETCH:
572 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
573 case PIPE_CAP_UMA:
574 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
575 case PIPE_CAP_POST_DEPTH_COVERAGE:
576 return 0;
577
578 case PIPE_CAP_QUERY_BUFFER_OBJECT:
579 return si_have_tgsi_compute(sscreen);
580
581 case PIPE_CAP_DRAW_PARAMETERS:
582 case PIPE_CAP_MULTI_DRAW_INDIRECT:
583 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
584 return sscreen->has_draw_indirect_multi;
585
586 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
587 return 30;
588
589 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
590 return sscreen->b.chip_class <= VI ?
591 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
592
593 /* Stream output. */
594 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
595 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
596 return 32*4;
597
598 /* Geometry shader output. */
599 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
600 return 1024;
601 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
602 return 4095;
603
604 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
605 return 2048;
606
607 /* Texturing. */
608 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
609 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
610 return 15; /* 16384 */
611 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
612 /* textures support 8192, but layered rendering supports 2048 */
613 return 12;
614 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
615 /* textures support 8192, but layered rendering supports 2048 */
616 return 2048;
617
618 /* Viewports and render targets. */
619 case PIPE_CAP_MAX_VIEWPORTS:
620 return R600_MAX_VIEWPORTS;
621 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
622 case PIPE_CAP_MAX_RENDER_TARGETS:
623 return 8;
624
625 /* Timer queries, present when the clock frequency is non zero. */
626 case PIPE_CAP_QUERY_TIMESTAMP:
627 case PIPE_CAP_QUERY_TIME_ELAPSED:
628 return sscreen->b.info.clock_crystal_freq != 0;
629
630 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
631 case PIPE_CAP_MIN_TEXEL_OFFSET:
632 return -32;
633
634 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
635 case PIPE_CAP_MAX_TEXEL_OFFSET:
636 return 31;
637
638 case PIPE_CAP_ENDIANNESS:
639 return PIPE_ENDIAN_LITTLE;
640
641 case PIPE_CAP_VENDOR_ID:
642 return ATI_VENDOR_ID;
643 case PIPE_CAP_DEVICE_ID:
644 return sscreen->b.info.pci_id;
645 case PIPE_CAP_VIDEO_MEMORY:
646 return sscreen->b.info.vram_size >> 20;
647 case PIPE_CAP_PCI_GROUP:
648 return sscreen->b.info.pci_domain;
649 case PIPE_CAP_PCI_BUS:
650 return sscreen->b.info.pci_bus;
651 case PIPE_CAP_PCI_DEVICE:
652 return sscreen->b.info.pci_dev;
653 case PIPE_CAP_PCI_FUNCTION:
654 return sscreen->b.info.pci_func;
655 }
656 return 0;
657 }
658
659 static int si_get_shader_param(struct pipe_screen* pscreen,
660 enum pipe_shader_type shader,
661 enum pipe_shader_cap param)
662 {
663 struct si_screen *sscreen = (struct si_screen *)pscreen;
664
665 switch(shader)
666 {
667 case PIPE_SHADER_FRAGMENT:
668 case PIPE_SHADER_VERTEX:
669 case PIPE_SHADER_GEOMETRY:
670 case PIPE_SHADER_TESS_CTRL:
671 case PIPE_SHADER_TESS_EVAL:
672 break;
673 case PIPE_SHADER_COMPUTE:
674 switch (param) {
675 case PIPE_SHADER_CAP_PREFERRED_IR:
676 return PIPE_SHADER_IR_NATIVE;
677
678 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
679 int ir = 1 << PIPE_SHADER_IR_NATIVE;
680
681 if (si_have_tgsi_compute(sscreen))
682 ir |= 1 << PIPE_SHADER_IR_TGSI;
683
684 return ir;
685 }
686
687 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
688 uint64_t max_const_buffer_size;
689 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
690 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
691 &max_const_buffer_size);
692 return MIN2(max_const_buffer_size, INT_MAX);
693 }
694 default:
695 /* If compute shaders don't require a special value
696 * for this cap, we can return the same value we
697 * do for other shader types. */
698 break;
699 }
700 break;
701 default:
702 return 0;
703 }
704
705 switch (param) {
706 /* Shader limits. */
707 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
708 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
709 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
710 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
711 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
712 return 16384;
713 case PIPE_SHADER_CAP_MAX_INPUTS:
714 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
715 case PIPE_SHADER_CAP_MAX_OUTPUTS:
716 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
717 case PIPE_SHADER_CAP_MAX_TEMPS:
718 return 256; /* Max native temporaries. */
719 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
720 return 4096 * sizeof(float[4]); /* actually only memory limits this */
721 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
722 return SI_NUM_CONST_BUFFERS;
723 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
724 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
725 return SI_NUM_SAMPLERS;
726 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
727 return SI_NUM_SHADER_BUFFERS;
728 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
729 return SI_NUM_IMAGES;
730 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
731 return 32;
732 case PIPE_SHADER_CAP_PREFERRED_IR:
733 return PIPE_SHADER_IR_TGSI;
734 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
735 return 3;
736
737 /* Supported boolean features. */
738 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
739 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
740 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
741 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
742 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
743 case PIPE_SHADER_CAP_INTEGERS:
744 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
745 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
746 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
747 return 1;
748
749 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
750 /* TODO: Indirection of geometry shader input dimension is not
751 * handled yet
752 */
753 return shader != PIPE_SHADER_GEOMETRY;
754
755 /* Unsupported boolean features. */
756 case PIPE_SHADER_CAP_SUBROUTINES:
757 case PIPE_SHADER_CAP_SUPPORTED_IRS:
758 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
759 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
760 return 0;
761 }
762 return 0;
763 }
764
765 static void si_destroy_screen(struct pipe_screen* pscreen)
766 {
767 struct si_screen *sscreen = (struct si_screen *)pscreen;
768 struct si_shader_part *parts[] = {
769 sscreen->vs_prologs,
770 sscreen->tcs_epilogs,
771 sscreen->gs_prologs,
772 sscreen->ps_prologs,
773 sscreen->ps_epilogs
774 };
775 unsigned i;
776
777 if (!sscreen->b.ws->unref(sscreen->b.ws))
778 return;
779
780 util_queue_destroy(&sscreen->shader_compiler_queue);
781 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
782
783 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
784 if (sscreen->tm[i])
785 LLVMDisposeTargetMachine(sscreen->tm[i]);
786
787 for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
788 if (sscreen->tm_low_priority[i])
789 LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
790
791 /* Free shader parts. */
792 for (i = 0; i < ARRAY_SIZE(parts); i++) {
793 while (parts[i]) {
794 struct si_shader_part *part = parts[i];
795
796 parts[i] = part->next;
797 radeon_shader_binary_clean(&part->binary);
798 FREE(part);
799 }
800 }
801 mtx_destroy(&sscreen->shader_parts_mutex);
802 si_destroy_shader_cache(sscreen);
803 r600_destroy_common_screen(&sscreen->b);
804 }
805
806 static bool si_init_gs_info(struct si_screen *sscreen)
807 {
808 switch (sscreen->b.family) {
809 case CHIP_OLAND:
810 case CHIP_HAINAN:
811 case CHIP_KAVERI:
812 case CHIP_KABINI:
813 case CHIP_MULLINS:
814 case CHIP_ICELAND:
815 case CHIP_CARRIZO:
816 case CHIP_STONEY:
817 sscreen->gs_table_depth = 16;
818 return true;
819 case CHIP_TAHITI:
820 case CHIP_PITCAIRN:
821 case CHIP_VERDE:
822 case CHIP_BONAIRE:
823 case CHIP_HAWAII:
824 case CHIP_TONGA:
825 case CHIP_FIJI:
826 case CHIP_POLARIS10:
827 case CHIP_POLARIS11:
828 case CHIP_POLARIS12:
829 case CHIP_VEGA10:
830 case CHIP_RAVEN:
831 sscreen->gs_table_depth = 32;
832 return true;
833 default:
834 return false;
835 }
836 }
837
838 static void si_handle_env_var_force_family(struct si_screen *sscreen)
839 {
840 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
841 unsigned i;
842
843 if (!family)
844 return;
845
846 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
847 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
848 /* Override family and chip_class. */
849 sscreen->b.family = sscreen->b.info.family = i;
850
851 if (i >= CHIP_VEGA10)
852 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
853 else if (i >= CHIP_TONGA)
854 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
855 else if (i >= CHIP_BONAIRE)
856 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
857 else
858 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
859
860 /* Don't submit any IBs. */
861 setenv("RADEON_NOOP", "1", 1);
862 return;
863 }
864 }
865
866 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
867 exit(1);
868 }
869
870 static void si_test_vmfault(struct si_screen *sscreen)
871 {
872 struct pipe_context *ctx = sscreen->b.aux_context;
873 struct si_context *sctx = (struct si_context *)ctx;
874 struct pipe_resource *buf =
875 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
876
877 if (!buf) {
878 puts("Buffer allocation failed.");
879 exit(1);
880 }
881
882 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
883
884 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
885 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
886 ctx->flush(ctx, NULL, 0);
887 puts("VM fault test: CP - done.");
888 }
889 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
890 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
891 ctx->flush(ctx, NULL, 0);
892 puts("VM fault test: SDMA - done.");
893 }
894 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
895 util_test_constant_buffer(ctx, buf);
896 puts("VM fault test: Shader - done.");
897 }
898 exit(0);
899 }
900
901 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
902 {
903 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
904 unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
905
906 if (!sscreen) {
907 return NULL;
908 }
909
910 /* Set functions first. */
911 sscreen->b.b.context_create = si_pipe_create_context;
912 sscreen->b.b.destroy = si_destroy_screen;
913 sscreen->b.b.get_param = si_get_param;
914 sscreen->b.b.get_shader_param = si_get_shader_param;
915 sscreen->b.b.resource_create = r600_resource_create_common;
916
917 si_init_screen_state_functions(sscreen);
918
919 if (!r600_common_screen_init(&sscreen->b, ws) ||
920 !si_init_gs_info(sscreen) ||
921 !si_init_shader_cache(sscreen)) {
922 FREE(sscreen);
923 return NULL;
924 }
925
926 /* Only enable as many threads as we have target machines, but at most
927 * the number of CPUs - 1 if there is more than one.
928 */
929 num_threads = sysconf(_SC_NPROCESSORS_ONLN);
930 num_threads = MAX2(1, num_threads - 1);
931 num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
932 num_compiler_threads_lowprio =
933 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
934
935 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
936 32, num_compiler_threads, 0)) {
937 si_destroy_shader_cache(sscreen);
938 FREE(sscreen);
939 return NULL;
940 }
941
942 /* The queue must be large enough so that adding optimized shaders
943 * doesn't stall draw calls when the queue is full. Especially varying
944 * packing generates a very high volume of optimized shader compilation
945 * jobs.
946 */
947 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
948 "si_shader_low",
949 1024, num_compiler_threads,
950 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
951 si_destroy_shader_cache(sscreen);
952 FREE(sscreen);
953 return NULL;
954 }
955
956 si_handle_env_var_force_family(sscreen);
957
958 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
959 si_init_perfcounters(sscreen);
960
961 /* Hawaii has a bug with offchip buffers > 256 that can be worked
962 * around by setting 4K granularity.
963 */
964 sscreen->tess_offchip_block_dw_size =
965 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
966
967 sscreen->has_distributed_tess =
968 sscreen->b.chip_class >= VI &&
969 sscreen->b.info.max_se >= 2;
970
971 sscreen->has_draw_indirect_multi =
972 (sscreen->b.family >= CHIP_POLARIS10) ||
973 (sscreen->b.chip_class == VI &&
974 sscreen->b.info.pfp_fw_version >= 121 &&
975 sscreen->b.info.me_fw_version >= 87) ||
976 (sscreen->b.chip_class == CIK &&
977 sscreen->b.info.pfp_fw_version >= 211 &&
978 sscreen->b.info.me_fw_version >= 173) ||
979 (sscreen->b.chip_class == SI &&
980 sscreen->b.info.pfp_fw_version >= 121 &&
981 sscreen->b.info.me_fw_version >= 87);
982
983 sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
984 sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
985 sscreen->b.family <= CHIP_POLARIS12) ||
986 sscreen->b.family == CHIP_VEGA10 ||
987 sscreen->b.family == CHIP_RAVEN;
988
989 sscreen->b.has_cp_dma = true;
990 sscreen->b.has_streamout = true;
991
992 /* Some chips have RB+ registers, but don't support RB+. Those must
993 * always disable it.
994 */
995 if (sscreen->b.family == CHIP_STONEY ||
996 sscreen->b.chip_class >= GFX9) {
997 sscreen->b.has_rbplus = true;
998
999 sscreen->b.rbplus_allowed =
1000 !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1001 (sscreen->b.family == CHIP_STONEY ||
1002 sscreen->b.family == CHIP_RAVEN);
1003 }
1004
1005 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1006 sscreen->use_monolithic_shaders =
1007 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1008
1009 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1010 SI_CONTEXT_INV_VMEM_L1;
1011 if (sscreen->b.chip_class <= VI)
1012 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1013
1014 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1015
1016 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1017 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1018
1019 for (i = 0; i < num_compiler_threads; i++)
1020 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1021 for (i = 0; i < num_compiler_threads_lowprio; i++)
1022 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1023
1024 /* Create the auxiliary context. This must be done last. */
1025 sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1026
1027 if (sscreen->b.debug_flags & DBG_TEST_DMA)
1028 r600_test_dma(&sscreen->b);
1029
1030 if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1031 DBG_TEST_VMFAULT_SDMA |
1032 DBG_TEST_VMFAULT_SHADER))
1033 si_test_vmfault(sscreen);
1034
1035 return &sscreen->b.b;
1036 }