src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "si_shader_internal.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_uvd.h"
  30 #include "util/hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "util/u_tests.h"
  34 #include "vl/vl_decoder.h"
  35 #include "../ddebug/dd_util.h"
  36
  37 /*
  38  * pipe_context
  39  */
  40 static void si_destroy_context(struct pipe_context *context)
  41 {
  42         struct si_context *sctx = (struct si_context *)context;
  43         int i;
  44
  45         /* Unreference the framebuffer normally to disable related logic
  46          * properly.
  47          */
  48         struct pipe_framebuffer_state fb = {};
  49         if (context->set_framebuffer_state)
  50                 context->set_framebuffer_state(context, &fb);
  51
  52         si_release_all_descriptors(sctx);
  53
  54         if (sctx->ce_suballocator)
  55                 u_suballocator_destroy(sctx->ce_suballocator);
  56
  57         r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67         r600_resource_reference(&sctx->wait_mem_scratch, NULL);
  68
  69         si_pm4_free_state(sctx, sctx->init_config, ~0);
  70         if (sctx->init_config_gs_rings)
  71                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  72         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  73                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  74
  75         if (sctx->fixed_func_tcs_shader.cso)
  76                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  77         if (sctx->custom_dsa_flush)
  78                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  79         if (sctx->custom_blend_resolve)
  80                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  81         if (sctx->custom_blend_fmask_decompress)
  82                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
  83         if (sctx->custom_blend_eliminate_fastclear)
  84                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
  85         if (sctx->custom_blend_dcc_decompress)
  86                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  87
  88         if (sctx->blitter)
  89                 util_blitter_destroy(sctx->blitter);
  90
  91         r600_common_context_cleanup(&sctx->b);
  92
  93         LLVMDisposeTargetMachine(sctx->tm);
  94
  95         r600_resource_reference(&sctx->trace_buf, NULL);
  96         r600_resource_reference(&sctx->last_trace_buf, NULL);
  97         radeon_clear_saved_cs(&sctx->last_gfx);
  98
  99         pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
 100         util_dynarray_fini(&sctx->bindless_descriptors);
 101
 102         _mesa_hash_table_destroy(sctx->tex_handles, NULL);
 103         _mesa_hash_table_destroy(sctx->img_handles, NULL);
 104
 105         util_dynarray_fini(&sctx->resident_tex_handles);
 106         util_dynarray_fini(&sctx->resident_img_handles);
 107         util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 108         util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 109         util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 110         FREE(sctx);
 111 }
 112
 113 static enum pipe_reset_status
 114 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 115 {
 116         struct si_context *sctx = (struct si_context *)ctx;
 117
 118         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 119 }
 120
 121 /* Apitrace profiling:
 122  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 123  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 124  *      and remember its number.
 125  *   3) In Mesa, enable queries and performance counters around that draw
 126  *      call and print the results.
 127  *   4) glretrace --benchmark --markers ..
 128  */
 129 static void si_emit_string_marker(struct pipe_context *ctx,
 130                                   const char *string, int len)
 131 {
 132         struct si_context *sctx = (struct si_context *)ctx;
 133
 134         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 135 }
 136
 137 static LLVMTargetMachineRef
 138 si_create_llvm_target_machine(struct si_screen *sscreen)
 139 {
 140         const char *triple = "amdgcn--";
 141         char features[256];
 142
 143         snprintf(features, sizeof(features),
 144                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s",
 145                  sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
 146                  sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
 147
 148         return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
 149                                        r600_get_llvm_processor_name(sscreen->b.family),
 150                                        features,
 151                                        LLVMCodeGenLevelDefault,
 152                                        LLVMRelocDefault,
 153                                        LLVMCodeModelDefault);
 154 }
 155
 156 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 157                                               unsigned flags)
 158 {
 159         struct si_context *sctx = CALLOC_STRUCT(si_context);
 160         struct si_screen* sscreen = (struct si_screen *)screen;
 161         struct radeon_winsys *ws = sscreen->b.ws;
 162         int shader, i;
 163
 164         if (!sctx)
 165                 return NULL;
 166
 167         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 168                 flags |= PIPE_CONTEXT_DEBUG;
 169
 170         if (flags & PIPE_CONTEXT_DEBUG)
 171                 sscreen->record_llvm_ir = true; /* racy but not critical */
 172
 173         sctx->b.b.screen = screen; /* this must be set first */
 174         sctx->b.b.priv = NULL;
 175         sctx->b.b.destroy = si_destroy_context;
 176         sctx->b.b.emit_string_marker = si_emit_string_marker;
 177         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 178         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 179         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 180
 181         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 182                 goto fail;
 183
 184         if (sscreen->b.info.drm_major == 3)
 185                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 186
 187         si_init_blit_functions(sctx);
 188         si_init_compute_functions(sctx);
 189         si_init_cp_dma_functions(sctx);
 190         si_init_debug_functions(sctx);
 191
 192         if (sscreen->b.info.has_hw_decode) {
 193                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 194                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 195         } else {
 196                 sctx->b.b.create_video_codec = vl_create_decoder;
 197                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 198         }
 199
 200         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 201                                        si_context_gfx_flush, sctx);
 202
 203         /* SI + AMDGPU + CE = GPU hang */
 204         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
 205             sscreen->b.chip_class != SI &&
 206             /* These can't use CE due to a power gating bug in the kernel. */
 207             sscreen->b.family != CHIP_CARRIZO &&
 208             sscreen->b.family != CHIP_STONEY) {
 209                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 210                 if (!sctx->ce_ib)
 211                         goto fail;
 212
 213                 if (ws->cs_add_const_preamble_ib) {
 214                         sctx->ce_preamble_ib =
 215                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 216
 217                         if (!sctx->ce_preamble_ib)
 218                                 goto fail;
 219                 }
 220
 221                 sctx->ce_suballocator =
 222                         u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
 223                                               PIPE_USAGE_DEFAULT,
 224                                               R600_RESOURCE_FLAG_UNMAPPABLE, false);
 225                 if (!sctx->ce_suballocator)
 226                         goto fail;
 227         }
 228
 229         sctx->b.gfx.flush = si_context_gfx_flush;
 230
 231         /* Border colors. */
 232         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 233                                           sizeof(*sctx->border_color_table));
 234         if (!sctx->border_color_table)
 235                 goto fail;
 236
 237         sctx->border_color_buffer = (struct r600_resource*)
 238                 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
 239                                    SI_MAX_BORDER_COLORS *
 240                                    sizeof(*sctx->border_color_table));
 241         if (!sctx->border_color_buffer)
 242                 goto fail;
 243
 244         sctx->border_color_map =
 245                 ws->buffer_map(sctx->border_color_buffer->buf,
 246                                NULL, PIPE_TRANSFER_WRITE);
 247         if (!sctx->border_color_map)
 248                 goto fail;
 249
 250         si_init_all_descriptors(sctx);
 251         si_init_state_functions(sctx);
 252         si_init_shader_functions(sctx);
 253         si_init_ia_multi_vgt_param_table(sctx);
 254
 255         if (sctx->b.chip_class >= CIK)
 256                 cik_init_sdma_functions(sctx);
 257         else
 258                 si_init_dma_functions(sctx);
 259
 260         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 261                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 262
 263         sctx->blitter = util_blitter_create(&sctx->b.b);
 264         if (sctx->blitter == NULL)
 265                 goto fail;
 266         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 267
 268         sctx->sample_mask.sample_mask = 0xffff;
 269
 270         /* these must be last */
 271         si_begin_new_cs(sctx);
 272
 273         if (sctx->b.chip_class >= GFX9) {
 274                 sctx->wait_mem_scratch = (struct r600_resource*)
 275                         pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
 276                 if (!sctx->wait_mem_scratch)
 277                         goto fail;
 278
 279                 /* Initialize the memory. */
 280                 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 281                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
 282                 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
 283                             S_370_WR_CONFIRM(1) |
 284                             S_370_ENGINE_SEL(V_370_ME));
 285                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
 286                 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
 287                 radeon_emit(cs, sctx->wait_mem_number);
 288         }
 289
 290         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
 291          * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
 292         if (sctx->b.chip_class == CIK) {
 293                 sctx->null_const_buf.buffer =
 294                         r600_aligned_buffer_create(screen,
 295                                                    R600_RESOURCE_FLAG_UNMAPPABLE,
 296                                                    PIPE_USAGE_DEFAULT, 16,
 297                                                    sctx->screen->b.info.tcc_cache_line_size);
 298                 if (!sctx->null_const_buf.buffer)
 299                         goto fail;
 300                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 301
 302                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 303                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 304                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 305                                                               &sctx->null_const_buf);
 306                         }
 307                 }
 308
 309                 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
 310                                  &sctx->null_const_buf);
 311                 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
 312                                  &sctx->null_const_buf);
 313                 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
 314                                  &sctx->null_const_buf);
 315                 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
 316                                  &sctx->null_const_buf);
 317                 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
 318                                  &sctx->null_const_buf);
 319
 320                 /* Clear the NULL constant buffer, because loads should return zeros. */
 321                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 322                                      sctx->null_const_buf.buffer->width0, 0,
 323                                      R600_COHERENCY_SHADER);
 324         }
 325
 326         uint64_t max_threads_per_block;
 327         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 328                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 329                                   &max_threads_per_block);
 330
 331         /* The maximum number of scratch waves. Scratch space isn't divided
 332          * evenly between CUs. The number is only a function of the number of CUs.
 333          * We can decrease the constant to decrease the scratch buffer size.
 334          *
 335          * sctx->scratch_waves must be >= the maximum posible size of
 336          * 1 threadgroup, so that the hw doesn't hang from being unable
 337          * to start any.
 338          *
 339          * The recommended value is 4 per CU at most. Higher numbers don't
 340          * bring much benefit, but they still occupy chip resources (think
 341          * async compute). I've seen ~2% performance difference between 4 and 32.
 342          */
 343         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 344                                    max_threads_per_block / 64);
 345
 346         sctx->tm = si_create_llvm_target_machine(sscreen);
 347
 348         /* Create a slab allocator for all bindless descriptors. */
 349         if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
 350                            si_bindless_descriptor_can_reclaim_slab,
 351                            si_bindless_descriptor_slab_alloc,
 352                            si_bindless_descriptor_slab_free))
 353                 goto fail;
 354
 355         util_dynarray_init(&sctx->bindless_descriptors, NULL);
 356
 357         /* Bindless handles. */
 358         sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 359                                                     _mesa_key_pointer_equal);
 360         sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 361                                                     _mesa_key_pointer_equal);
 362
 363         util_dynarray_init(&sctx->resident_tex_handles, NULL);
 364         util_dynarray_init(&sctx->resident_img_handles, NULL);
 365         util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
 366         util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
 367         util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
 368
 369         return &sctx->b.b;
 370 fail:
 371         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 372         si_destroy_context(&sctx->b.b);
 373         return NULL;
 374 }
 375
 376 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
 377                                                    void *priv, unsigned flags)
 378 {
 379         struct si_screen *sscreen = (struct si_screen *)screen;
 380         struct pipe_context *ctx = si_create_context(screen, flags);
 381
 382         if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
 383                 return ctx;
 384
 385         /* Clover (compute-only) is unsupported.
 386          *
 387          * Since the threaded context creates shader states from the non-driver
 388          * thread, asynchronous compilation is required for create_{shader}_-
 389          * state not to use pipe_context. Debug contexts (ddebug) disable
 390          * asynchronous compilation, so don't use the threaded context with
 391          * those.
 392          */
 393         if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
 394                 return ctx;
 395
 396         /* When shaders are logged to stderr, asynchronous compilation is
 397          * disabled too. */
 398         if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
 399                                       DBG_PS | DBG_CS))
 400                 return ctx;
 401
 402         return threaded_context_create(ctx, &sscreen->b.pool_transfers,
 403                                        r600_replace_buffer_storage,
 404                                        &((struct si_context*)ctx)->b.tc);
 405 }
 406
 407 /*
 408  * pipe_screen
 409  */
 410 static bool si_have_tgsi_compute(struct si_screen *sscreen)
 411 {
 412         /* Old kernels disallowed some register writes for SI
 413          * that are used for indirect dispatches. */
 414         return (sscreen->b.chip_class >= CIK ||
 415                 sscreen->b.info.drm_major == 3 ||
 416                 (sscreen->b.info.drm_major == 2 &&
 417                  sscreen->b.info.drm_minor >= 45));
 418 }
 419
 420 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 421 {
 422         struct si_screen *sscreen = (struct si_screen *)pscreen;
 423
 424         switch (param) {
 425         /* Supported features (boolean caps). */
 426         case PIPE_CAP_ACCELERATED:
 427         case PIPE_CAP_TWO_SIDED_STENCIL:
 428         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 429         case PIPE_CAP_ANISOTROPIC_FILTER:
 430         case PIPE_CAP_POINT_SPRITE:
 431         case PIPE_CAP_OCCLUSION_QUERY:
 432         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 433         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 434         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 435         case PIPE_CAP_TEXTURE_SWIZZLE:
 436         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 437         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 438         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 439         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 440         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 441         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 442         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 443         case PIPE_CAP_SM3:
 444         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 445         case PIPE_CAP_PRIMITIVE_RESTART:
 446         case PIPE_CAP_CONDITIONAL_RENDER:
 447         case PIPE_CAP_TEXTURE_BARRIER:
 448         case PIPE_CAP_INDEP_BLEND_ENABLE:
 449         case PIPE_CAP_INDEP_BLEND_FUNC:
 450         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 451         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 452         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 453         case PIPE_CAP_START_INSTANCE:
 454         case PIPE_CAP_NPOT_TEXTURES:
 455         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 456         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 457         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 458         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 459         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 460         case PIPE_CAP_TGSI_INSTANCEID:
 461         case PIPE_CAP_COMPUTE:
 462         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 463         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 464         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 465         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 466         case PIPE_CAP_CUBE_MAP_ARRAY:
 467         case PIPE_CAP_SAMPLE_SHADING:
 468         case PIPE_CAP_DRAW_INDIRECT:
 469         case PIPE_CAP_CLIP_HALFZ:
 470         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 471         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 472         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 473         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 474         case PIPE_CAP_TGSI_TEXCOORD:
 475         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 476         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 477         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 478         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 479         case PIPE_CAP_SHAREABLE_SHADERS:
 480         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 481         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 482         case PIPE_CAP_TEXTURE_QUERY_LOD:
 483         case PIPE_CAP_TEXTURE_GATHER_SM5:
 484         case PIPE_CAP_TGSI_TXQS:
 485         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 486         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 487         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 488         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 489         case PIPE_CAP_INVALIDATE_BUFFER:
 490         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 491         case PIPE_CAP_QUERY_MEMORY_INFO:
 492         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 493         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 494         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 495         case PIPE_CAP_GENERATE_MIPMAP:
 496         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 497         case PIPE_CAP_STRING_MARKER:
 498         case PIPE_CAP_CLEAR_TEXTURE:
 499         case PIPE_CAP_CULL_DISTANCE:
 500         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 501         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 502         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 503         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 504         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 505         case PIPE_CAP_DOUBLES:
 506         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 507         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 508         case PIPE_CAP_BINDLESS_TEXTURE:
 509                 return 1;
 510
 511         case PIPE_CAP_INT64:
 512         case PIPE_CAP_INT64_DIVMOD:
 513         case PIPE_CAP_TGSI_CLOCK:
 514         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 515         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 516                 return 1;
 517
 518         case PIPE_CAP_TGSI_VOTE:
 519                 return HAVE_LLVM >= 0x0400;
 520
 521         case PIPE_CAP_TGSI_BALLOT:
 522                 return HAVE_LLVM >= 0x0500;
 523
 524         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 525                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 526
 527         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 528                 return (sscreen->b.info.drm_major == 2 &&
 529                         sscreen->b.info.drm_minor >= 43) ||
 530                        sscreen->b.info.drm_major == 3;
 531
 532         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 533                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 534                 return sscreen->b.chip_class < CIK ||
 535                        (sscreen->b.info.drm_major == 2 &&
 536                         sscreen->b.info.drm_minor >= 35) ||
 537                        sscreen->b.info.drm_major == 3;
 538
 539         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 540                 return R600_MAP_BUFFER_ALIGNMENT;
 541
 542         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 543         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 544         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 545         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 546         case PIPE_CAP_MAX_VERTEX_STREAMS:
 547         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 548                 return 4;
 549
 550         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 551                 if (si_have_tgsi_compute(sscreen))
 552                         return 450;
 553                 return 420;
 554
 555         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 556                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 557
 558         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 559         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 560         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 561                 /* SI doesn't support unaligned loads.
 562                  * CIK needs DRM 2.50.0 on radeon. */
 563                 return sscreen->b.chip_class == SI ||
 564                        (sscreen->b.info.drm_major == 2 &&
 565                         sscreen->b.info.drm_minor < 50);
 566
 567         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 568                 /* TODO: GFX9 hangs. */
 569                 if (sscreen->b.chip_class >= GFX9)
 570                         return 0;
 571                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 572                  * faults are mitigated in software.
 573                  */
 574                 if (sscreen->b.chip_class >= CIK &&
 575                     sscreen->b.info.drm_major == 3 &&
 576                     sscreen->b.info.drm_minor >= 13)
 577                         return RADEON_SPARSE_PAGE_SIZE;
 578                 return 0;
 579
 580         /* Unsupported features. */
 581         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 582         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 583         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 584         case PIPE_CAP_USER_VERTEX_BUFFERS:
 585         case PIPE_CAP_FAKE_SW_MSAA:
 586         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 587         case PIPE_CAP_VERTEXID_NOBASE:
 588         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 589         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 590         case PIPE_CAP_NATIVE_FENCE_FD:
 591         case PIPE_CAP_TGSI_FS_FBFETCH:
 592         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 593         case PIPE_CAP_UMA:
 594         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 595         case PIPE_CAP_POST_DEPTH_COVERAGE:
 596                 return 0;
 597
 598         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 599                 return si_have_tgsi_compute(sscreen);
 600
 601         case PIPE_CAP_DRAW_PARAMETERS:
 602         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 603         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 604                 return sscreen->has_draw_indirect_multi;
 605
 606         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 607                 return 30;
 608
 609         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 610                 return sscreen->b.chip_class <= VI ?
 611                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 612
 613         /* Stream output. */
 614         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 615         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 616                 return 32*4;
 617
 618         /* Geometry shader output. */
 619         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 620                 return 1024;
 621         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 622                 return 4095;
 623
 624         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 625                 return 2048;
 626
 627         /* Texturing. */
 628         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 629         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 630                 return 15; /* 16384 */
 631         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 632                 /* textures support 8192, but layered rendering supports 2048 */
 633                 return 12;
 634         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 635                 /* textures support 8192, but layered rendering supports 2048 */
 636                 return 2048;
 637
 638         /* Viewports and render targets. */
 639         case PIPE_CAP_MAX_VIEWPORTS:
 640                 return R600_MAX_VIEWPORTS;
 641         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 642         case PIPE_CAP_MAX_RENDER_TARGETS:
 643                 return 8;
 644
 645         /* Timer queries, present when the clock frequency is non zero. */
 646         case PIPE_CAP_QUERY_TIMESTAMP:
 647         case PIPE_CAP_QUERY_TIME_ELAPSED:
 648                 return sscreen->b.info.clock_crystal_freq != 0;
 649
 650         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 651         case PIPE_CAP_MIN_TEXEL_OFFSET:
 652                 return -32;
 653
 654         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 655         case PIPE_CAP_MAX_TEXEL_OFFSET:
 656                 return 31;
 657
 658         case PIPE_CAP_ENDIANNESS:
 659                 return PIPE_ENDIAN_LITTLE;
 660
 661         case PIPE_CAP_VENDOR_ID:
 662                 return ATI_VENDOR_ID;
 663         case PIPE_CAP_DEVICE_ID:
 664                 return sscreen->b.info.pci_id;
 665         case PIPE_CAP_VIDEO_MEMORY:
 666                 return sscreen->b.info.vram_size >> 20;
 667         case PIPE_CAP_PCI_GROUP:
 668                 return sscreen->b.info.pci_domain;
 669         case PIPE_CAP_PCI_BUS:
 670                 return sscreen->b.info.pci_bus;
 671         case PIPE_CAP_PCI_DEVICE:
 672                 return sscreen->b.info.pci_dev;
 673         case PIPE_CAP_PCI_FUNCTION:
 674                 return sscreen->b.info.pci_func;
 675         }
 676         return 0;
 677 }
 678
 679 static int si_get_shader_param(struct pipe_screen* pscreen,
 680                                enum pipe_shader_type shader,
 681                                enum pipe_shader_cap param)
 682 {
 683         struct si_screen *sscreen = (struct si_screen *)pscreen;
 684
 685         switch(shader)
 686         {
 687         case PIPE_SHADER_FRAGMENT:
 688         case PIPE_SHADER_VERTEX:
 689         case PIPE_SHADER_GEOMETRY:
 690         case PIPE_SHADER_TESS_CTRL:
 691         case PIPE_SHADER_TESS_EVAL:
 692                 break;
 693         case PIPE_SHADER_COMPUTE:
 694                 switch (param) {
 695                 case PIPE_SHADER_CAP_PREFERRED_IR:
 696                         return PIPE_SHADER_IR_NATIVE;
 697
 698                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 699                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 700
 701                         if (si_have_tgsi_compute(sscreen))
 702                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 703
 704                         return ir;
 705                 }
 706
 707                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 708                         uint64_t max_const_buffer_size;
 709                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 710                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 711                                 &max_const_buffer_size);
 712                         return MIN2(max_const_buffer_size, INT_MAX);
 713                 }
 714                 default:
 715                         /* If compute shaders don't require a special value
 716                          * for this cap, we can return the same value we
 717                          * do for other shader types. */
 718                         break;
 719                 }
 720                 break;
 721         default:
 722                 return 0;
 723         }
 724
 725         switch (param) {
 726         /* Shader limits. */
 727         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 728         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 729         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 730         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 731         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 732                 return 16384;
 733         case PIPE_SHADER_CAP_MAX_INPUTS:
 734                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 735         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 736                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 737         case PIPE_SHADER_CAP_MAX_TEMPS:
 738                 return 256; /* Max native temporaries. */
 739         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 740                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 741         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 742                 return SI_NUM_CONST_BUFFERS;
 743         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 744         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 745                 return SI_NUM_SAMPLERS;
 746         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 747                 return SI_NUM_SHADER_BUFFERS;
 748         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 749                 return SI_NUM_IMAGES;
 750         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 751                 return 32;
 752         case PIPE_SHADER_CAP_PREFERRED_IR:
 753                 return PIPE_SHADER_IR_TGSI;
 754         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 755                 return 3;
 756
 757         /* Supported boolean features. */
 758         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 759         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 760         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 761         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 762         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 763         case PIPE_SHADER_CAP_INTEGERS:
 764         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 765         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 766         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 767                 return 1;
 768
 769         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 770                 /* TODO: Indirection of geometry shader input dimension is not
 771                  * handled yet
 772                  */
 773                 return shader != PIPE_SHADER_GEOMETRY;
 774
 775         /* Unsupported boolean features. */
 776         case PIPE_SHADER_CAP_SUBROUTINES:
 777         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 778         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 779         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 780                 return 0;
 781         }
 782         return 0;
 783 }
 784
 785 static void si_destroy_screen(struct pipe_screen* pscreen)
 786 {
 787         struct si_screen *sscreen = (struct si_screen *)pscreen;
 788         struct si_shader_part *parts[] = {
 789                 sscreen->vs_prologs,
 790                 sscreen->tcs_epilogs,
 791                 sscreen->gs_prologs,
 792                 sscreen->ps_prologs,
 793                 sscreen->ps_epilogs
 794         };
 795         unsigned i;
 796
 797         if (!sscreen->b.ws->unref(sscreen->b.ws))
 798                 return;
 799
 800         util_queue_destroy(&sscreen->shader_compiler_queue);
 801         util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
 802
 803         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 804                 if (sscreen->tm[i])
 805                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 806
 807         for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
 808                 if (sscreen->tm_low_priority[i])
 809                         LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
 810
 811         /* Free shader parts. */
 812         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 813                 while (parts[i]) {
 814                         struct si_shader_part *part = parts[i];
 815
 816                         parts[i] = part->next;
 817                         radeon_shader_binary_clean(&part->binary);
 818                         FREE(part);
 819                 }
 820         }
 821         mtx_destroy(&sscreen->shader_parts_mutex);
 822         si_destroy_shader_cache(sscreen);
 823         r600_destroy_common_screen(&sscreen->b);
 824 }
 825
 826 static bool si_init_gs_info(struct si_screen *sscreen)
 827 {
 828         switch (sscreen->b.family) {
 829         case CHIP_OLAND:
 830         case CHIP_HAINAN:
 831         case CHIP_KAVERI:
 832         case CHIP_KABINI:
 833         case CHIP_MULLINS:
 834         case CHIP_ICELAND:
 835         case CHIP_CARRIZO:
 836         case CHIP_STONEY:
 837                 sscreen->gs_table_depth = 16;
 838                 return true;
 839         case CHIP_TAHITI:
 840         case CHIP_PITCAIRN:
 841         case CHIP_VERDE:
 842         case CHIP_BONAIRE:
 843         case CHIP_HAWAII:
 844         case CHIP_TONGA:
 845         case CHIP_FIJI:
 846         case CHIP_POLARIS10:
 847         case CHIP_POLARIS11:
 848         case CHIP_POLARIS12:
 849         case CHIP_VEGA10:
 850         case CHIP_RAVEN:
 851                 sscreen->gs_table_depth = 32;
 852                 return true;
 853         default:
 854                 return false;
 855         }
 856 }
 857
 858 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 859 {
 860         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 861         unsigned i;
 862
 863         if (!family)
 864                 return;
 865
 866         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 867                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 868                         /* Override family and chip_class. */
 869                         sscreen->b.family = sscreen->b.info.family = i;
 870
 871                         if (i >= CHIP_VEGA10)
 872                                 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
 873                         else if (i >= CHIP_TONGA)
 874                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 875                         else if (i >= CHIP_BONAIRE)
 876                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 877                         else
 878                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 879
 880                         /* Don't submit any IBs. */
 881                         setenv("RADEON_NOOP", "1", 1);
 882                         return;
 883                 }
 884         }
 885
 886         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 887         exit(1);
 888 }
 889
 890 static void si_test_vmfault(struct si_screen *sscreen)
 891 {
 892         struct pipe_context *ctx = sscreen->b.aux_context;
 893         struct si_context *sctx = (struct si_context *)ctx;
 894         struct pipe_resource *buf =
 895                 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
 896
 897         if (!buf) {
 898                 puts("Buffer allocation failed.");
 899                 exit(1);
 900         }
 901
 902         r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
 903
 904         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
 905                 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
 906                 ctx->flush(ctx, NULL, 0);
 907                 puts("VM fault test: CP - done.");
 908         }
 909         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
 910                 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
 911                 ctx->flush(ctx, NULL, 0);
 912                 puts("VM fault test: SDMA - done.");
 913         }
 914         if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
 915                 util_test_constant_buffer(ctx, buf);
 916                 puts("VM fault test: Shader - done.");
 917         }
 918         exit(0);
 919 }
 920
 921 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 922                                            unsigned flags)
 923 {
 924         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 925         unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
 926
 927         if (!sscreen) {
 928                 return NULL;
 929         }
 930
 931         /* Set functions first. */
 932         sscreen->b.b.context_create = si_pipe_create_context;
 933         sscreen->b.b.destroy = si_destroy_screen;
 934         sscreen->b.b.get_param = si_get_param;
 935         sscreen->b.b.get_shader_param = si_get_shader_param;
 936         sscreen->b.b.resource_create = r600_resource_create_common;
 937
 938         si_init_screen_state_functions(sscreen);
 939
 940         if (!r600_common_screen_init(&sscreen->b, ws, flags) ||
 941             !si_init_gs_info(sscreen) ||
 942             !si_init_shader_cache(sscreen)) {
 943                 FREE(sscreen);
 944                 return NULL;
 945         }
 946
 947         /* Only enable as many threads as we have target machines, but at most
 948          * the number of CPUs - 1 if there is more than one.
 949          */
 950         num_threads = sysconf(_SC_NPROCESSORS_ONLN);
 951         num_threads = MAX2(1, num_threads - 1);
 952         num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
 953         num_compiler_threads_lowprio =
 954                 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
 955
 956         if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 957                              32, num_compiler_threads, 0)) {
 958                 si_destroy_shader_cache(sscreen);
 959                 FREE(sscreen);
 960                 return NULL;
 961         }
 962
 963         /* The queue must be large enough so that adding optimized shaders
 964          * doesn't stall draw calls when the queue is full. Especially varying
 965          * packing generates a very high volume of optimized shader compilation
 966          * jobs.
 967          */
 968         if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
 969                              "si_shader_low",
 970                              1024, num_compiler_threads,
 971                              UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
 972                si_destroy_shader_cache(sscreen);
 973                FREE(sscreen);
 974                return NULL;
 975         }
 976
 977         si_handle_env_var_force_family(sscreen);
 978
 979         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 980                 si_init_perfcounters(sscreen);
 981
 982         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 983          * around by setting 4K granularity.
 984          */
 985         sscreen->tess_offchip_block_dw_size =
 986                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 987
 988         sscreen->has_distributed_tess =
 989                 sscreen->b.chip_class >= VI &&
 990                 sscreen->b.info.max_se >= 2;
 991
 992         sscreen->has_draw_indirect_multi =
 993                 (sscreen->b.family >= CHIP_POLARIS10) ||
 994                 (sscreen->b.chip_class == VI &&
 995                  sscreen->b.info.pfp_fw_version >= 121 &&
 996                  sscreen->b.info.me_fw_version >= 87) ||
 997                 (sscreen->b.chip_class == CIK &&
 998                  sscreen->b.info.pfp_fw_version >= 211 &&
 999                  sscreen->b.info.me_fw_version >= 173) ||
1000                 (sscreen->b.chip_class == SI &&
1001                  sscreen->b.info.pfp_fw_version >= 121 &&
1002                  sscreen->b.info.me_fw_version >= 87);
1003
1004         sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
1005         sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1006                                             sscreen->b.family <= CHIP_POLARIS12) ||
1007                                            sscreen->b.family == CHIP_VEGA10 ||
1008                                            sscreen->b.family == CHIP_RAVEN;
1009
1010         sscreen->b.has_cp_dma = true;
1011         sscreen->b.has_streamout = true;
1012
1013         /* Some chips have RB+ registers, but don't support RB+. Those must
1014          * always disable it.
1015          */
1016         if (sscreen->b.family == CHIP_STONEY ||
1017             sscreen->b.chip_class >= GFX9) {
1018                 sscreen->b.has_rbplus = true;
1019
1020                 sscreen->b.rbplus_allowed =
1021                         !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1022                         (sscreen->b.family == CHIP_STONEY ||
1023                          sscreen->b.family == CHIP_RAVEN);
1024         }
1025
1026         (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1027         sscreen->use_monolithic_shaders =
1028                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1029
1030         sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1031                                             SI_CONTEXT_INV_VMEM_L1;
1032         if (sscreen->b.chip_class <= VI)
1033                 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1034
1035         sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1036
1037         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1038                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1039
1040         for (i = 0; i < num_compiler_threads; i++)
1041                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1042         for (i = 0; i < num_compiler_threads_lowprio; i++)
1043                 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1044
1045         /* Create the auxiliary context. This must be done last. */
1046         sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1047
1048         if (sscreen->b.debug_flags & DBG_TEST_DMA)
1049                 r600_test_dma(&sscreen->b);
1050
1051         if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1052                                       DBG_TEST_VMFAULT_SDMA |
1053                                       DBG_TEST_VMFAULT_SHADER))
1054                 si_test_vmfault(sscreen);
1055
1056         return &sscreen->b.b;
1057 }