radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "sid.h"
27
28 #include "radeon/radeon_uvd.h"
29 #include "util/u_memory.h"
30 #include "vl/vl_decoder.h"
31
32 /*
33 * pipe_context
34 */
35 static void si_destroy_context(struct pipe_context *context)
36 {
37 struct si_context *sctx = (struct si_context *)context;
38
39 si_release_all_descriptors(sctx);
40
41 pipe_resource_reference(&sctx->esgs_ring, NULL);
42 pipe_resource_reference(&sctx->gsvs_ring, NULL);
43 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
44 r600_resource_reference(&sctx->border_color_table, NULL);
45
46 si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
47 si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
48 si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
49
50 if (sctx->dummy_pixel_shader) {
51 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
52 }
53 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
54 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
55 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
56 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
57 util_unreference_framebuffer_state(&sctx->framebuffer.state);
58
59 util_blitter_destroy(sctx->blitter);
60
61 si_pm4_cleanup(sctx);
62
63 r600_common_context_cleanup(&sctx->b);
64 FREE(sctx);
65 }
66
67 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
68 {
69 struct si_context *sctx = CALLOC_STRUCT(si_context);
70 struct si_screen* sscreen = (struct si_screen *)screen;
71 struct radeon_winsys *ws = sscreen->b.ws;
72 int shader, i;
73
74 if (sctx == NULL)
75 return NULL;
76
77 sctx->b.b.screen = screen; /* this must be set first */
78 sctx->b.b.priv = priv;
79 sctx->b.b.destroy = si_destroy_context;
80 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
81
82 if (!r600_common_context_init(&sctx->b, &sscreen->b))
83 goto fail;
84
85 si_init_blit_functions(sctx);
86 si_init_compute_functions(sctx);
87
88 if (sscreen->b.info.has_uvd) {
89 sctx->b.b.create_video_codec = si_uvd_create_decoder;
90 sctx->b.b.create_video_buffer = si_video_buffer_create;
91 } else {
92 sctx->b.b.create_video_codec = vl_create_decoder;
93 sctx->b.b.create_video_buffer = vl_video_buffer_create;
94 }
95
96 sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
97 sctx, sscreen->b.trace_bo ?
98 sscreen->b.trace_bo->cs_buf : NULL);
99 sctx->b.rings.gfx.flush = si_context_gfx_flush;
100
101 si_init_all_descriptors(sctx);
102
103 /* Initialize cache_flush. */
104 sctx->cache_flush = si_atom_cache_flush;
105 sctx->atoms.s.cache_flush = &sctx->cache_flush;
106
107 sctx->msaa_config = si_atom_msaa_config;
108 sctx->atoms.s.msaa_config = &sctx->msaa_config;
109
110 sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
111 sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
112
113 switch (sctx->b.chip_class) {
114 case SI:
115 case CIK:
116 si_init_state_functions(sctx);
117 si_init_shader_functions(sctx);
118 si_init_config(sctx);
119 break;
120 default:
121 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
122 goto fail;
123 }
124
125 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
126 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
127
128 sctx->blitter = util_blitter_create(&sctx->b.b);
129 if (sctx->blitter == NULL)
130 goto fail;
131 sctx->blitter->draw_rectangle = r600_draw_rectangle;
132
133 /* these must be last */
134 si_begin_new_cs(sctx);
135 r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
136
137 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
138 * with a NULL buffer). We need to use a dummy buffer instead. */
139 if (sctx->b.chip_class == CIK) {
140 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
141 PIPE_USAGE_DEFAULT, 16);
142 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
143
144 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
145 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
146 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
147 &sctx->null_const_buf);
148 }
149 }
150
151 /* Clear the NULL constant buffer, because loads should return zeros. */
152 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
153 sctx->null_const_buf.buffer->width0, 0);
154 }
155
156 return &sctx->b.b;
157 fail:
158 si_destroy_context(&sctx->b.b);
159 return NULL;
160 }
161
162 /*
163 * pipe_screen
164 */
165
166 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
167 {
168 struct si_screen *sscreen = (struct si_screen *)pscreen;
169
170 switch (param) {
171 /* Supported features (boolean caps). */
172 case PIPE_CAP_TWO_SIDED_STENCIL:
173 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
174 case PIPE_CAP_ANISOTROPIC_FILTER:
175 case PIPE_CAP_POINT_SPRITE:
176 case PIPE_CAP_OCCLUSION_QUERY:
177 case PIPE_CAP_TEXTURE_SHADOW_MAP:
178 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
179 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
180 case PIPE_CAP_TEXTURE_SWIZZLE:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_SHADER_STENCIL_EXPORT:
183 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
184 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
185 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
186 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
187 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
188 case PIPE_CAP_SM3:
189 case PIPE_CAP_SEAMLESS_CUBE_MAP:
190 case PIPE_CAP_PRIMITIVE_RESTART:
191 case PIPE_CAP_CONDITIONAL_RENDER:
192 case PIPE_CAP_TEXTURE_BARRIER:
193 case PIPE_CAP_INDEP_BLEND_ENABLE:
194 case PIPE_CAP_INDEP_BLEND_FUNC:
195 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
196 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
197 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
198 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
199 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
200 case PIPE_CAP_USER_INDEX_BUFFERS:
201 case PIPE_CAP_USER_CONSTANT_BUFFERS:
202 case PIPE_CAP_START_INSTANCE:
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
206 case PIPE_CAP_TGSI_INSTANCEID:
207 case PIPE_CAP_COMPUTE:
208 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
209 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
210 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
211 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
212 case PIPE_CAP_CUBE_MAP_ARRAY:
213 case PIPE_CAP_SAMPLE_SHADING:
214 case PIPE_CAP_DRAW_INDIRECT:
215 case PIPE_CAP_CLIP_HALFZ:
216 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
217 return 1;
218
219 case PIPE_CAP_TEXTURE_MULTISAMPLE:
220 /* 2D tiling on CIK is supported since DRM 2.35.0 */
221 return sscreen->b.chip_class < CIK ||
222 sscreen->b.info.drm_minor >= 35;
223
224 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
225 return R600_MAP_BUFFER_ALIGNMENT;
226
227 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
228 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
229 return 4;
230
231 case PIPE_CAP_GLSL_FEATURE_LEVEL:
232 return 330;
233
234 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
235 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
236
237 case PIPE_CAP_TEXTURE_QUERY_LOD:
238 case PIPE_CAP_TEXTURE_GATHER_SM5:
239 return HAVE_LLVM >= 0x0305;
240 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
241 return HAVE_LLVM >= 0x0305 ? 4 : 0;
242
243 /* Unsupported features. */
244 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
245 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
246 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
247 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
248 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
249 case PIPE_CAP_USER_VERTEX_BUFFERS:
250 case PIPE_CAP_TGSI_TEXCOORD:
251 case PIPE_CAP_FAKE_SW_MSAA:
252 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
253 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
254 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
255 case PIPE_CAP_SAMPLER_VIEW_TARGET:
256 case PIPE_CAP_VERTEXID_NOBASE:
257 return 0;
258
259 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
260 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
261
262 /* Stream output. */
263 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
264 return sscreen->b.has_streamout ? 4 : 0;
265 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
266 return sscreen->b.has_streamout ? 1 : 0;
267 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
268 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
269 return sscreen->b.has_streamout ? 32*4 : 0;
270
271 /* Geometry shader output. */
272 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
273 return 1024;
274 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
275 return 4095;
276 case PIPE_CAP_MAX_VERTEX_STREAMS:
277 return 1;
278
279 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
280 return 2048;
281
282 /* Texturing. */
283 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
284 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
285 return 15; /* 16384 */
286 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
287 /* textures support 8192, but layered rendering supports 2048 */
288 return 12;
289 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
290 /* textures support 8192, but layered rendering supports 2048 */
291 return 2048;
292
293 /* Render targets. */
294 case PIPE_CAP_MAX_RENDER_TARGETS:
295 return 8;
296
297 case PIPE_CAP_MAX_VIEWPORTS:
298 return 1;
299
300 /* Timer queries, present when the clock frequency is non zero. */
301 case PIPE_CAP_QUERY_TIMESTAMP:
302 case PIPE_CAP_QUERY_TIME_ELAPSED:
303 return sscreen->b.info.r600_clock_crystal_freq != 0;
304
305 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
306 case PIPE_CAP_MIN_TEXEL_OFFSET:
307 return -32;
308
309 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
310 case PIPE_CAP_MAX_TEXEL_OFFSET:
311 return 31;
312
313 case PIPE_CAP_ENDIANNESS:
314 return PIPE_ENDIAN_LITTLE;
315
316 case PIPE_CAP_VENDOR_ID:
317 return 0x1002;
318 case PIPE_CAP_DEVICE_ID:
319 return sscreen->b.info.pci_id;
320 case PIPE_CAP_ACCELERATED:
321 return 1;
322 case PIPE_CAP_VIDEO_MEMORY:
323 return sscreen->b.info.vram_size >> 20;
324 case PIPE_CAP_UMA:
325 return 0;
326 }
327 return 0;
328 }
329
330 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
331 {
332 switch(shader)
333 {
334 case PIPE_SHADER_FRAGMENT:
335 case PIPE_SHADER_VERTEX:
336 case PIPE_SHADER_GEOMETRY:
337 break;
338 case PIPE_SHADER_COMPUTE:
339 switch (param) {
340 case PIPE_SHADER_CAP_PREFERRED_IR:
341 #if HAVE_LLVM < 0x0306
342 return PIPE_SHADER_IR_LLVM;
343 #else
344 return PIPE_SHADER_IR_NATIVE;
345 #endif
346 case PIPE_SHADER_CAP_DOUBLES:
347 return 0; /* XXX: Enable doubles once the compiler can
348 handle them. */
349 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
350 uint64_t max_const_buffer_size;
351 pscreen->get_compute_param(pscreen,
352 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
353 &max_const_buffer_size);
354 return max_const_buffer_size;
355 }
356 default:
357 return 0;
358 }
359 default:
360 /* TODO: support tessellation */
361 return 0;
362 }
363
364 switch (param) {
365 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
366 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
367 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
368 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
369 return 16384;
370 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
371 return 32;
372 case PIPE_SHADER_CAP_MAX_INPUTS:
373 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
374 case PIPE_SHADER_CAP_MAX_OUTPUTS:
375 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
376 case PIPE_SHADER_CAP_MAX_TEMPS:
377 return 256; /* Max native temporaries. */
378 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
379 return 4096 * sizeof(float[4]); /* actually only memory limits this */
380 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
381 return SI_NUM_USER_CONST_BUFFERS;
382 case PIPE_SHADER_CAP_MAX_PREDS:
383 return 0; /* FIXME */
384 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
385 return 1;
386 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
387 return 0;
388 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
389 /* Indirection of geometry shader input dimension is not
390 * handled yet
391 */
392 return shader < PIPE_SHADER_GEOMETRY;
393 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
394 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
395 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
396 return 1;
397 case PIPE_SHADER_CAP_INTEGERS:
398 return 1;
399 case PIPE_SHADER_CAP_SUBROUTINES:
400 return 0;
401 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
402 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
403 return 16;
404 case PIPE_SHADER_CAP_PREFERRED_IR:
405 return PIPE_SHADER_IR_TGSI;
406 case PIPE_SHADER_CAP_DOUBLES:
407 return 0;
408 }
409 return 0;
410 }
411
412 static void si_destroy_screen(struct pipe_screen* pscreen)
413 {
414 struct si_screen *sscreen = (struct si_screen *)pscreen;
415
416 if (sscreen == NULL)
417 return;
418
419 if (!sscreen->b.ws->unref(sscreen->b.ws))
420 return;
421
422 r600_destroy_common_screen(&sscreen->b);
423 }
424
425 #define SI_TILE_MODE_COLOR_2D_8BPP 14
426
427 /* Initialize pipe config. This is especially important for GPUs
428 * with 16 pipes and more where it's initialized incorrectly by
429 * the TILING_CONFIG ioctl. */
430 static bool si_initialize_pipe_config(struct si_screen *sscreen)
431 {
432 unsigned mode2d;
433
434 /* This is okay, because there can be no 2D tiling without
435 * the tile mode array, so we won't need the pipe config.
436 * Return "success".
437 */
438 if (!sscreen->b.info.si_tile_mode_array_valid)
439 return true;
440
441 /* The same index is used for the 2D mode on CIK too. */
442 mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
443
444 switch (G_009910_PIPE_CONFIG(mode2d)) {
445 case V_02803C_ADDR_SURF_P2:
446 sscreen->b.tiling_info.num_channels = 2;
447 break;
448 case V_02803C_X_ADDR_SURF_P4_8X16:
449 case V_02803C_X_ADDR_SURF_P4_16X16:
450 case V_02803C_X_ADDR_SURF_P4_16X32:
451 case V_02803C_X_ADDR_SURF_P4_32X32:
452 sscreen->b.tiling_info.num_channels = 4;
453 break;
454 case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
455 case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
456 case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
457 case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
458 case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
459 case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
460 case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
461 sscreen->b.tiling_info.num_channels = 8;
462 break;
463 case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
464 case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
465 sscreen->b.tiling_info.num_channels = 16;
466 break;
467 default:
468 assert(0);
469 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
470 G_009910_PIPE_CONFIG(mode2d));
471 return false;
472 }
473 return true;
474 }
475
476 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
477 {
478 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
479 if (sscreen == NULL) {
480 return NULL;
481 }
482
483 /* Set functions first. */
484 sscreen->b.b.context_create = si_create_context;
485 sscreen->b.b.destroy = si_destroy_screen;
486 sscreen->b.b.get_param = si_get_param;
487 sscreen->b.b.get_shader_param = si_get_shader_param;
488 sscreen->b.b.is_format_supported = si_is_format_supported;
489 sscreen->b.b.resource_create = r600_resource_create_common;
490
491 if (!r600_common_screen_init(&sscreen->b, ws) ||
492 !si_initialize_pipe_config(sscreen)) {
493 FREE(sscreen);
494 return NULL;
495 }
496
497 sscreen->b.has_cp_dma = true;
498 sscreen->b.has_streamout = true;
499
500 if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
501 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
502
503 /* Create the auxiliary context. This must be done last. */
504 sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
505
506 return &sscreen->b.b;
507 }