src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26 #include "sid.h"
  27
  28 #include "radeon/radeon_uvd.h"
  29 #include "util/u_memory.h"
  30 #include "vl/vl_decoder.h"
  31
  32 /*
  33  * pipe_context
  34  */
  35 static void si_destroy_context(struct pipe_context *context)
  36 {
  37         struct si_context *sctx = (struct si_context *)context;
  38
  39         si_release_all_descriptors(sctx);
  40
  41         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  42         r600_resource_reference(&sctx->border_color_table, NULL);
  43
  44         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  45         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  46         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  47
  48         if (sctx->dummy_pixel_shader) {
  49                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  50         }
  51         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  52         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  53         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  54         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  55         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  56
  57         util_blitter_destroy(sctx->blitter);
  58
  59         si_pm4_cleanup(sctx);
  60
  61         r600_common_context_cleanup(&sctx->b);
  62         FREE(sctx);
  63 }
  64
  65 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  66 {
  67         struct si_context *sctx = CALLOC_STRUCT(si_context);
  68         struct si_screen* sscreen = (struct si_screen *)screen;
  69         struct radeon_winsys *ws = sscreen->b.ws;
  70         int shader, i;
  71
  72         if (sctx == NULL)
  73                 return NULL;
  74
  75         sctx->b.b.screen = screen; /* this must be set first */
  76         sctx->b.b.priv = priv;
  77         sctx->b.b.destroy = si_destroy_context;
  78         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  79
  80         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  81                 goto fail;
  82
  83         si_init_blit_functions(sctx);
  84         si_init_compute_functions(sctx);
  85
  86         if (sscreen->b.info.has_uvd) {
  87                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  88                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  89         } else {
  90                 sctx->b.b.create_video_codec = vl_create_decoder;
  91                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
  92         }
  93
  94         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
  95                                              sctx, NULL);
  96         sctx->b.rings.gfx.flush = si_context_gfx_flush;
  97
  98         si_init_all_descriptors(sctx);
  99
 100         /* Initialize cache_flush. */
 101         sctx->cache_flush = si_atom_cache_flush;
 102         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 103
 104         sctx->msaa_config = si_atom_msaa_config;
 105         sctx->atoms.s.msaa_config = &sctx->msaa_config;
 106
 107         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 108         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 109
 110         switch (sctx->b.chip_class) {
 111         case SI:
 112         case CIK:
 113                 si_init_state_functions(sctx);
 114                 si_init_config(sctx);
 115                 break;
 116         default:
 117                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 118                 goto fail;
 119         }
 120
 121         sctx->blitter = util_blitter_create(&sctx->b.b);
 122         if (sctx->blitter == NULL)
 123                 goto fail;
 124         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 125
 126         /* these must be last */
 127         si_begin_new_cs(sctx);
 128         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 129
 130         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 131          * with a NULL buffer). We need to use a dummy buffer instead. */
 132         if (sctx->b.chip_class == CIK) {
 133                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 134                                                                  PIPE_USAGE_DEFAULT, 16);
 135                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 136
 137                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 138                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 139                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 140                                                               &sctx->null_const_buf);
 141                         }
 142                 }
 143
 144                 /* Clear the NULL constant buffer, because loads should return zeros. */
 145                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 146                                      sctx->null_const_buf.buffer->width0, 0);
 147         }
 148
 149         return &sctx->b.b;
 150 fail:
 151         si_destroy_context(&sctx->b.b);
 152         return NULL;
 153 }
 154
 155 /*
 156  * pipe_screen
 157  */
 158
 159 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 160 {
 161         struct si_screen *sscreen = (struct si_screen *)pscreen;
 162
 163         switch (param) {
 164         /* Supported features (boolean caps). */
 165         case PIPE_CAP_TWO_SIDED_STENCIL:
 166         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 167         case PIPE_CAP_ANISOTROPIC_FILTER:
 168         case PIPE_CAP_POINT_SPRITE:
 169         case PIPE_CAP_OCCLUSION_QUERY:
 170         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 171         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 172         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 173         case PIPE_CAP_TEXTURE_SWIZZLE:
 174         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 175         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 176         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 177         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 178         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 179         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 180         case PIPE_CAP_SM3:
 181         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 182         case PIPE_CAP_PRIMITIVE_RESTART:
 183         case PIPE_CAP_CONDITIONAL_RENDER:
 184         case PIPE_CAP_TEXTURE_BARRIER:
 185         case PIPE_CAP_INDEP_BLEND_ENABLE:
 186         case PIPE_CAP_INDEP_BLEND_FUNC:
 187         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 188         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 190         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 191         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 192         case PIPE_CAP_USER_INDEX_BUFFERS:
 193         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 194         case PIPE_CAP_START_INSTANCE:
 195         case PIPE_CAP_NPOT_TEXTURES:
 196         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 197         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 198         case PIPE_CAP_TGSI_INSTANCEID:
 199         case PIPE_CAP_COMPUTE:
 200         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 201         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 202         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 203         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 204         case PIPE_CAP_CUBE_MAP_ARRAY:
 205         case PIPE_CAP_SAMPLE_SHADING:
 206         case PIPE_CAP_DRAW_INDIRECT:
 207                 return 1;
 208
 209         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 210                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 211                 return sscreen->b.chip_class < CIK ||
 212                        sscreen->b.info.drm_minor >= 35;
 213
 214         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 215                 return R600_MAP_BUFFER_ALIGNMENT;
 216
 217         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 218         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 219                 return 4;
 220
 221         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 222                 return 330;
 223
 224         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 225                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 226
 227         case PIPE_CAP_TEXTURE_QUERY_LOD:
 228         case PIPE_CAP_TEXTURE_GATHER_SM5:
 229                 return HAVE_LLVM >= 0x0305;
 230         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 231                 return HAVE_LLVM >= 0x0305 ? 4 : 0;
 232
 233         /* Unsupported features. */
 234         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 235         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 236         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 237         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 238         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 239         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 240         case PIPE_CAP_USER_VERTEX_BUFFERS:
 241         case PIPE_CAP_TGSI_TEXCOORD:
 242         case PIPE_CAP_FAKE_SW_MSAA:
 243         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 244         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 245         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 246         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 247                 return 0;
 248
 249         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 250                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 251
 252         /* Stream output. */
 253         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 254                 return sscreen->b.has_streamout ? 4 : 0;
 255         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 256                 return sscreen->b.has_streamout ? 1 : 0;
 257         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 258         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 259                 return sscreen->b.has_streamout ? 32*4 : 0;
 260
 261         /* Geometry shader output. */
 262         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 263                 return 1024;
 264         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 265                 return 4095;
 266         case PIPE_CAP_MAX_VERTEX_STREAMS:
 267                 return 1;
 268
 269         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 270                 return 2048;
 271
 272         /* Texturing. */
 273         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 274         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 275                 return 15; /* 16384 */
 276         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 277                 /* textures support 8192, but layered rendering supports 2048 */
 278                 return 12;
 279         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 280                 /* textures support 8192, but layered rendering supports 2048 */
 281                 return 2048;
 282
 283         /* Render targets. */
 284         case PIPE_CAP_MAX_RENDER_TARGETS:
 285                 return 8;
 286
 287         case PIPE_CAP_MAX_VIEWPORTS:
 288                 return 1;
 289
 290         /* Timer queries, present when the clock frequency is non zero. */
 291         case PIPE_CAP_QUERY_TIMESTAMP:
 292         case PIPE_CAP_QUERY_TIME_ELAPSED:
 293                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 294
 295         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 296         case PIPE_CAP_MIN_TEXEL_OFFSET:
 297                 return -32;
 298
 299         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 300         case PIPE_CAP_MAX_TEXEL_OFFSET:
 301                 return 31;
 302
 303         case PIPE_CAP_ENDIANNESS:
 304                 return PIPE_ENDIAN_LITTLE;
 305
 306         case PIPE_CAP_VENDOR_ID:
 307                 return 0x1002;
 308         case PIPE_CAP_DEVICE_ID:
 309                 return sscreen->b.info.pci_id;
 310         case PIPE_CAP_ACCELERATED:
 311                 return 1;
 312         case PIPE_CAP_VIDEO_MEMORY:
 313                 return sscreen->b.info.vram_size >> 20;
 314         case PIPE_CAP_UMA:
 315                 return 0;
 316         }
 317         return 0;
 318 }
 319
 320 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 321 {
 322         switch(shader)
 323         {
 324         case PIPE_SHADER_FRAGMENT:
 325         case PIPE_SHADER_VERTEX:
 326         case PIPE_SHADER_GEOMETRY:
 327                 break;
 328         case PIPE_SHADER_COMPUTE:
 329                 switch (param) {
 330                 case PIPE_SHADER_CAP_PREFERRED_IR:
 331                         return PIPE_SHADER_IR_LLVM;
 332                 case PIPE_SHADER_CAP_DOUBLES:
 333                         return 0; /* XXX: Enable doubles once the compiler can
 334                                      handle them. */
 335                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 336                         uint64_t max_const_buffer_size;
 337                         pscreen->get_compute_param(pscreen,
 338                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 339                                 &max_const_buffer_size);
 340                         return max_const_buffer_size;
 341                 }
 342                 default:
 343                         return 0;
 344                 }
 345         default:
 346                 /* TODO: support tessellation */
 347                 return 0;
 348         }
 349
 350         switch (param) {
 351         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 352         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 353         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 354         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 355                 return 16384;
 356         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 357                 return 32;
 358         case PIPE_SHADER_CAP_MAX_INPUTS:
 359                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 360         case PIPE_SHADER_CAP_MAX_TEMPS:
 361                 return 256; /* Max native temporaries. */
 362         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 363                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 364         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 365                 return SI_NUM_USER_CONST_BUFFERS;
 366         case PIPE_SHADER_CAP_MAX_PREDS:
 367                 return 0; /* FIXME */
 368         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 369                 return 1;
 370         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 371                 return 0;
 372         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 373                 /* Indirection of geometry shader input dimension is not
 374                  * handled yet
 375                  */
 376                 return shader < PIPE_SHADER_GEOMETRY;
 377         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 378         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 379         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 380                 return 1;
 381         case PIPE_SHADER_CAP_INTEGERS:
 382                 return 1;
 383         case PIPE_SHADER_CAP_SUBROUTINES:
 384                 return 0;
 385         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 386         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 387                 return 16;
 388         case PIPE_SHADER_CAP_PREFERRED_IR:
 389                 return PIPE_SHADER_IR_TGSI;
 390         case PIPE_SHADER_CAP_DOUBLES:
 391                 return 0;
 392         }
 393         return 0;
 394 }
 395
 396 static void si_destroy_screen(struct pipe_screen* pscreen)
 397 {
 398         struct si_screen *sscreen = (struct si_screen *)pscreen;
 399
 400         if (sscreen == NULL)
 401                 return;
 402
 403         if (!sscreen->b.ws->unref(sscreen->b.ws))
 404                 return;
 405
 406         r600_destroy_common_screen(&sscreen->b);
 407 }
 408
 409 #define SI_TILE_MODE_COLOR_2D_8BPP  14
 410
 411 /* Initialize pipe config. This is especially important for GPUs
 412  * with 16 pipes and more where it's initialized incorrectly by
 413  * the TILING_CONFIG ioctl. */
 414 static bool si_initialize_pipe_config(struct si_screen *sscreen)
 415 {
 416         unsigned mode2d;
 417
 418         /* This is okay, because there can be no 2D tiling without
 419          * the tile mode array, so we won't need the pipe config.
 420          * Return "success".
 421          */
 422         if (!sscreen->b.info.si_tile_mode_array_valid)
 423                 return true;
 424
 425         /* The same index is used for the 2D mode on CIK too. */
 426         mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
 427
 428         switch (G_009910_PIPE_CONFIG(mode2d)) {
 429         case V_02803C_ADDR_SURF_P2:
 430                 sscreen->b.tiling_info.num_channels = 2;
 431                 break;
 432         case V_02803C_X_ADDR_SURF_P4_8X16:
 433         case V_02803C_X_ADDR_SURF_P4_16X16:
 434         case V_02803C_X_ADDR_SURF_P4_16X32:
 435         case V_02803C_X_ADDR_SURF_P4_32X32:
 436                 sscreen->b.tiling_info.num_channels = 4;
 437                 break;
 438         case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
 439         case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
 440         case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
 441         case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
 442         case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
 443         case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
 444         case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
 445                 sscreen->b.tiling_info.num_channels = 8;
 446                 break;
 447         case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
 448         case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
 449                 sscreen->b.tiling_info.num_channels = 16;
 450                 break;
 451         default:
 452                 assert(0);
 453                 fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
 454                         G_009910_PIPE_CONFIG(mode2d));
 455                 return false;
 456         }
 457         return true;
 458 }
 459
 460 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 461 {
 462         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 463         if (sscreen == NULL) {
 464                 return NULL;
 465         }
 466
 467         /* Set functions first. */
 468         sscreen->b.b.context_create = si_create_context;
 469         sscreen->b.b.destroy = si_destroy_screen;
 470         sscreen->b.b.get_param = si_get_param;
 471         sscreen->b.b.get_shader_param = si_get_shader_param;
 472         sscreen->b.b.is_format_supported = si_is_format_supported;
 473         sscreen->b.b.resource_create = r600_resource_create_common;
 474
 475         if (!r600_common_screen_init(&sscreen->b, ws) ||
 476             !si_initialize_pipe_config(sscreen)) {
 477                 FREE(sscreen);
 478                 return NULL;
 479         }
 480
 481         sscreen->b.has_cp_dma = true;
 482         sscreen->b.has_streamout = true;
 483
 484         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 485                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 486
 487         /* Create the auxiliary context. This must be done last. */
 488         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 489
 490         return &sscreen->b.b;
 491 }