2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
31 #include "radeon/radeon_uvd.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/u_log.h"
35 #include "util/u_memory.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_tests.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/xmlconfig.h"
40 #include "vl/vl_decoder.h"
41 #include "driver_ddebug/dd_util.h"
43 static const struct debug_named_value debug_options
[] = {
44 /* Shader logging options: */
45 { "vs", DBG(VS
), "Print vertex shaders" },
46 { "ps", DBG(PS
), "Print pixel shaders" },
47 { "gs", DBG(GS
), "Print geometry shaders" },
48 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
49 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
50 { "cs", DBG(CS
), "Print compute shaders" },
51 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
52 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
53 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
54 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
56 /* Shader compiler options the shader cache should be aware of: */
57 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
58 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
60 /* Shader compiler options (with no effect on the shader cache): */
61 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
62 { "nir", DBG(NIR
), "Enable experimental NIR shaders" },
63 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
64 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
66 /* Information logging options: */
67 { "info", DBG(INFO
), "Print driver information" },
68 { "tex", DBG(TEX
), "Print texture info" },
69 { "compute", DBG(COMPUTE
), "Print compute info" },
70 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
73 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
74 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
75 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
76 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
77 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
79 /* 3D engine options: */
80 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
81 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
82 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
83 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
84 { "dpbb", DBG(DPBB
), "Enable DPBB." },
85 { "dfsm", DBG(DFSM
), "Enable DFSM." },
86 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
87 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
88 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
89 { "notiling", DBG(NO_TILING
), "Disable tiling" },
90 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
91 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
92 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
93 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
94 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
97 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
98 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
99 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
100 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
102 DEBUG_NAMED_VALUE_END
/* must be last */
108 static void si_destroy_context(struct pipe_context
*context
)
110 struct si_context
*sctx
= (struct si_context
*)context
;
113 /* Unreference the framebuffer normally to disable related logic
116 struct pipe_framebuffer_state fb
= {};
117 if (context
->set_framebuffer_state
)
118 context
->set_framebuffer_state(context
, &fb
);
120 si_release_all_descriptors(sctx
);
122 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
123 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
124 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
125 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
126 r600_resource_reference(&sctx
->border_color_buffer
, NULL
);
127 free(sctx
->border_color_table
);
128 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
129 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
130 r600_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
132 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
133 if (sctx
->init_config_gs_rings
)
134 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
135 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
136 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
138 if (sctx
->fixed_func_tcs_shader
.cso
)
139 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
140 if (sctx
->custom_dsa_flush
)
141 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
142 if (sctx
->custom_blend_resolve
)
143 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
144 if (sctx
->custom_blend_fmask_decompress
)
145 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
146 if (sctx
->custom_blend_eliminate_fastclear
)
147 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
148 if (sctx
->custom_blend_dcc_decompress
)
149 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
150 if (sctx
->vs_blit_pos
)
151 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
152 if (sctx
->vs_blit_pos_layered
)
153 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
154 if (sctx
->vs_blit_color
)
155 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
156 if (sctx
->vs_blit_color_layered
)
157 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
158 if (sctx
->vs_blit_texcoord
)
159 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
162 util_blitter_destroy(sctx
->blitter
);
164 /* Release DCC stats. */
165 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
166 assert(!sctx
->dcc_stats
[i
].query_active
);
168 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
169 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
170 sctx
->b
.destroy_query(&sctx
->b
,
171 sctx
->dcc_stats
[i
].ps_stats
[j
]);
173 r600_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
176 if (sctx
->query_result_shader
)
177 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
180 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
182 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
184 sctx
->ws
->ctx_destroy(sctx
->ctx
);
186 if (sctx
->b
.stream_uploader
)
187 u_upload_destroy(sctx
->b
.stream_uploader
);
188 if (sctx
->b
.const_uploader
)
189 u_upload_destroy(sctx
->b
.const_uploader
);
190 if (sctx
->cached_gtt_allocator
)
191 u_upload_destroy(sctx
->cached_gtt_allocator
);
193 slab_destroy_child(&sctx
->pool_transfers
);
194 slab_destroy_child(&sctx
->pool_transfers_unsync
);
196 if (sctx
->allocator_zeroed_memory
)
197 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
199 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
200 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
201 r600_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
203 LLVMDisposeTargetMachine(sctx
->tm
);
205 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
207 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
208 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
210 util_dynarray_fini(&sctx
->resident_tex_handles
);
211 util_dynarray_fini(&sctx
->resident_img_handles
);
212 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
213 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
214 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
218 static enum pipe_reset_status
219 si_amdgpu_get_reset_status(struct pipe_context
*ctx
)
221 struct si_context
*sctx
= (struct si_context
*)ctx
;
223 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
226 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
228 struct si_context
*sctx
= (struct si_context
*)ctx
;
229 unsigned latest
= sctx
->ws
->query_value(sctx
->ws
,
230 RADEON_GPU_RESET_COUNTER
);
232 if (sctx
->gpu_reset_counter
== latest
)
233 return PIPE_NO_RESET
;
235 sctx
->gpu_reset_counter
= latest
;
236 return PIPE_UNKNOWN_CONTEXT_RESET
;
239 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
240 const struct pipe_device_reset_callback
*cb
)
242 struct si_context
*sctx
= (struct si_context
*)ctx
;
245 sctx
->device_reset_callback
= *cb
;
247 memset(&sctx
->device_reset_callback
, 0,
248 sizeof(sctx
->device_reset_callback
));
251 bool si_check_device_reset(struct si_context
*sctx
)
253 enum pipe_reset_status status
;
255 if (!sctx
->device_reset_callback
.reset
)
258 if (!sctx
->b
.get_device_reset_status
)
261 status
= sctx
->b
.get_device_reset_status(&sctx
->b
);
262 if (status
== PIPE_NO_RESET
)
265 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
269 /* Apitrace profiling:
270 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
271 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
272 * and remember its number.
273 * 3) In Mesa, enable queries and performance counters around that draw
274 * call and print the results.
275 * 4) glretrace --benchmark --markers ..
277 static void si_emit_string_marker(struct pipe_context
*ctx
,
278 const char *string
, int len
)
280 struct si_context
*sctx
= (struct si_context
*)ctx
;
282 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
285 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
288 static LLVMTargetMachineRef
289 si_create_llvm_target_machine(struct si_screen
*sscreen
)
291 enum ac_target_machine_options tm_options
=
292 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
293 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
294 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
295 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0);
297 return ac_create_target_machine(sscreen
->info
.family
, tm_options
);
300 static void si_set_debug_callback(struct pipe_context
*ctx
,
301 const struct pipe_debug_callback
*cb
)
303 struct si_context
*sctx
= (struct si_context
*)ctx
;
304 struct si_screen
*screen
= sctx
->screen
;
306 util_queue_finish(&screen
->shader_compiler_queue
);
307 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
312 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
315 static void si_set_log_context(struct pipe_context
*ctx
,
316 struct u_log_context
*log
)
318 struct si_context
*sctx
= (struct si_context
*)ctx
;
322 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
325 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
328 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
329 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
330 struct radeon_winsys
*ws
= sscreen
->ws
;
336 if (flags
& PIPE_CONTEXT_DEBUG
)
337 sscreen
->record_llvm_ir
= true; /* racy but not critical */
339 sctx
->b
.screen
= screen
; /* this must be set first */
341 sctx
->b
.destroy
= si_destroy_context
;
342 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
343 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
344 sctx
->b
.set_log_context
= si_set_log_context
;
345 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
346 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
348 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
349 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
351 sctx
->ws
= sscreen
->ws
;
352 sctx
->family
= sscreen
->info
.family
;
353 sctx
->chip_class
= sscreen
->info
.chip_class
;
355 if (sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
>= 43) {
356 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
357 sctx
->gpu_reset_counter
=
358 sctx
->ws
->query_value(sctx
->ws
,
359 RADEON_GPU_RESET_COUNTER
);
362 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
364 si_init_context_texture_functions(sctx
);
365 si_init_query_functions(sctx
);
367 if (sctx
->chip_class
== CIK
||
368 sctx
->chip_class
== VI
||
369 sctx
->chip_class
== GFX9
) {
370 sctx
->eop_bug_scratch
= r600_resource(
371 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
372 16 * sscreen
->info
.num_render_backends
));
373 if (!sctx
->eop_bug_scratch
)
377 sctx
->allocator_zeroed_memory
=
378 u_suballocator_create(&sctx
->b
, sscreen
->info
.gart_page_size
,
379 0, PIPE_USAGE_DEFAULT
, 0, true);
380 if (!sctx
->allocator_zeroed_memory
)
383 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
384 0, PIPE_USAGE_STREAM
,
385 SI_RESOURCE_FLAG_READ_ONLY
);
386 if (!sctx
->b
.stream_uploader
)
389 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 128 * 1024,
390 0, PIPE_USAGE_DEFAULT
,
391 SI_RESOURCE_FLAG_32BIT
|
392 (sscreen
->cpdma_prefetch_writes_memory
?
393 0 : SI_RESOURCE_FLAG_READ_ONLY
));
394 if (!sctx
->b
.const_uploader
)
397 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
398 0, PIPE_USAGE_STAGING
, 0);
399 if (!sctx
->cached_gtt_allocator
)
402 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
406 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
407 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
408 (void*)si_flush_dma_cs
,
412 if (sscreen
->info
.drm_major
== 3)
413 sctx
->b
.get_device_reset_status
= si_amdgpu_get_reset_status
;
415 si_init_buffer_functions(sctx
);
416 si_init_clear_functions(sctx
);
417 si_init_blit_functions(sctx
);
418 si_init_compute_functions(sctx
);
419 si_init_cp_dma_functions(sctx
);
420 si_init_debug_functions(sctx
);
421 si_init_msaa_functions(sctx
);
422 si_init_streamout_functions(sctx
);
424 if (sscreen
->info
.has_hw_decode
) {
425 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
426 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
428 sctx
->b
.create_video_codec
= vl_create_decoder
;
429 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
432 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, RING_GFX
,
433 (void*)si_flush_gfx_cs
, sctx
);
436 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
437 sizeof(*sctx
->border_color_table
));
438 if (!sctx
->border_color_table
)
441 sctx
->border_color_buffer
= r600_resource(
442 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
443 SI_MAX_BORDER_COLORS
*
444 sizeof(*sctx
->border_color_table
)));
445 if (!sctx
->border_color_buffer
)
448 sctx
->border_color_map
=
449 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
450 NULL
, PIPE_TRANSFER_WRITE
);
451 if (!sctx
->border_color_map
)
454 si_init_all_descriptors(sctx
);
455 si_init_fence_functions(sctx
);
456 si_init_state_functions(sctx
);
457 si_init_shader_functions(sctx
);
458 si_init_viewport_functions(sctx
);
459 si_init_ia_multi_vgt_param_table(sctx
);
461 if (sctx
->chip_class
>= CIK
)
462 cik_init_sdma_functions(sctx
);
464 si_init_dma_functions(sctx
);
466 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
467 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
469 sctx
->blitter
= util_blitter_create(&sctx
->b
);
470 if (sctx
->blitter
== NULL
)
472 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
473 sctx
->blitter
->skip_viewport_restore
= true;
475 sctx
->sample_mask
= 0xffff;
477 if (sctx
->chip_class
>= GFX9
) {
478 sctx
->wait_mem_scratch
= r600_resource(
479 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 4));
480 if (!sctx
->wait_mem_scratch
)
483 /* Initialize the memory. */
484 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
485 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
486 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
487 S_370_WR_CONFIRM(1) |
488 S_370_ENGINE_SEL(V_370_ME
));
489 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
);
490 radeon_emit(cs
, sctx
->wait_mem_scratch
->gpu_address
>> 32);
491 radeon_emit(cs
, sctx
->wait_mem_number
);
492 radeon_add_to_buffer_list(sctx
, cs
, sctx
->wait_mem_scratch
,
493 RADEON_USAGE_WRITE
, RADEON_PRIO_FENCE
);
496 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
497 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
498 if (sctx
->chip_class
== CIK
) {
499 sctx
->null_const_buf
.buffer
=
500 pipe_aligned_buffer_create(screen
,
501 SI_RESOURCE_FLAG_32BIT
,
502 PIPE_USAGE_DEFAULT
, 16,
503 sctx
->screen
->info
.tcc_cache_line_size
);
504 if (!sctx
->null_const_buf
.buffer
)
506 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
508 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
509 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
510 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
511 &sctx
->null_const_buf
);
515 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
516 &sctx
->null_const_buf
);
517 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
518 &sctx
->null_const_buf
);
519 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
520 &sctx
->null_const_buf
);
521 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
522 &sctx
->null_const_buf
);
523 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
524 &sctx
->null_const_buf
);
526 /* Clear the NULL constant buffer, because loads should return zeros. */
527 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
528 sctx
->null_const_buf
.buffer
->width0
, 0,
529 SI_COHERENCY_SHADER
);
532 uint64_t max_threads_per_block
;
533 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
534 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
535 &max_threads_per_block
);
537 /* The maximum number of scratch waves. Scratch space isn't divided
538 * evenly between CUs. The number is only a function of the number of CUs.
539 * We can decrease the constant to decrease the scratch buffer size.
541 * sctx->scratch_waves must be >= the maximum posible size of
542 * 1 threadgroup, so that the hw doesn't hang from being unable
545 * The recommended value is 4 per CU at most. Higher numbers don't
546 * bring much benefit, but they still occupy chip resources (think
547 * async compute). I've seen ~2% performance difference between 4 and 32.
549 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
550 max_threads_per_block
/ 64);
552 sctx
->tm
= si_create_llvm_target_machine(sscreen
);
554 /* Bindless handles. */
555 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
556 _mesa_key_pointer_equal
);
557 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
558 _mesa_key_pointer_equal
);
560 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
561 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
562 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
563 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
564 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
566 /* this must be last */
567 si_begin_new_gfx_cs(sctx
);
570 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
571 si_destroy_context(&sctx
->b
);
575 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
576 void *priv
, unsigned flags
)
578 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
579 struct pipe_context
*ctx
;
581 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
582 flags
|= PIPE_CONTEXT_DEBUG
;
584 ctx
= si_create_context(screen
, flags
);
586 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
589 /* Clover (compute-only) is unsupported. */
590 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
593 /* When shaders are logged to stderr, asynchronous compilation is
595 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
598 /* Use asynchronous flushes only on amdgpu, since the radeon
599 * implementation for fence_server_sync is incomplete. */
600 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
601 si_replace_buffer_storage
,
602 sscreen
->info
.drm_major
>= 3 ? si_create_fence
: NULL
,
603 &((struct si_context
*)ctx
)->tc
);
609 static void si_destroy_screen(struct pipe_screen
* pscreen
)
611 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
612 struct si_shader_part
*parts
[] = {
614 sscreen
->tcs_epilogs
,
621 if (!sscreen
->ws
->unref(sscreen
->ws
))
624 util_queue_destroy(&sscreen
->shader_compiler_queue
);
625 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
627 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm
); i
++)
629 LLVMDisposeTargetMachine(sscreen
->tm
[i
]);
631 for (i
= 0; i
< ARRAY_SIZE(sscreen
->tm_low_priority
); i
++)
632 if (sscreen
->tm_low_priority
[i
])
633 LLVMDisposeTargetMachine(sscreen
->tm_low_priority
[i
]);
635 /* Free shader parts. */
636 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
638 struct si_shader_part
*part
= parts
[i
];
640 parts
[i
] = part
->next
;
641 ac_shader_binary_clean(&part
->binary
);
645 mtx_destroy(&sscreen
->shader_parts_mutex
);
646 si_destroy_shader_cache(sscreen
);
648 si_perfcounters_destroy(sscreen
);
649 si_gpu_load_kill_thread(sscreen
);
651 mtx_destroy(&sscreen
->gpu_load_mutex
);
652 mtx_destroy(&sscreen
->aux_context_lock
);
653 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
655 slab_destroy_parent(&sscreen
->pool_transfers
);
657 disk_cache_destroy(sscreen
->disk_shader_cache
);
658 sscreen
->ws
->destroy(sscreen
->ws
);
662 static void si_init_gs_info(struct si_screen
*sscreen
)
664 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
665 sscreen
->info
.family
);
668 static void si_handle_env_var_force_family(struct si_screen
*sscreen
)
670 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
676 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
677 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
678 /* Override family and chip_class. */
679 sscreen
->info
.family
= i
;
681 if (i
>= CHIP_VEGA10
)
682 sscreen
->info
.chip_class
= GFX9
;
683 else if (i
>= CHIP_TONGA
)
684 sscreen
->info
.chip_class
= VI
;
685 else if (i
>= CHIP_BONAIRE
)
686 sscreen
->info
.chip_class
= CIK
;
688 sscreen
->info
.chip_class
= SI
;
690 /* Don't submit any IBs. */
691 setenv("RADEON_NOOP", "1", 1);
696 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
700 static void si_test_vmfault(struct si_screen
*sscreen
)
702 struct pipe_context
*ctx
= sscreen
->aux_context
;
703 struct si_context
*sctx
= (struct si_context
*)ctx
;
704 struct pipe_resource
*buf
=
705 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
708 puts("Buffer allocation failed.");
712 r600_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
714 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
715 si_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0);
716 ctx
->flush(ctx
, NULL
, 0);
717 puts("VM fault test: CP - done.");
719 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
720 sctx
->dma_clear_buffer(sctx
, buf
, 0, 4, 0);
721 ctx
->flush(ctx
, NULL
, 0);
722 puts("VM fault test: SDMA - done.");
724 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
725 util_test_constant_buffer(ctx
, buf
);
726 puts("VM fault test: Shader - done.");
731 static void si_disk_cache_create(struct si_screen
*sscreen
)
733 /* Don't use the cache if shader dumping is enabled. */
734 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
737 uint32_t mesa_timestamp
;
738 if (disk_cache_get_function_timestamp(si_disk_cache_create
,
742 uint32_t llvm_timestamp
;
744 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
,
746 res
= asprintf(×tamp_str
, "%u_%u",
747 mesa_timestamp
, llvm_timestamp
);
751 /* These flags affect shader compilation. */
752 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
756 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
759 /* Add the high bits of 32-bit addresses, which affects
760 * how 32-bit addresses are expanded to 64 bits.
762 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
763 shader_debug_flags
|= (uint64_t)sscreen
->info
.address32_hi
<< 32;
765 sscreen
->disk_shader_cache
=
766 disk_cache_create(si_get_family_name(sscreen
),
774 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
,
775 const struct pipe_screen_config
*config
)
777 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
778 unsigned num_threads
, num_compiler_threads
, num_compiler_threads_lowprio
, i
;
785 ws
->query_info(ws
, &sscreen
->info
);
787 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
790 /* Set functions first. */
791 sscreen
->b
.context_create
= si_pipe_create_context
;
792 sscreen
->b
.destroy
= si_destroy_screen
;
794 si_init_screen_get_functions(sscreen
);
795 si_init_screen_buffer_functions(sscreen
);
796 si_init_screen_fence_functions(sscreen
);
797 si_init_screen_state_functions(sscreen
);
798 si_init_screen_texture_functions(sscreen
);
799 si_init_screen_query_functions(sscreen
);
801 /* Set these flags in debug_flags early, so that the shader cache takes
804 if (driQueryOptionb(config
->options
,
805 "glsl_correct_derivatives_after_discard"))
806 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
807 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
808 sscreen
->debug_flags
|= DBG(SI_SCHED
);
811 if (sscreen
->debug_flags
& DBG(INFO
))
812 ac_print_gpu_info(&sscreen
->info
);
814 slab_create_parent(&sscreen
->pool_transfers
,
815 sizeof(struct r600_transfer
), 64);
817 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
818 if (sscreen
->force_aniso
>= 0) {
819 printf("radeonsi: Forcing anisotropy filter to %ix\n",
820 /* round down to a power of two */
821 1 << util_logbase2(sscreen
->force_aniso
));
824 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
825 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
827 si_init_gs_info(sscreen
);
828 if (!si_init_shader_cache(sscreen
)) {
833 si_disk_cache_create(sscreen
);
835 /* Only enable as many threads as we have target machines, but at most
836 * the number of CPUs - 1 if there is more than one.
838 num_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
839 num_threads
= MAX2(1, num_threads
- 1);
840 num_compiler_threads
= MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm
));
841 num_compiler_threads_lowprio
=
842 MIN2(num_threads
, ARRAY_SIZE(sscreen
->tm_low_priority
));
844 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "si_shader",
845 32, num_compiler_threads
,
846 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
847 si_destroy_shader_cache(sscreen
);
852 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
854 32, num_compiler_threads_lowprio
,
855 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
856 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
857 si_destroy_shader_cache(sscreen
);
862 si_handle_env_var_force_family(sscreen
);
864 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
865 si_init_perfcounters(sscreen
);
867 /* Determine tessellation ring info. */
868 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= CIK
&&
869 sscreen
->info
.family
!= CHIP_CARRIZO
&&
870 sscreen
->info
.family
!= CHIP_STONEY
;
871 /* This must be one less than the maximum number due to a hw limitation.
872 * Various hardware bugs in SI, CIK, and GFX9 need this.
874 unsigned max_offchip_buffers_per_se
;
876 /* Only certain chips can use the maximum value. */
877 if (sscreen
->info
.family
== CHIP_VEGA12
)
878 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
880 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
882 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
883 sscreen
->info
.max_se
;
884 unsigned offchip_granularity
;
886 /* Hawaii has a bug with offchip buffers > 256 that can be worked
887 * around by setting 4K granularity.
889 if (sscreen
->info
.family
== CHIP_HAWAII
) {
890 sscreen
->tess_offchip_block_dw_size
= 4096;
891 offchip_granularity
= V_03093C_X_4K_DWORDS
;
893 sscreen
->tess_offchip_block_dw_size
= 8192;
894 offchip_granularity
= V_03093C_X_8K_DWORDS
;
897 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
898 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
899 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
900 sscreen
->tess_offchip_block_dw_size
* 4;
902 if (sscreen
->info
.chip_class
>= CIK
) {
903 if (sscreen
->info
.chip_class
>= VI
)
904 --max_offchip_buffers
;
905 sscreen
->vgt_hs_offchip_param
=
906 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
907 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
909 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
910 sscreen
->vgt_hs_offchip_param
=
911 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
914 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
916 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= CIK
;
918 sscreen
->has_distributed_tess
=
919 sscreen
->info
.chip_class
>= VI
&&
920 sscreen
->info
.max_se
>= 2;
922 sscreen
->has_draw_indirect_multi
=
923 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
924 (sscreen
->info
.chip_class
== VI
&&
925 sscreen
->info
.pfp_fw_version
>= 121 &&
926 sscreen
->info
.me_fw_version
>= 87) ||
927 (sscreen
->info
.chip_class
== CIK
&&
928 sscreen
->info
.pfp_fw_version
>= 211 &&
929 sscreen
->info
.me_fw_version
>= 173) ||
930 (sscreen
->info
.chip_class
== SI
&&
931 sscreen
->info
.pfp_fw_version
>= 79 &&
932 sscreen
->info
.me_fw_version
>= 142);
934 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= VI
&&
935 sscreen
->info
.max_se
>= 2 &&
936 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
937 sscreen
->assume_no_z_fights
=
938 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
939 sscreen
->commutative_blend_add
=
940 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
941 sscreen
->clear_db_cache_before_clear
=
942 driQueryOptionb(config
->options
, "radeonsi_clear_db_cache_before_clear");
943 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
944 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
945 sscreen
->info
.family
== CHIP_VEGA10
||
946 sscreen
->info
.family
== CHIP_RAVEN
;
947 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
948 sscreen
->info
.family
== CHIP_RAVEN
;
950 if (sscreen
->debug_flags
& DBG(DPBB
)) {
951 sscreen
->dpbb_allowed
= true;
953 /* Only enable primitive binning on Raven by default. */
954 /* TODO: Investigate if binning is profitable on Vega12. */
955 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
&&
956 !(sscreen
->debug_flags
& DBG(NO_DPBB
));
959 if (sscreen
->debug_flags
& DBG(DFSM
)) {
960 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
;
962 sscreen
->dfsm_allowed
= sscreen
->dpbb_allowed
&&
963 !(sscreen
->debug_flags
& DBG(NO_DFSM
));
966 /* While it would be nice not to have this flag, we are constrained
967 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
970 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= VI
;
972 /* Some chips have RB+ registers, but don't support RB+. Those must
975 if (sscreen
->info
.family
== CHIP_STONEY
||
976 sscreen
->info
.chip_class
>= GFX9
) {
977 sscreen
->has_rbplus
= true;
979 sscreen
->rbplus_allowed
=
980 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
981 (sscreen
->info
.family
== CHIP_STONEY
||
982 sscreen
->info
.family
== CHIP_VEGA12
||
983 sscreen
->info
.family
== CHIP_RAVEN
);
986 sscreen
->dcc_msaa_allowed
=
987 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
989 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= VI
;
991 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
992 sscreen
->use_monolithic_shaders
=
993 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
995 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SMEM_L1
|
996 SI_CONTEXT_INV_VMEM_L1
;
997 if (sscreen
->info
.chip_class
<= VI
) {
998 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_GLOBAL_L2
;
999 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1002 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1003 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1005 for (i
= 0; i
< num_compiler_threads
; i
++)
1006 sscreen
->tm
[i
] = si_create_llvm_target_machine(sscreen
);
1007 for (i
= 0; i
< num_compiler_threads_lowprio
; i
++)
1008 sscreen
->tm_low_priority
[i
] = si_create_llvm_target_machine(sscreen
);
1010 /* Create the auxiliary context. This must be done last. */
1011 sscreen
->aux_context
= si_create_context(&sscreen
->b
, 0);
1013 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1014 si_test_dma(sscreen
);
1016 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1017 DBG(TEST_VMFAULT_SDMA
) |
1018 DBG(TEST_VMFAULT_SHADER
)))
1019 si_test_vmfault(sscreen
);