projects / mesa.git / blob
? search:


dd962e08e7ad9f777114f5532fe3374e39981883
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/u_memory.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_tests.h"
33 #include "vl/vl_decoder.h"
34 #include "../ddebug/dd_util.h"
35
36 #define SI_LLVM_DEFAULT_FEATURES \
37 "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
38
39 /*
40 * pipe_context
41 */
42 static void si_destroy_context(struct pipe_context *context)
43 {
44 struct si_context *sctx = (struct si_context *)context;
45 int i;
46
47 /* Unreference the framebuffer normally to disable related logic
48 * properly.
49 */
50 struct pipe_framebuffer_state fb = {};
51 context->set_framebuffer_state(context, &fb);
52
53 si_release_all_descriptors(sctx);
54
55 if (sctx->ce_suballocator)
56 u_suballocator_destroy(sctx->ce_suballocator);
57
58 pipe_resource_reference(&sctx->esgs_ring, NULL);
59 pipe_resource_reference(&sctx->gsvs_ring, NULL);
60 pipe_resource_reference(&sctx->tf_ring, NULL);
61 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
62 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
63 r600_resource_reference(&sctx->border_color_buffer, NULL);
64 free(sctx->border_color_table);
65 r600_resource_reference(&sctx->scratch_buffer, NULL);
66 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
67
68 si_pm4_free_state(sctx, sctx->init_config, ~0);
69 if (sctx->init_config_gs_rings)
70 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
71 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
72 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
73
74 if (sctx->fixed_func_tcs_shader.cso)
75 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
76 if (sctx->custom_dsa_flush)
77 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
78 if (sctx->custom_blend_resolve)
79 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
80 if (sctx->custom_blend_decompress)
81 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
82 if (sctx->custom_blend_fastclear)
83 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
84 if (sctx->custom_blend_dcc_decompress)
85 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
86
87 if (sctx->blitter)
88 util_blitter_destroy(sctx->blitter);
89
90 r600_common_context_cleanup(&sctx->b);
91
92 LLVMDisposeTargetMachine(sctx->tm);
93
94 r600_resource_reference(&sctx->trace_buf, NULL);
95 r600_resource_reference(&sctx->last_trace_buf, NULL);
96 radeon_clear_saved_cs(&sctx->last_gfx);
97
98 FREE(sctx);
99 }
100
101 static enum pipe_reset_status
102 si_amdgpu_get_reset_status(struct pipe_context *ctx)
103 {
104 struct si_context *sctx = (struct si_context *)ctx;
105
106 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
107 }
108
109 /* Apitrace profiling:
110 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
111 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
112 * and remember its number.
113 * 3) In Mesa, enable queries and performance counters around that draw
114 * call and print the results.
115 * 4) glretrace --benchmark --markers ..
116 */
117 static void si_emit_string_marker(struct pipe_context *ctx,
118 const char *string, int len)
119 {
120 struct si_context *sctx = (struct si_context *)ctx;
121
122 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
123 }
124
125 static LLVMTargetMachineRef
126 si_create_llvm_target_machine(struct si_screen *sscreen)
127 {
128 const char *triple = "amdgcn--";
129
130 return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), triple,
131 r600_get_llvm_processor_name(sscreen->b.family),
132 sscreen->b.debug_flags & DBG_SI_SCHED ?
133 SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
134 SI_LLVM_DEFAULT_FEATURES,
135 LLVMCodeGenLevelDefault,
136 LLVMRelocDefault,
137 LLVMCodeModelDefault);
138 }
139
140 static struct pipe_context *si_create_context(struct pipe_screen *screen,
141 unsigned flags)
142 {
143 struct si_context *sctx = CALLOC_STRUCT(si_context);
144 struct si_screen* sscreen = (struct si_screen *)screen;
145 struct radeon_winsys *ws = sscreen->b.ws;
146 int shader, i;
147
148 if (!sctx)
149 return NULL;
150
151 if (sscreen->b.debug_flags & DBG_CHECK_VM)
152 flags |= PIPE_CONTEXT_DEBUG;
153
154 if (flags & PIPE_CONTEXT_DEBUG)
155 sscreen->record_llvm_ir = true; /* racy but not critical */
156
157 sctx->b.b.screen = screen; /* this must be set first */
158 sctx->b.b.priv = NULL;
159 sctx->b.b.destroy = si_destroy_context;
160 sctx->b.b.emit_string_marker = si_emit_string_marker;
161 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
162 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
163 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
164
165 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
166 goto fail;
167
168 if (sscreen->b.info.drm_major == 3)
169 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
170
171 si_init_blit_functions(sctx);
172 si_init_compute_functions(sctx);
173 si_init_cp_dma_functions(sctx);
174 si_init_debug_functions(sctx);
175
176 if (sscreen->b.info.has_uvd) {
177 sctx->b.b.create_video_codec = si_uvd_create_decoder;
178 sctx->b.b.create_video_buffer = si_video_buffer_create;
179 } else {
180 sctx->b.b.create_video_codec = vl_create_decoder;
181 sctx->b.b.create_video_buffer = vl_video_buffer_create;
182 }
183
184 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
185 si_context_gfx_flush, sctx);
186
187 /* SI + AMDGPU + CE = GPU hang */
188 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
189 sscreen->b.chip_class != SI &&
190 /* These can't use CE due to a power gating bug in the kernel. */
191 sscreen->b.family != CHIP_CARRIZO &&
192 sscreen->b.family != CHIP_STONEY &&
193 /* Some CE bug is causing green screen corruption w/ MPV video
194 * playback and occasional corruption w/ 3D. */
195 sscreen->b.chip_class != GFX9) {
196 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
197 if (!sctx->ce_ib)
198 goto fail;
199
200 if (ws->cs_add_const_preamble_ib) {
201 sctx->ce_preamble_ib =
202 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
203
204 if (!sctx->ce_preamble_ib)
205 goto fail;
206 }
207
208 sctx->ce_suballocator =
209 u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
210 PIPE_USAGE_DEFAULT,
211 R600_RESOURCE_FLAG_UNMAPPABLE, false);
212 if (!sctx->ce_suballocator)
213 goto fail;
214 }
215
216 sctx->b.gfx.flush = si_context_gfx_flush;
217
218 /* Border colors. */
219 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
220 sizeof(*sctx->border_color_table));
221 if (!sctx->border_color_table)
222 goto fail;
223
224 sctx->border_color_buffer = (struct r600_resource*)
225 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
226 SI_MAX_BORDER_COLORS *
227 sizeof(*sctx->border_color_table));
228 if (!sctx->border_color_buffer)
229 goto fail;
230
231 sctx->border_color_map =
232 ws->buffer_map(sctx->border_color_buffer->buf,
233 NULL, PIPE_TRANSFER_WRITE);
234 if (!sctx->border_color_map)
235 goto fail;
236
237 si_init_all_descriptors(sctx);
238 si_init_state_functions(sctx);
239 si_init_shader_functions(sctx);
240 si_init_ia_multi_vgt_param_table(sctx);
241
242 if (sctx->b.chip_class >= CIK)
243 cik_init_sdma_functions(sctx);
244 else
245 si_init_dma_functions(sctx);
246
247 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
248 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
249
250 sctx->blitter = util_blitter_create(&sctx->b.b);
251 if (sctx->blitter == NULL)
252 goto fail;
253 sctx->blitter->draw_rectangle = r600_draw_rectangle;
254
255 sctx->sample_mask.sample_mask = 0xffff;
256
257 /* these must be last */
258 si_begin_new_cs(sctx);
259
260 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
261 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
262 if (sctx->b.chip_class == CIK) {
263 sctx->null_const_buf.buffer =
264 r600_aligned_buffer_create(screen,
265 R600_RESOURCE_FLAG_UNMAPPABLE,
266 PIPE_USAGE_DEFAULT, 16,
267 sctx->screen->b.info.tcc_cache_line_size);
268 if (!sctx->null_const_buf.buffer)
269 goto fail;
270 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
271
272 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
273 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
274 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
275 &sctx->null_const_buf);
276 }
277 }
278
279 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
280 &sctx->null_const_buf);
281 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
282 &sctx->null_const_buf);
283 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
284 &sctx->null_const_buf);
285 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
286 &sctx->null_const_buf);
287
288 /* Clear the NULL constant buffer, because loads should return zeros. */
289 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
290 sctx->null_const_buf.buffer->width0, 0,
291 R600_COHERENCY_SHADER);
292 }
293
294 uint64_t max_threads_per_block;
295 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
296 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
297 &max_threads_per_block);
298
299 /* The maximum number of scratch waves. Scratch space isn't divided
300 * evenly between CUs. The number is only a function of the number of CUs.
301 * We can decrease the constant to decrease the scratch buffer size.
302 *
303 * sctx->scratch_waves must be >= the maximum posible size of
304 * 1 threadgroup, so that the hw doesn't hang from being unable
305 * to start any.
306 *
307 * The recommended value is 4 per CU at most. Higher numbers don't
308 * bring much benefit, but they still occupy chip resources (think
309 * async compute). I've seen ~2% performance difference between 4 and 32.
310 */
311 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
312 max_threads_per_block / 64);
313
314 sctx->tm = si_create_llvm_target_machine(sscreen);
315
316 return &sctx->b.b;
317 fail:
318 fprintf(stderr, "radeonsi: Failed to create a context.\n");
319 si_destroy_context(&sctx->b.b);
320 return NULL;
321 }
322
323 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
324 void *priv, unsigned flags)
325 {
326 struct si_screen *sscreen = (struct si_screen *)screen;
327 struct pipe_context *ctx = si_create_context(screen, flags);
328
329 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
330 return ctx;
331
332 /* Clover (compute-only) is unsupported.
333 *
334 * Since the threaded context creates shader states from the non-driver
335 * thread, asynchronous compilation is required for create_{shader}_-
336 * state not to use pipe_context. Debug contexts (ddebug) disable
337 * asynchronous compilation, so don't use the threaded context with
338 * those.
339 */
340 if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
341 return ctx;
342
343 /* When shaders are logged to stderr, asynchronous compilation is
344 * disabled too. */
345 if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
346 DBG_PS | DBG_CS))
347 return ctx;
348
349 return threaded_context_create(ctx, &sscreen->b.pool_transfers,
350 r600_replace_buffer_storage,
351 &((struct si_context*)ctx)->b.tc);
352 }
353
354 /*
355 * pipe_screen
356 */
357 static bool si_have_tgsi_compute(struct si_screen *sscreen)
358 {
359 /* Old kernels disallowed some register writes for SI
360 * that are used for indirect dispatches. */
361 return (sscreen->b.chip_class >= CIK ||
362 sscreen->b.info.drm_major == 3 ||
363 (sscreen->b.info.drm_major == 2 &&
364 sscreen->b.info.drm_minor >= 45));
365 }
366
367 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
368 {
369 struct si_screen *sscreen = (struct si_screen *)pscreen;
370
371 switch (param) {
372 /* Supported features (boolean caps). */
373 case PIPE_CAP_ACCELERATED:
374 case PIPE_CAP_TWO_SIDED_STENCIL:
375 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
376 case PIPE_CAP_ANISOTROPIC_FILTER:
377 case PIPE_CAP_POINT_SPRITE:
378 case PIPE_CAP_OCCLUSION_QUERY:
379 case PIPE_CAP_TEXTURE_SHADOW_MAP:
380 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
381 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
382 case PIPE_CAP_TEXTURE_SWIZZLE:
383 case PIPE_CAP_DEPTH_CLIP_DISABLE:
384 case PIPE_CAP_SHADER_STENCIL_EXPORT:
385 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
386 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
387 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
388 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
389 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
390 case PIPE_CAP_SM3:
391 case PIPE_CAP_SEAMLESS_CUBE_MAP:
392 case PIPE_CAP_PRIMITIVE_RESTART:
393 case PIPE_CAP_CONDITIONAL_RENDER:
394 case PIPE_CAP_TEXTURE_BARRIER:
395 case PIPE_CAP_INDEP_BLEND_ENABLE:
396 case PIPE_CAP_INDEP_BLEND_FUNC:
397 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
398 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
399 case PIPE_CAP_USER_CONSTANT_BUFFERS:
400 case PIPE_CAP_START_INSTANCE:
401 case PIPE_CAP_NPOT_TEXTURES:
402 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
403 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
404 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
405 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
406 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
407 case PIPE_CAP_TGSI_INSTANCEID:
408 case PIPE_CAP_COMPUTE:
409 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
410 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
411 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
412 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
413 case PIPE_CAP_CUBE_MAP_ARRAY:
414 case PIPE_CAP_SAMPLE_SHADING:
415 case PIPE_CAP_DRAW_INDIRECT:
416 case PIPE_CAP_CLIP_HALFZ:
417 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
418 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
419 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
420 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
421 case PIPE_CAP_TGSI_TEXCOORD:
422 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
423 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
424 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
425 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
426 case PIPE_CAP_SHAREABLE_SHADERS:
427 case PIPE_CAP_DEPTH_BOUNDS_TEST:
428 case PIPE_CAP_SAMPLER_VIEW_TARGET:
429 case PIPE_CAP_TEXTURE_QUERY_LOD:
430 case PIPE_CAP_TEXTURE_GATHER_SM5:
431 case PIPE_CAP_TGSI_TXQS:
432 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
433 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
434 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
435 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
436 case PIPE_CAP_INVALIDATE_BUFFER:
437 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
438 case PIPE_CAP_QUERY_MEMORY_INFO:
439 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
440 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
441 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
442 case PIPE_CAP_GENERATE_MIPMAP:
443 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
444 case PIPE_CAP_STRING_MARKER:
445 case PIPE_CAP_CLEAR_TEXTURE:
446 case PIPE_CAP_CULL_DISTANCE:
447 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
448 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
449 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
450 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
451 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
452 case PIPE_CAP_DOUBLES:
453 case PIPE_CAP_TGSI_TEX_TXF_LZ:
454 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
455 case PIPE_CAP_INT64:
456 case PIPE_CAP_INT64_DIVMOD:
457 case PIPE_CAP_TGSI_CLOCK:
458 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
459 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
460 return 1;
461
462 case PIPE_CAP_TGSI_VOTE:
463 return HAVE_LLVM >= 0x0400;
464
465 case PIPE_CAP_TGSI_BALLOT:
466 return HAVE_LLVM >= 0x0500;
467
468 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
469 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
470
471 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
472 return (sscreen->b.info.drm_major == 2 &&
473 sscreen->b.info.drm_minor >= 43) ||
474 sscreen->b.info.drm_major == 3;
475
476 case PIPE_CAP_TEXTURE_MULTISAMPLE:
477 /* 2D tiling on CIK is supported since DRM 2.35.0 */
478 return sscreen->b.chip_class < CIK ||
479 (sscreen->b.info.drm_major == 2 &&
480 sscreen->b.info.drm_minor >= 35) ||
481 sscreen->b.info.drm_major == 3;
482
483 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
484 return R600_MAP_BUFFER_ALIGNMENT;
485
486 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
487 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
488 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
489 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
490 case PIPE_CAP_MAX_VERTEX_STREAMS:
491 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
492 return 4;
493
494 case PIPE_CAP_GLSL_FEATURE_LEVEL:
495 if (si_have_tgsi_compute(sscreen))
496 return 450;
497 return 420;
498
499 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
500 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
501
502 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
503 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
504 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
505 /* SI doesn't support unaligned loads.
506 * CIK needs DRM 2.50.0 on radeon. */
507 return sscreen->b.chip_class == SI ||
508 (sscreen->b.info.drm_major == 2 &&
509 sscreen->b.info.drm_minor < 50);
510
511 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
512 /* Disable on SI due to VM faults in CP DMA. Enable once these
513 * faults are mitigated in software.
514 */
515 if (sscreen->b.chip_class >= CIK &&
516 sscreen->b.info.drm_major == 3 &&
517 sscreen->b.info.drm_minor >= 13)
518 return RADEON_SPARSE_PAGE_SIZE;
519 return 0;
520
521 /* Unsupported features. */
522 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
523 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
524 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
525 case PIPE_CAP_USER_VERTEX_BUFFERS:
526 case PIPE_CAP_FAKE_SW_MSAA:
527 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
528 case PIPE_CAP_VERTEXID_NOBASE:
529 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
530 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
531 case PIPE_CAP_NATIVE_FENCE_FD:
532 case PIPE_CAP_TGSI_FS_FBFETCH:
533 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
534 case PIPE_CAP_UMA:
535 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
536 return 0;
537
538 case PIPE_CAP_QUERY_BUFFER_OBJECT:
539 return si_have_tgsi_compute(sscreen);
540
541 case PIPE_CAP_DRAW_PARAMETERS:
542 case PIPE_CAP_MULTI_DRAW_INDIRECT:
543 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
544 return sscreen->has_draw_indirect_multi;
545
546 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
547 return 30;
548
549 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
550 return sscreen->b.chip_class <= VI ?
551 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
552
553 /* Stream output. */
554 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
555 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
556 return 32*4;
557
558 /* Geometry shader output. */
559 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
560 return 1024;
561 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
562 return 4095;
563
564 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
565 return 2048;
566
567 /* Texturing. */
568 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
569 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
570 return 15; /* 16384 */
571 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
572 /* textures support 8192, but layered rendering supports 2048 */
573 return 12;
574 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
575 /* textures support 8192, but layered rendering supports 2048 */
576 return 2048;
577
578 /* Viewports and render targets. */
579 case PIPE_CAP_MAX_VIEWPORTS:
580 return R600_MAX_VIEWPORTS;
581 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
582 case PIPE_CAP_MAX_RENDER_TARGETS:
583 return 8;
584
585 /* Timer queries, present when the clock frequency is non zero. */
586 case PIPE_CAP_QUERY_TIMESTAMP:
587 case PIPE_CAP_QUERY_TIME_ELAPSED:
588 return sscreen->b.info.clock_crystal_freq != 0;
589
590 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
591 case PIPE_CAP_MIN_TEXEL_OFFSET:
592 return -32;
593
594 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
595 case PIPE_CAP_MAX_TEXEL_OFFSET:
596 return 31;
597
598 case PIPE_CAP_ENDIANNESS:
599 return PIPE_ENDIAN_LITTLE;
600
601 case PIPE_CAP_VENDOR_ID:
602 return ATI_VENDOR_ID;
603 case PIPE_CAP_DEVICE_ID:
604 return sscreen->b.info.pci_id;
605 case PIPE_CAP_VIDEO_MEMORY:
606 return sscreen->b.info.vram_size >> 20;
607 case PIPE_CAP_PCI_GROUP:
608 return sscreen->b.info.pci_domain;
609 case PIPE_CAP_PCI_BUS:
610 return sscreen->b.info.pci_bus;
611 case PIPE_CAP_PCI_DEVICE:
612 return sscreen->b.info.pci_dev;
613 case PIPE_CAP_PCI_FUNCTION:
614 return sscreen->b.info.pci_func;
615 }
616 return 0;
617 }
618
619 static int si_get_shader_param(struct pipe_screen* pscreen,
620 enum pipe_shader_type shader,
621 enum pipe_shader_cap param)
622 {
623 struct si_screen *sscreen = (struct si_screen *)pscreen;
624
625 switch(shader)
626 {
627 case PIPE_SHADER_FRAGMENT:
628 case PIPE_SHADER_VERTEX:
629 case PIPE_SHADER_GEOMETRY:
630 case PIPE_SHADER_TESS_CTRL:
631 case PIPE_SHADER_TESS_EVAL:
632 break;
633 case PIPE_SHADER_COMPUTE:
634 switch (param) {
635 case PIPE_SHADER_CAP_PREFERRED_IR:
636 return PIPE_SHADER_IR_NATIVE;
637
638 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
639 int ir = 1 << PIPE_SHADER_IR_NATIVE;
640
641 if (si_have_tgsi_compute(sscreen))
642 ir |= 1 << PIPE_SHADER_IR_TGSI;
643
644 return ir;
645 }
646
647 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
648 uint64_t max_const_buffer_size;
649 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
650 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
651 &max_const_buffer_size);
652 return MIN2(max_const_buffer_size, INT_MAX);
653 }
654 default:
655 /* If compute shaders don't require a special value
656 * for this cap, we can return the same value we
657 * do for other shader types. */
658 break;
659 }
660 break;
661 default:
662 return 0;
663 }
664
665 switch (param) {
666 /* Shader limits. */
667 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
668 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
669 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
670 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
671 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
672 return 16384;
673 case PIPE_SHADER_CAP_MAX_INPUTS:
674 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
675 case PIPE_SHADER_CAP_MAX_OUTPUTS:
676 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
677 case PIPE_SHADER_CAP_MAX_TEMPS:
678 return 256; /* Max native temporaries. */
679 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
680 return 4096 * sizeof(float[4]); /* actually only memory limits this */
681 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
682 return SI_NUM_CONST_BUFFERS;
683 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
684 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
685 return SI_NUM_SAMPLERS;
686 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
687 return SI_NUM_SHADER_BUFFERS;
688 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
689 return SI_NUM_IMAGES;
690 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
691 return 32;
692 case PIPE_SHADER_CAP_PREFERRED_IR:
693 return PIPE_SHADER_IR_TGSI;
694 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
695 return 3;
696
697 /* Supported boolean features. */
698 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
699 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
700 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
701 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
702 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
703 case PIPE_SHADER_CAP_INTEGERS:
704 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
705 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
706 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
707 return 1;
708
709 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
710 /* TODO: Indirection of geometry shader input dimension is not
711 * handled yet
712 */
713 return shader != PIPE_SHADER_GEOMETRY;
714
715 /* Unsupported boolean features. */
716 case PIPE_SHADER_CAP_SUBROUTINES:
717 case PIPE_SHADER_CAP_SUPPORTED_IRS:
718 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
719 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
720 return 0;
721 }
722 return 0;
723 }
724
725 static void si_destroy_screen(struct pipe_screen* pscreen)
726 {
727 struct si_screen *sscreen = (struct si_screen *)pscreen;
728 struct si_shader_part *parts[] = {
729 sscreen->vs_prologs,
730 sscreen->tcs_epilogs,
731 sscreen->gs_prologs,
732 sscreen->ps_prologs,
733 sscreen->ps_epilogs
734 };
735 unsigned i;
736
737 if (!sscreen->b.ws->unref(sscreen->b.ws))
738 return;
739
740 util_queue_destroy(&sscreen->shader_compiler_queue);
741
742 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
743 if (sscreen->tm[i])
744 LLVMDisposeTargetMachine(sscreen->tm[i]);
745
746 /* Free shader parts. */
747 for (i = 0; i < ARRAY_SIZE(parts); i++) {
748 while (parts[i]) {
749 struct si_shader_part *part = parts[i];
750
751 parts[i] = part->next;
752 radeon_shader_binary_clean(&part->binary);
753 FREE(part);
754 }
755 }
756 mtx_destroy(&sscreen->shader_parts_mutex);
757 si_destroy_shader_cache(sscreen);
758 r600_destroy_common_screen(&sscreen->b);
759 }
760
761 static bool si_init_gs_info(struct si_screen *sscreen)
762 {
763 switch (sscreen->b.family) {
764 case CHIP_OLAND:
765 case CHIP_HAINAN:
766 case CHIP_KAVERI:
767 case CHIP_KABINI:
768 case CHIP_MULLINS:
769 case CHIP_ICELAND:
770 case CHIP_CARRIZO:
771 case CHIP_STONEY:
772 sscreen->gs_table_depth = 16;
773 return true;
774 case CHIP_TAHITI:
775 case CHIP_PITCAIRN:
776 case CHIP_VERDE:
777 case CHIP_BONAIRE:
778 case CHIP_HAWAII:
779 case CHIP_TONGA:
780 case CHIP_FIJI:
781 case CHIP_POLARIS10:
782 case CHIP_POLARIS11:
783 case CHIP_POLARIS12:
784 case CHIP_VEGA10:
785 case CHIP_RAVEN:
786 sscreen->gs_table_depth = 32;
787 return true;
788 default:
789 return false;
790 }
791 }
792
793 static void si_handle_env_var_force_family(struct si_screen *sscreen)
794 {
795 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
796 unsigned i;
797
798 if (!family)
799 return;
800
801 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
802 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
803 /* Override family and chip_class. */
804 sscreen->b.family = sscreen->b.info.family = i;
805
806 if (i >= CHIP_VEGA10)
807 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
808 else if (i >= CHIP_TONGA)
809 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
810 else if (i >= CHIP_BONAIRE)
811 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
812 else
813 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
814
815 /* Don't submit any IBs. */
816 setenv("RADEON_NOOP", "1", 1);
817 return;
818 }
819 }
820
821 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
822 exit(1);
823 }
824
825 static void si_test_vmfault(struct si_screen *sscreen)
826 {
827 struct pipe_context *ctx = sscreen->b.aux_context;
828 struct si_context *sctx = (struct si_context *)ctx;
829 struct pipe_resource *buf =
830 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
831
832 if (!buf) {
833 puts("Buffer allocation failed.");
834 exit(1);
835 }
836
837 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
838
839 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
840 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
841 ctx->flush(ctx, NULL, 0);
842 puts("VM fault test: CP - done.");
843 }
844 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
845 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
846 ctx->flush(ctx, NULL, 0);
847 puts("VM fault test: SDMA - done.");
848 }
849 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
850 util_test_constant_buffer(ctx, buf);
851 puts("VM fault test: Shader - done.");
852 }
853 exit(0);
854 }
855
856 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
857 {
858 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
859 unsigned num_cpus, num_compiler_threads, i;
860
861 if (!sscreen) {
862 return NULL;
863 }
864
865 /* Set functions first. */
866 sscreen->b.b.context_create = si_pipe_create_context;
867 sscreen->b.b.destroy = si_destroy_screen;
868 sscreen->b.b.get_param = si_get_param;
869 sscreen->b.b.get_shader_param = si_get_shader_param;
870 sscreen->b.b.resource_create = r600_resource_create_common;
871
872 si_init_screen_state_functions(sscreen);
873
874 if (!r600_common_screen_init(&sscreen->b, ws) ||
875 !si_init_gs_info(sscreen) ||
876 !si_init_shader_cache(sscreen)) {
877 FREE(sscreen);
878 return NULL;
879 }
880
881 /* Only enable as many threads as we have target machines and CPUs. */
882 num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
883 num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
884
885 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
886 32, num_compiler_threads)) {
887 si_destroy_shader_cache(sscreen);
888 FREE(sscreen);
889 return NULL;
890 }
891
892 si_handle_env_var_force_family(sscreen);
893
894 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
895 si_init_perfcounters(sscreen);
896
897 /* Hawaii has a bug with offchip buffers > 256 that can be worked
898 * around by setting 4K granularity.
899 */
900 sscreen->tess_offchip_block_dw_size =
901 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
902
903 sscreen->has_distributed_tess =
904 sscreen->b.chip_class >= VI &&
905 sscreen->b.info.max_se >= 2;
906
907 sscreen->has_draw_indirect_multi =
908 (sscreen->b.family >= CHIP_POLARIS10) ||
909 (sscreen->b.chip_class == VI &&
910 sscreen->b.info.pfp_fw_version >= 121 &&
911 sscreen->b.info.me_fw_version >= 87) ||
912 (sscreen->b.chip_class == CIK &&
913 sscreen->b.info.pfp_fw_version >= 211 &&
914 sscreen->b.info.me_fw_version >= 173) ||
915 (sscreen->b.chip_class == SI &&
916 sscreen->b.info.pfp_fw_version >= 121 &&
917 sscreen->b.info.me_fw_version >= 87);
918
919 sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
920 sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
921 sscreen->b.family <= CHIP_POLARIS12) ||
922 sscreen->b.family == CHIP_VEGA10 ||
923 sscreen->b.family == CHIP_RAVEN;
924
925 sscreen->b.has_cp_dma = true;
926 sscreen->b.has_streamout = true;
927
928 /* Some chips have RB+ registers, but don't support RB+. Those must
929 * always disable it.
930 */
931 if (sscreen->b.family == CHIP_STONEY ||
932 sscreen->b.chip_class >= GFX9) {
933 sscreen->b.has_rbplus = true;
934
935 sscreen->b.rbplus_allowed =
936 !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
937 (sscreen->b.family == CHIP_STONEY ||
938 sscreen->b.family == CHIP_RAVEN);
939 }
940
941 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
942 sscreen->use_monolithic_shaders =
943 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
944
945 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
946 SI_CONTEXT_INV_VMEM_L1 |
947 SI_CONTEXT_INV_GLOBAL_L2;
948 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
949
950 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
951 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
952
953 for (i = 0; i < num_compiler_threads; i++)
954 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
955
956 /* Create the auxiliary context. This must be done last. */
957 sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
958
959 if (sscreen->b.debug_flags & DBG_TEST_DMA)
960 r600_test_dma(&sscreen->b);
961
962 if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
963 DBG_TEST_VMFAULT_SDMA |
964 DBG_TEST_VMFAULT_SHADER))
965 si_test_vmfault(sscreen);
966
967 return &sscreen->b.b;
968 }