src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "vl/vl_decoder.h"
  33
  34 /*
  35  * pipe_context
  36  */
  37 static void si_destroy_context(struct pipe_context *context)
  38 {
  39         struct si_context *sctx = (struct si_context *)context;
  40         int i;
  41
  42         si_release_all_descriptors(sctx);
  43
  44         pipe_resource_reference(&sctx->esgs_ring, NULL);
  45         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  46         pipe_resource_reference(&sctx->tf_ring, NULL);
  47         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  48         r600_resource_reference(&sctx->border_color_buffer, NULL);
  49         free(sctx->border_color_table);
  50         r600_resource_reference(&sctx->scratch_buffer, NULL);
  51         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  52
  53         si_pm4_free_state(sctx, sctx->init_config, ~0);
  54         if (sctx->init_config_gs_rings)
  55                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  56         for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
  57                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  58
  59         if (sctx->pstipple_sampler_state)
  60                 sctx->b.b.delete_sampler_state(&sctx->b.b, sctx->pstipple_sampler_state);
  61         if (sctx->fixed_func_tcs_shader.cso)
  62                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  63         if (sctx->custom_dsa_flush)
  64                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  65         if (sctx->custom_blend_resolve)
  66                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  67         if (sctx->custom_blend_decompress)
  68                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  69         if (sctx->custom_blend_fastclear)
  70                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  71         if (sctx->custom_blend_dcc_decompress)
  72                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  73         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  74
  75         if (sctx->blitter)
  76                 util_blitter_destroy(sctx->blitter);
  77
  78         r600_common_context_cleanup(&sctx->b);
  79
  80         LLVMDisposeTargetMachine(sctx->tm);
  81
  82         r600_resource_reference(&sctx->trace_buf, NULL);
  83         r600_resource_reference(&sctx->last_trace_buf, NULL);
  84         free(sctx->last_ib);
  85         if (sctx->last_bo_list) {
  86                 for (i = 0; i < sctx->last_bo_count; i++)
  87                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  88                 free(sctx->last_bo_list);
  89         }
  90         FREE(sctx);
  91 }
  92
  93 static enum pipe_reset_status
  94 si_amdgpu_get_reset_status(struct pipe_context *ctx)
  95 {
  96         struct si_context *sctx = (struct si_context *)ctx;
  97
  98         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
  99 }
 100
 101 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 102                                               void *priv, unsigned flags)
 103 {
 104         struct si_context *sctx = CALLOC_STRUCT(si_context);
 105         struct si_screen* sscreen = (struct si_screen *)screen;
 106         struct radeon_winsys *ws = sscreen->b.ws;
 107         LLVMTargetRef r600_target;
 108         const char *triple = "amdgcn--";
 109         int shader, i;
 110
 111         if (!sctx)
 112                 return NULL;
 113
 114         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 115                 flags |= PIPE_CONTEXT_DEBUG;
 116
 117         sctx->b.b.screen = screen; /* this must be set first */
 118         sctx->b.b.priv = priv;
 119         sctx->b.b.destroy = si_destroy_context;
 120         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 121         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 122         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 123
 124         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 125                 goto fail;
 126
 127         if (sscreen->b.info.drm_major == 3)
 128                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 129
 130         si_init_blit_functions(sctx);
 131         si_init_compute_functions(sctx);
 132         si_init_cp_dma_functions(sctx);
 133         si_init_debug_functions(sctx);
 134
 135         if (sscreen->b.info.has_uvd) {
 136                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 137                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 138         } else {
 139                 sctx->b.b.create_video_codec = vl_create_decoder;
 140                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 141         }
 142
 143         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 144                                        si_context_gfx_flush, sctx);
 145
 146         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 147                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 148                 if (!sctx->ce_ib)
 149                         goto fail;
 150
 151                 if (ws->cs_add_const_preamble_ib) {
 152                         sctx->ce_preamble_ib =
 153                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 154
 155                         if (!sctx->ce_preamble_ib)
 156                                 goto fail;
 157                 }
 158         }
 159
 160         sctx->b.gfx.flush = si_context_gfx_flush;
 161
 162         /* Border colors. */
 163         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 164                                           sizeof(*sctx->border_color_table));
 165         if (!sctx->border_color_table)
 166                 goto fail;
 167
 168         sctx->border_color_buffer = (struct r600_resource*)
 169                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 170                                    SI_MAX_BORDER_COLORS *
 171                                    sizeof(*sctx->border_color_table));
 172         if (!sctx->border_color_buffer)
 173                 goto fail;
 174
 175         sctx->border_color_map =
 176                 ws->buffer_map(sctx->border_color_buffer->buf,
 177                                NULL, PIPE_TRANSFER_WRITE);
 178         if (!sctx->border_color_map)
 179                 goto fail;
 180
 181         si_init_all_descriptors(sctx);
 182         si_init_state_functions(sctx);
 183         si_init_shader_functions(sctx);
 184
 185         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 186                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 187
 188         sctx->blitter = util_blitter_create(&sctx->b.b);
 189         if (sctx->blitter == NULL)
 190                 goto fail;
 191         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 192
 193         sctx->sample_mask.sample_mask = 0xffff;
 194
 195         /* these must be last */
 196         si_begin_new_cs(sctx);
 197         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 198
 199         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 200          * with a NULL buffer). We need to use a dummy buffer instead. */
 201         if (sctx->b.chip_class == CIK) {
 202                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 203                                                                  PIPE_USAGE_DEFAULT, 16);
 204                 if (!sctx->null_const_buf.buffer)
 205                         goto fail;
 206                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 207
 208                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 209                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 210                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 211                                                               &sctx->null_const_buf);
 212                         }
 213                 }
 214
 215                 /* Clear the NULL constant buffer, because loads should return zeros. */
 216                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 217                                      sctx->null_const_buf.buffer->width0, 0, false);
 218         }
 219
 220         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 221          * this for non-cs shaders.  Using the wrong value here can result in
 222          * GPU lockups, but the maximum value seems to always work.
 223          */
 224         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 225
 226         /* Initialize LLVM TargetMachine */
 227         r600_target = radeon_llvm_get_r600_target(triple);
 228         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 229                                            r600_get_llvm_processor_name(sscreen->b.family),
 230 #if HAVE_LLVM >= 0x0308
 231                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 232                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 233 #endif
 234                                                 "+DumpCode,+vgpr-spilling",
 235                                            LLVMCodeGenLevelDefault,
 236                                            LLVMRelocDefault,
 237                                            LLVMCodeModelDefault);
 238
 239         return &sctx->b.b;
 240 fail:
 241         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 242         si_destroy_context(&sctx->b.b);
 243         return NULL;
 244 }
 245
 246 /*
 247  * pipe_screen
 248  */
 249
 250 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 251 {
 252         struct si_screen *sscreen = (struct si_screen *)pscreen;
 253
 254         switch (param) {
 255         /* Supported features (boolean caps). */
 256         case PIPE_CAP_TWO_SIDED_STENCIL:
 257         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 258         case PIPE_CAP_ANISOTROPIC_FILTER:
 259         case PIPE_CAP_POINT_SPRITE:
 260         case PIPE_CAP_OCCLUSION_QUERY:
 261         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 262         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 263         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 264         case PIPE_CAP_TEXTURE_SWIZZLE:
 265         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 266         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 267         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 268         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 269         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 270         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 271         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 272         case PIPE_CAP_SM3:
 273         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 274         case PIPE_CAP_PRIMITIVE_RESTART:
 275         case PIPE_CAP_CONDITIONAL_RENDER:
 276         case PIPE_CAP_TEXTURE_BARRIER:
 277         case PIPE_CAP_INDEP_BLEND_ENABLE:
 278         case PIPE_CAP_INDEP_BLEND_FUNC:
 279         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 280         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 281         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 282         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 283         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 284         case PIPE_CAP_USER_INDEX_BUFFERS:
 285         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 286         case PIPE_CAP_START_INSTANCE:
 287         case PIPE_CAP_NPOT_TEXTURES:
 288         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 289         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 290         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 291         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 292         case PIPE_CAP_TGSI_INSTANCEID:
 293         case PIPE_CAP_COMPUTE:
 294         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 295         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 296         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 297         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 298         case PIPE_CAP_CUBE_MAP_ARRAY:
 299         case PIPE_CAP_SAMPLE_SHADING:
 300         case PIPE_CAP_DRAW_INDIRECT:
 301         case PIPE_CAP_CLIP_HALFZ:
 302         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 303         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 304         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 305         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 306         case PIPE_CAP_TGSI_TEXCOORD:
 307         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 308         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 309         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 310         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 311         case PIPE_CAP_SHAREABLE_SHADERS:
 312         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 313         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 314         case PIPE_CAP_TEXTURE_QUERY_LOD:
 315         case PIPE_CAP_TEXTURE_GATHER_SM5:
 316         case PIPE_CAP_TGSI_TXQS:
 317         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 318         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 319         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 320         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 321         case PIPE_CAP_INVALIDATE_BUFFER:
 322         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 323         case PIPE_CAP_QUERY_MEMORY_INFO:
 324         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 325         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 326         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 327                 return 1;
 328
 329         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 330                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 331
 332         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 333                 return (sscreen->b.info.drm_major == 2 &&
 334                         sscreen->b.info.drm_minor >= 43) ||
 335                        sscreen->b.info.drm_major == 3;
 336
 337         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 338                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 339                 return sscreen->b.chip_class < CIK ||
 340                        (sscreen->b.info.drm_major == 2 &&
 341                         sscreen->b.info.drm_minor >= 35) ||
 342                        sscreen->b.info.drm_major == 3;
 343
 344         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 345                 return R600_MAP_BUFFER_ALIGNMENT;
 346
 347         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 348         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 349         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 350                 return 4;
 351         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 352                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 353
 354         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 355                 return HAVE_LLVM >= 0x0309 ? 420 :
 356                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 357
 358         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 359                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 360
 361         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 362                 return 0;
 363
 364         /* Unsupported features. */
 365         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 366         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 367         case PIPE_CAP_USER_VERTEX_BUFFERS:
 368         case PIPE_CAP_FAKE_SW_MSAA:
 369         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 370         case PIPE_CAP_VERTEXID_NOBASE:
 371         case PIPE_CAP_CLEAR_TEXTURE:
 372         case PIPE_CAP_DRAW_PARAMETERS:
 373         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 374         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 375         case PIPE_CAP_GENERATE_MIPMAP:
 376         case PIPE_CAP_STRING_MARKER:
 377         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 378                 return 0;
 379
 380         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 381                 return 30;
 382
 383         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 384                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 385
 386         /* Stream output. */
 387         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 388                 return sscreen->b.has_streamout ? 4 : 0;
 389         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 390                 return sscreen->b.has_streamout ? 1 : 0;
 391         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 392         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 393                 return sscreen->b.has_streamout ? 32*4 : 0;
 394
 395         /* Geometry shader output. */
 396         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 397                 return 1024;
 398         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 399                 return 4095;
 400         case PIPE_CAP_MAX_VERTEX_STREAMS:
 401                 return 4;
 402
 403         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 404                 return 2048;
 405
 406         /* Texturing. */
 407         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 408         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 409                 return 15; /* 16384 */
 410         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 411                 /* textures support 8192, but layered rendering supports 2048 */
 412                 return 12;
 413         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 414                 /* textures support 8192, but layered rendering supports 2048 */
 415                 return 2048;
 416
 417         /* Render targets. */
 418         case PIPE_CAP_MAX_RENDER_TARGETS:
 419                 return 8;
 420
 421         case PIPE_CAP_MAX_VIEWPORTS:
 422                 return R600_MAX_VIEWPORTS;
 423
 424         /* Timer queries, present when the clock frequency is non zero. */
 425         case PIPE_CAP_QUERY_TIMESTAMP:
 426         case PIPE_CAP_QUERY_TIME_ELAPSED:
 427                 return sscreen->b.info.clock_crystal_freq != 0;
 428
 429         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 430         case PIPE_CAP_MIN_TEXEL_OFFSET:
 431                 return -32;
 432
 433         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 434         case PIPE_CAP_MAX_TEXEL_OFFSET:
 435                 return 31;
 436
 437         case PIPE_CAP_ENDIANNESS:
 438                 return PIPE_ENDIAN_LITTLE;
 439
 440         case PIPE_CAP_VENDOR_ID:
 441                 return ATI_VENDOR_ID;
 442         case PIPE_CAP_DEVICE_ID:
 443                 return sscreen->b.info.pci_id;
 444         case PIPE_CAP_ACCELERATED:
 445                 return 1;
 446         case PIPE_CAP_VIDEO_MEMORY:
 447                 return sscreen->b.info.vram_size >> 20;
 448         case PIPE_CAP_UMA:
 449                 return 0;
 450         case PIPE_CAP_PCI_GROUP:
 451                 return sscreen->b.info.pci_domain;
 452         case PIPE_CAP_PCI_BUS:
 453                 return sscreen->b.info.pci_bus;
 454         case PIPE_CAP_PCI_DEVICE:
 455                 return sscreen->b.info.pci_dev;
 456         case PIPE_CAP_PCI_FUNCTION:
 457                 return sscreen->b.info.pci_func;
 458         }
 459         return 0;
 460 }
 461
 462 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 463 {
 464         switch(shader)
 465         {
 466         case PIPE_SHADER_FRAGMENT:
 467         case PIPE_SHADER_VERTEX:
 468         case PIPE_SHADER_GEOMETRY:
 469                 break;
 470         case PIPE_SHADER_TESS_CTRL:
 471         case PIPE_SHADER_TESS_EVAL:
 472                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 473                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 474                         return 0;
 475                 break;
 476         case PIPE_SHADER_COMPUTE:
 477                 switch (param) {
 478                 case PIPE_SHADER_CAP_PREFERRED_IR:
 479                         return PIPE_SHADER_IR_NATIVE;
 480
 481                 case PIPE_SHADER_CAP_SUPPORTED_IRS:
 482                         return 0;
 483
 484                 case PIPE_SHADER_CAP_DOUBLES:
 485                         return HAVE_LLVM >= 0x0307;
 486
 487                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 488                         uint64_t max_const_buffer_size;
 489                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 490                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 491                                 &max_const_buffer_size);
 492                         return max_const_buffer_size;
 493                 }
 494                 default:
 495                         /* If compute shaders don't require a special value
 496                          * for this cap, we can return the same value we
 497                          * do for other shader types. */
 498                         break;
 499                 }
 500                 break;
 501         default:
 502                 return 0;
 503         }
 504
 505         switch (param) {
 506         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 507         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 508         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 509         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 510                 return 16384;
 511         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 512                 return 32;
 513         case PIPE_SHADER_CAP_MAX_INPUTS:
 514                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 515         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 516                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 517         case PIPE_SHADER_CAP_MAX_TEMPS:
 518                 return 256; /* Max native temporaries. */
 519         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 520                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 521         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 522                 return SI_NUM_USER_CONST_BUFFERS;
 523         case PIPE_SHADER_CAP_MAX_PREDS:
 524                 return 0; /* FIXME */
 525         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 526                 return 1;
 527         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 528                 return 1;
 529         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 530                 /* Indirection of geometry shader input dimension is not
 531                  * handled yet
 532                  */
 533                 return shader != PIPE_SHADER_GEOMETRY;
 534         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 535         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 536         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 537                 return 1;
 538         case PIPE_SHADER_CAP_INTEGERS:
 539                 return 1;
 540         case PIPE_SHADER_CAP_SUBROUTINES:
 541                 return 0;
 542         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 543         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 544                 return SI_NUM_USER_SAMPLERS;
 545         case PIPE_SHADER_CAP_PREFERRED_IR:
 546                 return PIPE_SHADER_IR_TGSI;
 547         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 548                 return 0;
 549         case PIPE_SHADER_CAP_DOUBLES:
 550                 return HAVE_LLVM >= 0x0307;
 551         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 552         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 553                 return 0;
 554         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 555         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 556                 return 1;
 557         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 558                 return 32;
 559         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 560                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 561         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 562                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 563         }
 564         return 0;
 565 }
 566
 567 static void si_destroy_screen(struct pipe_screen* pscreen)
 568 {
 569         struct si_screen *sscreen = (struct si_screen *)pscreen;
 570         struct si_shader_part *parts[] = {
 571                 sscreen->vs_prologs,
 572                 sscreen->vs_epilogs,
 573                 sscreen->tcs_epilogs,
 574                 sscreen->ps_prologs,
 575                 sscreen->ps_epilogs
 576         };
 577         unsigned i;
 578
 579         if (!sscreen)
 580                 return;
 581
 582         if (!sscreen->b.ws->unref(sscreen->b.ws))
 583                 return;
 584
 585         /* Free shader parts. */
 586         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 587                 while (parts[i]) {
 588                         struct si_shader_part *part = parts[i];
 589
 590                         parts[i] = part->next;
 591                         radeon_shader_binary_clean(&part->binary);
 592                         FREE(part);
 593                 }
 594         }
 595         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 596         si_destroy_shader_cache(sscreen);
 597         r600_destroy_common_screen(&sscreen->b);
 598 }
 599
 600 static bool si_init_gs_info(struct si_screen *sscreen)
 601 {
 602         switch (sscreen->b.family) {
 603         case CHIP_OLAND:
 604         case CHIP_HAINAN:
 605         case CHIP_KAVERI:
 606         case CHIP_KABINI:
 607         case CHIP_MULLINS:
 608         case CHIP_ICELAND:
 609         case CHIP_CARRIZO:
 610         case CHIP_STONEY:
 611                 sscreen->gs_table_depth = 16;
 612                 return true;
 613         case CHIP_TAHITI:
 614         case CHIP_PITCAIRN:
 615         case CHIP_VERDE:
 616         case CHIP_BONAIRE:
 617         case CHIP_HAWAII:
 618         case CHIP_TONGA:
 619         case CHIP_FIJI:
 620         case CHIP_POLARIS10:
 621         case CHIP_POLARIS11:
 622                 sscreen->gs_table_depth = 32;
 623                 return true;
 624         default:
 625                 return false;
 626         }
 627 }
 628
 629 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 630 {
 631         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 632
 633         if (!sscreen) {
 634                 return NULL;
 635         }
 636
 637         /* Set functions first. */
 638         sscreen->b.b.context_create = si_create_context;
 639         sscreen->b.b.destroy = si_destroy_screen;
 640         sscreen->b.b.get_param = si_get_param;
 641         sscreen->b.b.get_shader_param = si_get_shader_param;
 642         sscreen->b.b.is_format_supported = si_is_format_supported;
 643         sscreen->b.b.resource_create = r600_resource_create_common;
 644
 645         si_init_screen_state_functions(sscreen);
 646
 647         if (!r600_common_screen_init(&sscreen->b, ws) ||
 648             !si_init_gs_info(sscreen) ||
 649             !si_init_shader_cache(sscreen)) {
 650                 FREE(sscreen);
 651                 return NULL;
 652         }
 653
 654         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 655                 si_init_perfcounters(sscreen);
 656
 657         sscreen->b.has_cp_dma = true;
 658         sscreen->b.has_streamout = true;
 659         pipe_mutex_init(sscreen->shader_parts_mutex);
 660         sscreen->use_monolithic_shaders =
 661                 HAVE_LLVM < 0x0308 ||
 662                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 663
 664         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 665                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 666
 667         /* Create the auxiliary context. This must be done last. */
 668         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 669
 670         return &sscreen->b.b;
 671 }