src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_public.h"
  26
  27 #include "radeon/radeon_uvd.h"
  28 #include "util/u_blitter.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_simple_shaders.h"
  31 #include "vl/vl_decoder.h"
  32
  33 /*
  34  * pipe_context
  35  */
  36 static void si_destroy_context(struct pipe_context *context)
  37 {
  38         struct si_context *sctx = (struct si_context *)context;
  39
  40         si_release_all_descriptors(sctx);
  41
  42         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  43         r600_resource_reference(&sctx->border_color_table, NULL);
  44
  45         si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
  46         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_on);
  47         si_pm4_delete_state(sctx, gs_onoff, sctx->gs_off);
  48
  49         if (sctx->dummy_pixel_shader) {
  50                 sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
  51         }
  52         for (int i = 0; i < 8; i++) {
  53                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
  54                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
  55                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
  56         }
  57         sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
  58         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  59         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  60         sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  61         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  62
  63         util_blitter_destroy(sctx->blitter);
  64
  65         si_pm4_cleanup(sctx);
  66
  67         r600_common_context_cleanup(&sctx->b);
  68         FREE(sctx);
  69 }
  70
  71 static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
  72 {
  73         struct si_context *sctx = CALLOC_STRUCT(si_context);
  74         struct si_screen* sscreen = (struct si_screen *)screen;
  75         struct radeon_winsys *ws = sscreen->b.ws;
  76         int shader, i;
  77
  78         if (sctx == NULL)
  79                 return NULL;
  80
  81         sctx->b.b.screen = screen; /* this must be set first */
  82         sctx->b.b.priv = priv;
  83         sctx->b.b.destroy = si_destroy_context;
  84         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
  85
  86         if (!r600_common_context_init(&sctx->b, &sscreen->b))
  87                 goto fail;
  88
  89         si_init_blit_functions(sctx);
  90         si_init_compute_functions(sctx);
  91
  92         if (sscreen->b.info.has_uvd) {
  93                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
  94                 sctx->b.b.create_video_buffer = si_video_buffer_create;
  95         } else {
  96                 sctx->b.b.create_video_codec = vl_create_decoder;
  97                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
  98         }
  99
 100         sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
 101                                              sctx, NULL);
 102         sctx->b.rings.gfx.flush = si_context_gfx_flush;
 103
 104         si_init_all_descriptors(sctx);
 105
 106         /* Initialize cache_flush. */
 107         sctx->cache_flush = si_atom_cache_flush;
 108         sctx->atoms.s.cache_flush = &sctx->cache_flush;
 109
 110         sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
 111         sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 112
 113         switch (sctx->b.chip_class) {
 114         case SI:
 115         case CIK:
 116                 si_init_state_functions(sctx);
 117                 si_init_config(sctx);
 118                 break;
 119         default:
 120                 R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
 121                 goto fail;
 122         }
 123
 124         sctx->blitter = util_blitter_create(&sctx->b.b);
 125         if (sctx->blitter == NULL)
 126                 goto fail;
 127
 128         sctx->dummy_pixel_shader =
 129                 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
 130                                                      TGSI_SEMANTIC_GENERIC,
 131                                                      TGSI_INTERPOLATE_CONSTANT);
 132         sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
 133
 134         /* these must be last */
 135         si_begin_new_cs(sctx);
 136         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 137
 138         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 139          * with a NULL buffer). We need to use a dummy buffer instead. */
 140         if (sctx->b.chip_class == CIK) {
 141                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 142                                                                  PIPE_USAGE_DEFAULT, 16);
 143                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 144
 145                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 146                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 147                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 148                                                               &sctx->null_const_buf);
 149                         }
 150                 }
 151
 152                 /* Clear the NULL constant buffer, because loads should return zeros. */
 153                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 154                                      sctx->null_const_buf.buffer->width0, 0);
 155         }
 156
 157         return &sctx->b.b;
 158 fail:
 159         si_destroy_context(&sctx->b.b);
 160         return NULL;
 161 }
 162
 163 /*
 164  * pipe_screen
 165  */
 166
 167 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 168 {
 169         struct si_screen *sscreen = (struct si_screen *)pscreen;
 170
 171         switch (param) {
 172         /* Supported features (boolean caps). */
 173         case PIPE_CAP_TWO_SIDED_STENCIL:
 174         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 175         case PIPE_CAP_ANISOTROPIC_FILTER:
 176         case PIPE_CAP_POINT_SPRITE:
 177         case PIPE_CAP_OCCLUSION_QUERY:
 178         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 179         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 180         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 181         case PIPE_CAP_TEXTURE_SWIZZLE:
 182         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 183         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 184         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 185         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 186         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 187         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 188         case PIPE_CAP_SM3:
 189         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 190         case PIPE_CAP_PRIMITIVE_RESTART:
 191         case PIPE_CAP_CONDITIONAL_RENDER:
 192         case PIPE_CAP_TEXTURE_BARRIER:
 193         case PIPE_CAP_INDEP_BLEND_ENABLE:
 194         case PIPE_CAP_INDEP_BLEND_FUNC:
 195         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 196         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 197         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 200         case PIPE_CAP_USER_INDEX_BUFFERS:
 201         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 202         case PIPE_CAP_START_INSTANCE:
 203         case PIPE_CAP_NPOT_TEXTURES:
 204         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 205         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 206         case PIPE_CAP_TGSI_INSTANCEID:
 207         case PIPE_CAP_COMPUTE:
 208         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 209         case PIPE_CAP_TGSI_VS_LAYER:
 210         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 211         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 212         case PIPE_CAP_CUBE_MAP_ARRAY:
 213                 return 1;
 214
 215         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 216                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 217                 return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
 218                                                sscreen->b.info.drm_minor >= 35);
 219
 220         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 221                 return R600_MAP_BUFFER_ALIGNMENT;
 222
 223         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 224         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 225                 return 4;
 226
 227         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 228                 return HAVE_LLVM >= 0x0305 ? 330 : 140;
 229
 230         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 231                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 232
 233         /* Unsupported features. */
 234         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 235         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 236         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 237         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 238         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 239         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 240         case PIPE_CAP_USER_VERTEX_BUFFERS:
 241         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 242         case PIPE_CAP_TEXTURE_GATHER_SM5:
 243         case PIPE_CAP_TGSI_TEXCOORD:
 244         case PIPE_CAP_FAKE_SW_MSAA:
 245         case PIPE_CAP_TEXTURE_QUERY_LOD:
 246         case PIPE_CAP_SAMPLE_SHADING:
 247         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 248                 return 0;
 249
 250         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 251                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 252
 253         /* Stream output. */
 254         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 255                 return sscreen->b.has_streamout ? 4 : 0;
 256         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 257                 return sscreen->b.has_streamout ? 1 : 0;
 258         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 259         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 260                 return sscreen->b.has_streamout ? 32*4 : 0;
 261
 262         /* Geometry shader output. */
 263         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 264                 return 1024;
 265         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 266                 return 4095;
 267
 268         /* Texturing. */
 269         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 270         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 271                 return 15; /* 16384 */
 272         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 273                 /* textures support 8192, but layered rendering supports 2048 */
 274                 return 12;
 275         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 276                 /* textures support 8192, but layered rendering supports 2048 */
 277                 return 2048;
 278
 279         /* Render targets. */
 280         case PIPE_CAP_MAX_RENDER_TARGETS:
 281                 return 8;
 282
 283         case PIPE_CAP_MAX_VIEWPORTS:
 284                 return 1;
 285
 286         /* Timer queries, present when the clock frequency is non zero. */
 287         case PIPE_CAP_QUERY_TIMESTAMP:
 288         case PIPE_CAP_QUERY_TIME_ELAPSED:
 289                 return sscreen->b.info.r600_clock_crystal_freq != 0;
 290
 291         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 292         case PIPE_CAP_MIN_TEXEL_OFFSET:
 293                 return -8;
 294
 295         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 296         case PIPE_CAP_MAX_TEXEL_OFFSET:
 297                 return 7;
 298         case PIPE_CAP_ENDIANNESS:
 299                 return PIPE_ENDIAN_LITTLE;
 300         }
 301         return 0;
 302 }
 303
 304 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 305 {
 306         switch(shader)
 307         {
 308         case PIPE_SHADER_FRAGMENT:
 309         case PIPE_SHADER_VERTEX:
 310                 break;
 311         case PIPE_SHADER_GEOMETRY:
 312 #if HAVE_LLVM < 0x0305
 313                 return 0;
 314 #endif
 315                 break;
 316         case PIPE_SHADER_COMPUTE:
 317                 switch (param) {
 318                 case PIPE_SHADER_CAP_PREFERRED_IR:
 319                         return PIPE_SHADER_IR_LLVM;
 320                 default:
 321                         return 0;
 322                 }
 323         default:
 324                 /* TODO: support tessellation */
 325                 return 0;
 326         }
 327
 328         switch (param) {
 329         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 330         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 331         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 332         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 333                 return 16384;
 334         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 335                 return 32;
 336         case PIPE_SHADER_CAP_MAX_INPUTS:
 337                 return 32;
 338         case PIPE_SHADER_CAP_MAX_TEMPS:
 339                 return 256; /* Max native temporaries. */
 340         case PIPE_SHADER_CAP_MAX_ADDRS:
 341                 /* FIXME Isn't this equal to TEMPS? */
 342                 return 1; /* Max native address registers */
 343         case PIPE_SHADER_CAP_MAX_CONSTS:
 344                 return 4096; /* actually only memory limits this */
 345         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 346                 return NUM_PIPE_CONST_BUFFERS;
 347         case PIPE_SHADER_CAP_MAX_PREDS:
 348                 return 0; /* FIXME */
 349         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 350                 return 1;
 351         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 352                 return 0;
 353         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 354                 /* Indirection of geometry shader input dimension is not
 355                  * handled yet
 356                  */
 357                 return shader < PIPE_SHADER_GEOMETRY;
 358         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 359         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 360         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 361                 return 1;
 362         case PIPE_SHADER_CAP_INTEGERS:
 363                 return 1;
 364         case PIPE_SHADER_CAP_SUBROUTINES:
 365                 return 0;
 366         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 367         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 368                 return 16;
 369         case PIPE_SHADER_CAP_PREFERRED_IR:
 370                 return PIPE_SHADER_IR_TGSI;
 371         }
 372         return 0;
 373 }
 374
 375 static void si_destroy_screen(struct pipe_screen* pscreen)
 376 {
 377         struct si_screen *sscreen = (struct si_screen *)pscreen;
 378
 379         if (sscreen == NULL)
 380                 return;
 381
 382         if (!sscreen->b.ws->unref(sscreen->b.ws))
 383                 return;
 384
 385         r600_destroy_common_screen(&sscreen->b);
 386 }
 387
 388 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 389 {
 390         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 391         if (sscreen == NULL) {
 392                 return NULL;
 393         }
 394
 395         /* Set functions first. */
 396         sscreen->b.b.context_create = si_create_context;
 397         sscreen->b.b.destroy = si_destroy_screen;
 398         sscreen->b.b.get_param = si_get_param;
 399         sscreen->b.b.get_shader_param = si_get_shader_param;
 400         sscreen->b.b.is_format_supported = si_is_format_supported;
 401         sscreen->b.b.resource_create = r600_resource_create_common;
 402
 403         if (!r600_common_screen_init(&sscreen->b, ws)) {
 404                 FREE(sscreen);
 405                 return NULL;
 406         }
 407
 408         sscreen->b.has_cp_dma = true;
 409         sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
 410
 411         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 412                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 413
 414         /* Create the auxiliary context. This must be done last. */
 415         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 416
 417         return &sscreen->b.b;
 418 }