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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_tests.h"
35 #include "util/xmlconfig.h"
36 #include "vl/vl_decoder.h"
37 #include "../ddebug/dd_util.h"
38
39 #include "compiler/nir/nir.h"
40
41 /*
42 * pipe_context
43 */
44 static void si_destroy_context(struct pipe_context *context)
45 {
46 struct si_context *sctx = (struct si_context *)context;
47 int i;
48
49 /* Unreference the framebuffer normally to disable related logic
50 * properly.
51 */
52 struct pipe_framebuffer_state fb = {};
53 if (context->set_framebuffer_state)
54 context->set_framebuffer_state(context, &fb);
55
56 si_release_all_descriptors(sctx);
57
58 pipe_resource_reference(&sctx->esgs_ring, NULL);
59 pipe_resource_reference(&sctx->gsvs_ring, NULL);
60 pipe_resource_reference(&sctx->tf_ring, NULL);
61 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
62 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
63 r600_resource_reference(&sctx->border_color_buffer, NULL);
64 free(sctx->border_color_table);
65 r600_resource_reference(&sctx->scratch_buffer, NULL);
66 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
67 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
68
69 si_pm4_free_state(sctx, sctx->init_config, ~0);
70 if (sctx->init_config_gs_rings)
71 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
72 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
73 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
74
75 if (sctx->fixed_func_tcs_shader.cso)
76 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
77 if (sctx->custom_dsa_flush)
78 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
79 if (sctx->custom_blend_resolve)
80 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
81 if (sctx->custom_blend_fmask_decompress)
82 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
83 if (sctx->custom_blend_eliminate_fastclear)
84 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
85 if (sctx->custom_blend_dcc_decompress)
86 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
87 if (sctx->vs_blit_pos)
88 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
89 if (sctx->vs_blit_pos_layered)
90 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
91 if (sctx->vs_blit_color)
92 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
93 if (sctx->vs_blit_color_layered)
94 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
95 if (sctx->vs_blit_texcoord)
96 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
97
98 if (sctx->blitter)
99 util_blitter_destroy(sctx->blitter);
100
101 si_common_context_cleanup(&sctx->b);
102
103 LLVMDisposeTargetMachine(sctx->tm);
104
105 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
106
107 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
108 _mesa_hash_table_destroy(sctx->img_handles, NULL);
109
110 util_dynarray_fini(&sctx->resident_tex_handles);
111 util_dynarray_fini(&sctx->resident_img_handles);
112 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
113 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
114 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
115 FREE(sctx);
116 }
117
118 static enum pipe_reset_status
119 si_amdgpu_get_reset_status(struct pipe_context *ctx)
120 {
121 struct si_context *sctx = (struct si_context *)ctx;
122
123 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
124 }
125
126 /* Apitrace profiling:
127 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
128 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
129 * and remember its number.
130 * 3) In Mesa, enable queries and performance counters around that draw
131 * call and print the results.
132 * 4) glretrace --benchmark --markers ..
133 */
134 static void si_emit_string_marker(struct pipe_context *ctx,
135 const char *string, int len)
136 {
137 struct si_context *sctx = (struct si_context *)ctx;
138
139 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
140
141 if (sctx->b.log)
142 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
143 }
144
145 static LLVMTargetMachineRef
146 si_create_llvm_target_machine(struct si_screen *sscreen)
147 {
148 enum ac_target_machine_options tm_options =
149 (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
150 (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
151 (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
152 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
153
154 return ac_create_target_machine(sscreen->b.family, tm_options);
155 }
156
157 static void si_set_debug_callback(struct pipe_context *ctx,
158 const struct pipe_debug_callback *cb)
159 {
160 struct si_context *sctx = (struct si_context *)ctx;
161 struct si_screen *screen = sctx->screen;
162
163 util_queue_finish(&screen->shader_compiler_queue);
164 util_queue_finish(&screen->shader_compiler_queue_low_priority);
165
166 if (cb)
167 sctx->debug = *cb;
168 else
169 memset(&sctx->debug, 0, sizeof(sctx->debug));
170 }
171
172 static void si_set_log_context(struct pipe_context *ctx,
173 struct u_log_context *log)
174 {
175 struct si_context *sctx = (struct si_context *)ctx;
176 sctx->b.log = log;
177
178 if (log)
179 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
180 }
181
182 static struct pipe_context *si_create_context(struct pipe_screen *screen,
183 unsigned flags)
184 {
185 struct si_context *sctx = CALLOC_STRUCT(si_context);
186 struct si_screen* sscreen = (struct si_screen *)screen;
187 struct radeon_winsys *ws = sscreen->b.ws;
188 int shader, i;
189
190 if (!sctx)
191 return NULL;
192
193 if (flags & PIPE_CONTEXT_DEBUG)
194 sscreen->record_llvm_ir = true; /* racy but not critical */
195
196 sctx->b.b.screen = screen; /* this must be set first */
197 sctx->b.b.priv = NULL;
198 sctx->b.b.destroy = si_destroy_context;
199 sctx->b.b.emit_string_marker = si_emit_string_marker;
200 sctx->b.b.set_debug_callback = si_set_debug_callback;
201 sctx->b.b.set_log_context = si_set_log_context;
202 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
203 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
204 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
205
206 if (!si_common_context_init(&sctx->b, &sscreen->b, flags))
207 goto fail;
208
209 if (sscreen->b.info.drm_major == 3)
210 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
211
212 si_init_blit_functions(sctx);
213 si_init_compute_functions(sctx);
214 si_init_cp_dma_functions(sctx);
215 si_init_debug_functions(sctx);
216 si_init_msaa_functions(sctx);
217 si_init_streamout_functions(sctx);
218
219 if (sscreen->b.info.has_hw_decode) {
220 sctx->b.b.create_video_codec = si_uvd_create_decoder;
221 sctx->b.b.create_video_buffer = si_video_buffer_create;
222 } else {
223 sctx->b.b.create_video_codec = vl_create_decoder;
224 sctx->b.b.create_video_buffer = vl_video_buffer_create;
225 }
226
227 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
228 si_context_gfx_flush, sctx);
229 sctx->b.gfx.flush = si_context_gfx_flush;
230
231 /* Border colors. */
232 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
233 sizeof(*sctx->border_color_table));
234 if (!sctx->border_color_table)
235 goto fail;
236
237 sctx->border_color_buffer = (struct r600_resource*)
238 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
239 SI_MAX_BORDER_COLORS *
240 sizeof(*sctx->border_color_table));
241 if (!sctx->border_color_buffer)
242 goto fail;
243
244 sctx->border_color_map =
245 ws->buffer_map(sctx->border_color_buffer->buf,
246 NULL, PIPE_TRANSFER_WRITE);
247 if (!sctx->border_color_map)
248 goto fail;
249
250 si_init_all_descriptors(sctx);
251 si_init_fence_functions(sctx);
252 si_init_state_functions(sctx);
253 si_init_shader_functions(sctx);
254 si_init_viewport_functions(sctx);
255 si_init_ia_multi_vgt_param_table(sctx);
256
257 if (sctx->b.chip_class >= CIK)
258 cik_init_sdma_functions(sctx);
259 else
260 si_init_dma_functions(sctx);
261
262 if (sscreen->b.debug_flags & DBG(FORCE_DMA))
263 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
264
265 sctx->blitter = util_blitter_create(&sctx->b.b);
266 if (sctx->blitter == NULL)
267 goto fail;
268 sctx->blitter->draw_rectangle = si_draw_rectangle;
269 sctx->blitter->skip_viewport_restore = true;
270
271 sctx->sample_mask.sample_mask = 0xffff;
272
273 /* these must be last */
274 si_begin_new_cs(sctx);
275
276 if (sctx->b.chip_class >= GFX9) {
277 sctx->wait_mem_scratch = (struct r600_resource*)
278 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
279 if (!sctx->wait_mem_scratch)
280 goto fail;
281
282 /* Initialize the memory. */
283 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
284 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
285 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
286 S_370_WR_CONFIRM(1) |
287 S_370_ENGINE_SEL(V_370_ME));
288 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
289 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
290 radeon_emit(cs, sctx->wait_mem_number);
291 }
292
293 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
294 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
295 if (sctx->b.chip_class == CIK) {
296 sctx->null_const_buf.buffer =
297 si_aligned_buffer_create(screen,
298 R600_RESOURCE_FLAG_UNMAPPABLE,
299 PIPE_USAGE_DEFAULT, 16,
300 sctx->screen->b.info.tcc_cache_line_size);
301 if (!sctx->null_const_buf.buffer)
302 goto fail;
303 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
304
305 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
306 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
307 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
308 &sctx->null_const_buf);
309 }
310 }
311
312 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
313 &sctx->null_const_buf);
314 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
315 &sctx->null_const_buf);
316 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
317 &sctx->null_const_buf);
318 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
319 &sctx->null_const_buf);
320 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
321 &sctx->null_const_buf);
322
323 /* Clear the NULL constant buffer, because loads should return zeros. */
324 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
325 sctx->null_const_buf.buffer->width0, 0,
326 R600_COHERENCY_SHADER);
327 }
328
329 uint64_t max_threads_per_block;
330 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
331 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
332 &max_threads_per_block);
333
334 /* The maximum number of scratch waves. Scratch space isn't divided
335 * evenly between CUs. The number is only a function of the number of CUs.
336 * We can decrease the constant to decrease the scratch buffer size.
337 *
338 * sctx->scratch_waves must be >= the maximum posible size of
339 * 1 threadgroup, so that the hw doesn't hang from being unable
340 * to start any.
341 *
342 * The recommended value is 4 per CU at most. Higher numbers don't
343 * bring much benefit, but they still occupy chip resources (think
344 * async compute). I've seen ~2% performance difference between 4 and 32.
345 */
346 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
347 max_threads_per_block / 64);
348
349 sctx->tm = si_create_llvm_target_machine(sscreen);
350
351 /* Bindless handles. */
352 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
353 _mesa_key_pointer_equal);
354 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
355 _mesa_key_pointer_equal);
356
357 util_dynarray_init(&sctx->resident_tex_handles, NULL);
358 util_dynarray_init(&sctx->resident_img_handles, NULL);
359 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
360 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
361 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
362
363 return &sctx->b.b;
364 fail:
365 fprintf(stderr, "radeonsi: Failed to create a context.\n");
366 si_destroy_context(&sctx->b.b);
367 return NULL;
368 }
369
370 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
371 void *priv, unsigned flags)
372 {
373 struct si_screen *sscreen = (struct si_screen *)screen;
374 struct pipe_context *ctx;
375
376 if (sscreen->b.debug_flags & DBG(CHECK_VM))
377 flags |= PIPE_CONTEXT_DEBUG;
378
379 ctx = si_create_context(screen, flags);
380
381 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
382 return ctx;
383
384 /* Clover (compute-only) is unsupported.
385 *
386 * Since the threaded context creates shader states from the non-driver
387 * thread, asynchronous compilation is required for create_{shader}_-
388 * state not to use pipe_context. Debug contexts (ddebug) disable
389 * asynchronous compilation, so don't use the threaded context with
390 * those.
391 */
392 if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
393 return ctx;
394
395 /* When shaders are logged to stderr, asynchronous compilation is
396 * disabled too. */
397 if (sscreen->b.debug_flags & DBG_ALL_SHADERS)
398 return ctx;
399
400 /* Use asynchronous flushes only on amdgpu, since the radeon
401 * implementation for fence_server_sync is incomplete. */
402 return threaded_context_create(ctx, &sscreen->b.pool_transfers,
403 si_replace_buffer_storage,
404 sscreen->b.info.drm_major >= 3 ? si_create_fence : NULL,
405 &((struct si_context*)ctx)->b.tc);
406 }
407
408 /*
409 * pipe_screen
410 */
411 static bool si_have_tgsi_compute(struct si_screen *sscreen)
412 {
413 /* Old kernels disallowed some register writes for SI
414 * that are used for indirect dispatches. */
415 return (sscreen->b.chip_class >= CIK ||
416 sscreen->b.info.drm_major == 3 ||
417 (sscreen->b.info.drm_major == 2 &&
418 sscreen->b.info.drm_minor >= 45));
419 }
420
421 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
422 {
423 struct si_screen *sscreen = (struct si_screen *)pscreen;
424
425 switch (param) {
426 /* Supported features (boolean caps). */
427 case PIPE_CAP_ACCELERATED:
428 case PIPE_CAP_TWO_SIDED_STENCIL:
429 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
430 case PIPE_CAP_ANISOTROPIC_FILTER:
431 case PIPE_CAP_POINT_SPRITE:
432 case PIPE_CAP_OCCLUSION_QUERY:
433 case PIPE_CAP_TEXTURE_SHADOW_MAP:
434 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
435 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
436 case PIPE_CAP_TEXTURE_SWIZZLE:
437 case PIPE_CAP_DEPTH_CLIP_DISABLE:
438 case PIPE_CAP_SHADER_STENCIL_EXPORT:
439 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
440 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
441 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
442 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
443 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
444 case PIPE_CAP_SM3:
445 case PIPE_CAP_SEAMLESS_CUBE_MAP:
446 case PIPE_CAP_PRIMITIVE_RESTART:
447 case PIPE_CAP_CONDITIONAL_RENDER:
448 case PIPE_CAP_TEXTURE_BARRIER:
449 case PIPE_CAP_INDEP_BLEND_ENABLE:
450 case PIPE_CAP_INDEP_BLEND_FUNC:
451 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
452 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
453 case PIPE_CAP_USER_CONSTANT_BUFFERS:
454 case PIPE_CAP_START_INSTANCE:
455 case PIPE_CAP_NPOT_TEXTURES:
456 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
457 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
458 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
459 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
460 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
461 case PIPE_CAP_TGSI_INSTANCEID:
462 case PIPE_CAP_COMPUTE:
463 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
464 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
465 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
466 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
467 case PIPE_CAP_CUBE_MAP_ARRAY:
468 case PIPE_CAP_SAMPLE_SHADING:
469 case PIPE_CAP_DRAW_INDIRECT:
470 case PIPE_CAP_CLIP_HALFZ:
471 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
472 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
473 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
474 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
475 case PIPE_CAP_TGSI_TEXCOORD:
476 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
477 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
478 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
479 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
480 case PIPE_CAP_SHAREABLE_SHADERS:
481 case PIPE_CAP_DEPTH_BOUNDS_TEST:
482 case PIPE_CAP_SAMPLER_VIEW_TARGET:
483 case PIPE_CAP_TEXTURE_QUERY_LOD:
484 case PIPE_CAP_TEXTURE_GATHER_SM5:
485 case PIPE_CAP_TGSI_TXQS:
486 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
487 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
488 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
489 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
490 case PIPE_CAP_INVALIDATE_BUFFER:
491 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
492 case PIPE_CAP_QUERY_MEMORY_INFO:
493 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
494 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
495 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
496 case PIPE_CAP_GENERATE_MIPMAP:
497 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
498 case PIPE_CAP_STRING_MARKER:
499 case PIPE_CAP_CLEAR_TEXTURE:
500 case PIPE_CAP_CULL_DISTANCE:
501 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
502 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
503 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
504 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
505 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
506 case PIPE_CAP_DOUBLES:
507 case PIPE_CAP_TGSI_TEX_TXF_LZ:
508 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
509 case PIPE_CAP_BINDLESS_TEXTURE:
510 case PIPE_CAP_QUERY_TIMESTAMP:
511 case PIPE_CAP_QUERY_TIME_ELAPSED:
512 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
513 case PIPE_CAP_QUERY_SO_OVERFLOW:
514 case PIPE_CAP_MEMOBJ:
515 case PIPE_CAP_LOAD_CONSTBUF:
516 case PIPE_CAP_INT64:
517 case PIPE_CAP_INT64_DIVMOD:
518 case PIPE_CAP_TGSI_CLOCK:
519 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
520 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
521 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
522 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
523 return 1;
524
525 case PIPE_CAP_TGSI_VOTE:
526 return HAVE_LLVM >= 0x0400;
527
528 case PIPE_CAP_TGSI_BALLOT:
529 return HAVE_LLVM >= 0x0500;
530
531 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
532 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
533
534 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
535 return (sscreen->b.info.drm_major == 2 &&
536 sscreen->b.info.drm_minor >= 43) ||
537 sscreen->b.info.drm_major == 3;
538
539 case PIPE_CAP_TEXTURE_MULTISAMPLE:
540 /* 2D tiling on CIK is supported since DRM 2.35.0 */
541 return sscreen->b.chip_class < CIK ||
542 (sscreen->b.info.drm_major == 2 &&
543 sscreen->b.info.drm_minor >= 35) ||
544 sscreen->b.info.drm_major == 3;
545
546 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
547 return R600_MAP_BUFFER_ALIGNMENT;
548
549 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
550 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
551 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
552 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
553 case PIPE_CAP_MAX_VERTEX_STREAMS:
554 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
555 return 4;
556
557 case PIPE_CAP_GLSL_FEATURE_LEVEL:
558 if (sscreen->b.debug_flags & DBG(NIR))
559 return 140; /* no geometry and tessellation shaders yet */
560 if (si_have_tgsi_compute(sscreen))
561 return 450;
562 return 420;
563
564 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
565 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
566
567 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
568 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
569 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
570 /* SI doesn't support unaligned loads.
571 * CIK needs DRM 2.50.0 on radeon. */
572 return sscreen->b.chip_class == SI ||
573 (sscreen->b.info.drm_major == 2 &&
574 sscreen->b.info.drm_minor < 50);
575
576 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
577 /* TODO: GFX9 hangs. */
578 if (sscreen->b.chip_class >= GFX9)
579 return 0;
580 /* Disable on SI due to VM faults in CP DMA. Enable once these
581 * faults are mitigated in software.
582 */
583 if (sscreen->b.chip_class >= CIK &&
584 sscreen->b.info.drm_major == 3 &&
585 sscreen->b.info.drm_minor >= 13)
586 return RADEON_SPARSE_PAGE_SIZE;
587 return 0;
588
589 /* Unsupported features. */
590 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
591 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
592 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
593 case PIPE_CAP_USER_VERTEX_BUFFERS:
594 case PIPE_CAP_FAKE_SW_MSAA:
595 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
596 case PIPE_CAP_VERTEXID_NOBASE:
597 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
598 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
599 case PIPE_CAP_TGSI_FS_FBFETCH:
600 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
601 case PIPE_CAP_UMA:
602 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
603 case PIPE_CAP_POST_DEPTH_COVERAGE:
604 case PIPE_CAP_TILE_RASTER_ORDER:
605 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
606 return 0;
607
608 case PIPE_CAP_NATIVE_FENCE_FD:
609 return sscreen->b.info.has_sync_file;
610
611 case PIPE_CAP_QUERY_BUFFER_OBJECT:
612 return si_have_tgsi_compute(sscreen);
613
614 case PIPE_CAP_DRAW_PARAMETERS:
615 case PIPE_CAP_MULTI_DRAW_INDIRECT:
616 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
617 return sscreen->has_draw_indirect_multi;
618
619 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
620 return 30;
621
622 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
623 return sscreen->b.chip_class <= VI ?
624 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
625
626 /* Stream output. */
627 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
628 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
629 return 32*4;
630
631 /* Geometry shader output. */
632 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
633 return 1024;
634 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
635 return 4095;
636
637 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
638 return 2048;
639
640 /* Texturing. */
641 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
642 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
643 return 15; /* 16384 */
644 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
645 /* textures support 8192, but layered rendering supports 2048 */
646 return 12;
647 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
648 /* textures support 8192, but layered rendering supports 2048 */
649 return 2048;
650
651 /* Viewports and render targets. */
652 case PIPE_CAP_MAX_VIEWPORTS:
653 return SI_MAX_VIEWPORTS;
654 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
655 case PIPE_CAP_MAX_RENDER_TARGETS:
656 return 8;
657
658 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
659 case PIPE_CAP_MIN_TEXEL_OFFSET:
660 return -32;
661
662 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
663 case PIPE_CAP_MAX_TEXEL_OFFSET:
664 return 31;
665
666 case PIPE_CAP_ENDIANNESS:
667 return PIPE_ENDIAN_LITTLE;
668
669 case PIPE_CAP_VENDOR_ID:
670 return ATI_VENDOR_ID;
671 case PIPE_CAP_DEVICE_ID:
672 return sscreen->b.info.pci_id;
673 case PIPE_CAP_VIDEO_MEMORY:
674 return sscreen->b.info.vram_size >> 20;
675 case PIPE_CAP_PCI_GROUP:
676 return sscreen->b.info.pci_domain;
677 case PIPE_CAP_PCI_BUS:
678 return sscreen->b.info.pci_bus;
679 case PIPE_CAP_PCI_DEVICE:
680 return sscreen->b.info.pci_dev;
681 case PIPE_CAP_PCI_FUNCTION:
682 return sscreen->b.info.pci_func;
683 }
684 return 0;
685 }
686
687 static int si_get_shader_param(struct pipe_screen* pscreen,
688 enum pipe_shader_type shader,
689 enum pipe_shader_cap param)
690 {
691 struct si_screen *sscreen = (struct si_screen *)pscreen;
692
693 switch(shader)
694 {
695 case PIPE_SHADER_FRAGMENT:
696 case PIPE_SHADER_VERTEX:
697 case PIPE_SHADER_GEOMETRY:
698 case PIPE_SHADER_TESS_CTRL:
699 case PIPE_SHADER_TESS_EVAL:
700 break;
701 case PIPE_SHADER_COMPUTE:
702 switch (param) {
703 case PIPE_SHADER_CAP_PREFERRED_IR:
704 return PIPE_SHADER_IR_NATIVE;
705
706 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
707 int ir = 1 << PIPE_SHADER_IR_NATIVE;
708
709 if (si_have_tgsi_compute(sscreen))
710 ir |= 1 << PIPE_SHADER_IR_TGSI;
711
712 return ir;
713 }
714
715 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
716 uint64_t max_const_buffer_size;
717 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
718 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
719 &max_const_buffer_size);
720 return MIN2(max_const_buffer_size, INT_MAX);
721 }
722 default:
723 /* If compute shaders don't require a special value
724 * for this cap, we can return the same value we
725 * do for other shader types. */
726 break;
727 }
728 break;
729 default:
730 return 0;
731 }
732
733 switch (param) {
734 /* Shader limits. */
735 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
736 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
737 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
738 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
739 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
740 return 16384;
741 case PIPE_SHADER_CAP_MAX_INPUTS:
742 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
743 case PIPE_SHADER_CAP_MAX_OUTPUTS:
744 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
745 case PIPE_SHADER_CAP_MAX_TEMPS:
746 return 256; /* Max native temporaries. */
747 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
748 return 4096 * sizeof(float[4]); /* actually only memory limits this */
749 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
750 return SI_NUM_CONST_BUFFERS;
751 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
752 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
753 return SI_NUM_SAMPLERS;
754 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
755 return SI_NUM_SHADER_BUFFERS;
756 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
757 return SI_NUM_IMAGES;
758 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
759 return 32;
760 case PIPE_SHADER_CAP_PREFERRED_IR:
761 if (sscreen->b.debug_flags & DBG(NIR) &&
762 (shader == PIPE_SHADER_VERTEX ||
763 shader == PIPE_SHADER_FRAGMENT))
764 return PIPE_SHADER_IR_NIR;
765 return PIPE_SHADER_IR_TGSI;
766 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
767 return 4;
768
769 /* Supported boolean features. */
770 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
771 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
772 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
773 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
774 case PIPE_SHADER_CAP_INTEGERS:
775 case PIPE_SHADER_CAP_INT64_ATOMICS:
776 case PIPE_SHADER_CAP_FP16:
777 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
778 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
779 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
780 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
781 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
782 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
783 return 1;
784
785 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
786 /* TODO: Indirect indexing of GS inputs is unimplemented. */
787 return shader != PIPE_SHADER_GEOMETRY &&
788 (sscreen->llvm_has_working_vgpr_indexing ||
789 /* TCS and TES load inputs directly from LDS or
790 * offchip memory, so indirect indexing is trivial. */
791 shader == PIPE_SHADER_TESS_CTRL ||
792 shader == PIPE_SHADER_TESS_EVAL);
793
794 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
795 return sscreen->llvm_has_working_vgpr_indexing ||
796 /* TCS stores outputs directly to memory. */
797 shader == PIPE_SHADER_TESS_CTRL;
798
799 /* Unsupported boolean features. */
800 case PIPE_SHADER_CAP_SUBROUTINES:
801 case PIPE_SHADER_CAP_SUPPORTED_IRS:
802 return 0;
803 }
804 return 0;
805 }
806
807 static const struct nir_shader_compiler_options nir_options = {
808 .vertex_id_zero_based = true,
809 .lower_scmp = true,
810 .lower_flrp32 = true,
811 .lower_fsat = true,
812 .lower_fdiv = true,
813 .lower_sub = true,
814 .lower_ffma = true,
815 .lower_pack_snorm_2x16 = true,
816 .lower_pack_snorm_4x8 = true,
817 .lower_pack_unorm_2x16 = true,
818 .lower_pack_unorm_4x8 = true,
819 .lower_unpack_snorm_2x16 = true,
820 .lower_unpack_snorm_4x8 = true,
821 .lower_unpack_unorm_2x16 = true,
822 .lower_unpack_unorm_4x8 = true,
823 .lower_extract_byte = true,
824 .lower_extract_word = true,
825 .max_unroll_iterations = 32,
826 .native_integers = true,
827 };
828
829 static const void *
830 si_get_compiler_options(struct pipe_screen *screen,
831 enum pipe_shader_ir ir,
832 enum pipe_shader_type shader)
833 {
834 assert(ir == PIPE_SHADER_IR_NIR);
835 return &nir_options;
836 }
837
838 static void si_destroy_screen(struct pipe_screen* pscreen)
839 {
840 struct si_screen *sscreen = (struct si_screen *)pscreen;
841 struct si_shader_part *parts[] = {
842 sscreen->vs_prologs,
843 sscreen->tcs_epilogs,
844 sscreen->gs_prologs,
845 sscreen->ps_prologs,
846 sscreen->ps_epilogs
847 };
848 unsigned i;
849
850 if (!sscreen->b.ws->unref(sscreen->b.ws))
851 return;
852
853 util_queue_destroy(&sscreen->shader_compiler_queue);
854 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
855
856 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
857 if (sscreen->tm[i])
858 LLVMDisposeTargetMachine(sscreen->tm[i]);
859
860 for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
861 if (sscreen->tm_low_priority[i])
862 LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
863
864 /* Free shader parts. */
865 for (i = 0; i < ARRAY_SIZE(parts); i++) {
866 while (parts[i]) {
867 struct si_shader_part *part = parts[i];
868
869 parts[i] = part->next;
870 si_radeon_shader_binary_clean(&part->binary);
871 FREE(part);
872 }
873 }
874 mtx_destroy(&sscreen->shader_parts_mutex);
875 si_destroy_shader_cache(sscreen);
876 si_destroy_common_screen(&sscreen->b);
877 }
878
879 static bool si_init_gs_info(struct si_screen *sscreen)
880 {
881 /* gs_table_depth is not used by GFX9 */
882 if (sscreen->b.chip_class >= GFX9)
883 return true;
884
885 switch (sscreen->b.family) {
886 case CHIP_OLAND:
887 case CHIP_HAINAN:
888 case CHIP_KAVERI:
889 case CHIP_KABINI:
890 case CHIP_MULLINS:
891 case CHIP_ICELAND:
892 case CHIP_CARRIZO:
893 case CHIP_STONEY:
894 sscreen->gs_table_depth = 16;
895 return true;
896 case CHIP_TAHITI:
897 case CHIP_PITCAIRN:
898 case CHIP_VERDE:
899 case CHIP_BONAIRE:
900 case CHIP_HAWAII:
901 case CHIP_TONGA:
902 case CHIP_FIJI:
903 case CHIP_POLARIS10:
904 case CHIP_POLARIS11:
905 case CHIP_POLARIS12:
906 sscreen->gs_table_depth = 32;
907 return true;
908 default:
909 return false;
910 }
911 }
912
913 static void si_handle_env_var_force_family(struct si_screen *sscreen)
914 {
915 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
916 unsigned i;
917
918 if (!family)
919 return;
920
921 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
922 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
923 /* Override family and chip_class. */
924 sscreen->b.family = sscreen->b.info.family = i;
925
926 if (i >= CHIP_VEGA10)
927 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
928 else if (i >= CHIP_TONGA)
929 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
930 else if (i >= CHIP_BONAIRE)
931 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
932 else
933 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
934
935 /* Don't submit any IBs. */
936 setenv("RADEON_NOOP", "1", 1);
937 return;
938 }
939 }
940
941 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
942 exit(1);
943 }
944
945 static void si_test_vmfault(struct si_screen *sscreen)
946 {
947 struct pipe_context *ctx = sscreen->b.aux_context;
948 struct si_context *sctx = (struct si_context *)ctx;
949 struct pipe_resource *buf =
950 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
951
952 if (!buf) {
953 puts("Buffer allocation failed.");
954 exit(1);
955 }
956
957 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
958
959 if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_CP)) {
960 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
961 ctx->flush(ctx, NULL, 0);
962 puts("VM fault test: CP - done.");
963 }
964 if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SDMA)) {
965 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
966 ctx->flush(ctx, NULL, 0);
967 puts("VM fault test: SDMA - done.");
968 }
969 if (sscreen->b.debug_flags & DBG(TEST_VMFAULT_SHADER)) {
970 util_test_constant_buffer(ctx, buf);
971 puts("VM fault test: Shader - done.");
972 }
973 exit(0);
974 }
975
976 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
977 {
978 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
979 }
980
981 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
982 {
983 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
984
985 ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
986 }
987
988 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
989 const struct pipe_screen_config *config)
990 {
991 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
992 unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
993
994 if (!sscreen) {
995 return NULL;
996 }
997
998 /* Set functions first. */
999 sscreen->b.b.context_create = si_pipe_create_context;
1000 sscreen->b.b.destroy = si_destroy_screen;
1001 sscreen->b.b.get_param = si_get_param;
1002 sscreen->b.b.get_shader_param = si_get_shader_param;
1003 sscreen->b.b.get_compiler_options = si_get_compiler_options;
1004 sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
1005 sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
1006 sscreen->b.b.resource_create = si_resource_create_common;
1007
1008 si_init_screen_fence_functions(sscreen);
1009 si_init_screen_state_functions(sscreen);
1010
1011 /* Set these flags in debug_flags early, so that the shader cache takes
1012 * them into account.
1013 */
1014 if (driQueryOptionb(config->options,
1015 "glsl_correct_derivatives_after_discard"))
1016 sscreen->b.debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1017 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1018 sscreen->b.debug_flags |= DBG(SI_SCHED);
1019
1020 if (!si_common_screen_init(&sscreen->b, ws) ||
1021 !si_init_gs_info(sscreen) ||
1022 !si_init_shader_cache(sscreen)) {
1023 FREE(sscreen);
1024 return NULL;
1025 }
1026
1027 /* Only enable as many threads as we have target machines, but at most
1028 * the number of CPUs - 1 if there is more than one.
1029 */
1030 num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1031 num_threads = MAX2(1, num_threads - 1);
1032 num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1033 num_compiler_threads_lowprio =
1034 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1035
1036 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1037 32, num_compiler_threads,
1038 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1039 si_destroy_shader_cache(sscreen);
1040 FREE(sscreen);
1041 return NULL;
1042 }
1043
1044 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1045 "si_shader_low",
1046 32, num_compiler_threads_lowprio,
1047 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1048 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1049 si_destroy_shader_cache(sscreen);
1050 FREE(sscreen);
1051 return NULL;
1052 }
1053
1054 si_handle_env_var_force_family(sscreen);
1055
1056 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1057 si_init_perfcounters(sscreen);
1058
1059 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1060 * around by setting 4K granularity.
1061 */
1062 sscreen->tess_offchip_block_dw_size =
1063 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1064
1065 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1066 * on SI. */
1067 sscreen->has_clear_state = sscreen->b.chip_class >= CIK;
1068
1069 sscreen->has_distributed_tess =
1070 sscreen->b.chip_class >= VI &&
1071 sscreen->b.info.max_se >= 2;
1072
1073 sscreen->has_draw_indirect_multi =
1074 (sscreen->b.family >= CHIP_POLARIS10) ||
1075 (sscreen->b.chip_class == VI &&
1076 sscreen->b.info.pfp_fw_version >= 121 &&
1077 sscreen->b.info.me_fw_version >= 87) ||
1078 (sscreen->b.chip_class == CIK &&
1079 sscreen->b.info.pfp_fw_version >= 211 &&
1080 sscreen->b.info.me_fw_version >= 173) ||
1081 (sscreen->b.chip_class == SI &&
1082 sscreen->b.info.pfp_fw_version >= 79 &&
1083 sscreen->b.info.me_fw_version >= 142);
1084
1085 sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
1086 sscreen->b.info.max_se >= 2 &&
1087 !(sscreen->b.debug_flags & DBG(NO_OUT_OF_ORDER));
1088 sscreen->assume_no_z_fights =
1089 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1090 sscreen->commutative_blend_add =
1091 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1092 sscreen->clear_db_cache_before_clear =
1093 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1094 sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1095 sscreen->b.family <= CHIP_POLARIS12) ||
1096 sscreen->b.family == CHIP_VEGA10 ||
1097 sscreen->b.family == CHIP_RAVEN;
1098 sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
1099 sscreen->b.family == CHIP_RAVEN;
1100
1101 if (sscreen->b.debug_flags & DBG(DPBB)) {
1102 sscreen->dpbb_allowed = true;
1103 } else {
1104 /* Only enable primitive binning on Raven by default. */
1105 sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
1106 !(sscreen->b.debug_flags & DBG(NO_DPBB));
1107 }
1108
1109 if (sscreen->b.debug_flags & DBG(DFSM)) {
1110 sscreen->dfsm_allowed = sscreen->dpbb_allowed;
1111 } else {
1112 sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
1113 !(sscreen->b.debug_flags & DBG(NO_DFSM));
1114 }
1115
1116 /* While it would be nice not to have this flag, we are constrained
1117 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1118 * on GFX9.
1119 */
1120 sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1121
1122 sscreen->b.has_cp_dma = true;
1123 sscreen->b.has_streamout = true;
1124
1125 /* Some chips have RB+ registers, but don't support RB+. Those must
1126 * always disable it.
1127 */
1128 if (sscreen->b.family == CHIP_STONEY ||
1129 sscreen->b.chip_class >= GFX9) {
1130 sscreen->b.has_rbplus = true;
1131
1132 sscreen->b.rbplus_allowed =
1133 !(sscreen->b.debug_flags & DBG(NO_RB_PLUS)) &&
1134 (sscreen->b.family == CHIP_STONEY ||
1135 sscreen->b.family == CHIP_RAVEN);
1136 }
1137
1138 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1139 sscreen->use_monolithic_shaders =
1140 (sscreen->b.debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1141
1142 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1143 SI_CONTEXT_INV_VMEM_L1;
1144 if (sscreen->b.chip_class <= VI) {
1145 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1146 sscreen->b.barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1147 }
1148
1149 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1150
1151 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1152 sscreen->b.debug_flags |= DBG_ALL_SHADERS;
1153
1154 for (i = 0; i < num_compiler_threads; i++)
1155 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1156 for (i = 0; i < num_compiler_threads_lowprio; i++)
1157 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1158
1159 /* Create the auxiliary context. This must be done last. */
1160 sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1161
1162 if (sscreen->b.debug_flags & DBG(TEST_DMA))
1163 si_test_dma(&sscreen->b);
1164
1165 if (sscreen->b.debug_flags & (DBG(TEST_VMFAULT_CP) |
1166 DBG(TEST_VMFAULT_SDMA) |
1167 DBG(TEST_VMFAULT_SHADER)))
1168 si_test_vmfault(sscreen);
1169
1170 return &sscreen->b.b;
1171 }