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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_public.h"
26 #include "si_shader_internal.h"
27 #include "sid.h"
28
29 #include "radeon/radeon_uvd.h"
30 #include "util/hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_suballoc.h"
33 #include "util/u_tests.h"
34 #include "util/xmlconfig.h"
35 #include "vl/vl_decoder.h"
36 #include "../ddebug/dd_util.h"
37
38 #include "compiler/nir/nir.h"
39
40 /*
41 * pipe_context
42 */
43 static void si_destroy_context(struct pipe_context *context)
44 {
45 struct si_context *sctx = (struct si_context *)context;
46 int i;
47
48 /* Unreference the framebuffer normally to disable related logic
49 * properly.
50 */
51 struct pipe_framebuffer_state fb = {};
52 if (context->set_framebuffer_state)
53 context->set_framebuffer_state(context, &fb);
54
55 si_release_all_descriptors(sctx);
56
57 if (sctx->ce_suballocator)
58 u_suballocator_destroy(sctx->ce_suballocator);
59
60 r600_resource_reference(&sctx->ce_ram_saved_buffer, NULL);
61 pipe_resource_reference(&sctx->esgs_ring, NULL);
62 pipe_resource_reference(&sctx->gsvs_ring, NULL);
63 pipe_resource_reference(&sctx->tf_ring, NULL);
64 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
65 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
66 r600_resource_reference(&sctx->border_color_buffer, NULL);
67 free(sctx->border_color_table);
68 r600_resource_reference(&sctx->scratch_buffer, NULL);
69 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
70 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
71
72 si_pm4_free_state(sctx, sctx->init_config, ~0);
73 if (sctx->init_config_gs_rings)
74 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
75 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
76 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
77
78 if (sctx->fixed_func_tcs_shader.cso)
79 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
80 if (sctx->custom_dsa_flush)
81 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
82 if (sctx->custom_blend_resolve)
83 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
84 if (sctx->custom_blend_fmask_decompress)
85 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
86 if (sctx->custom_blend_eliminate_fastclear)
87 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
88 if (sctx->custom_blend_dcc_decompress)
89 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
90
91 if (sctx->blitter)
92 util_blitter_destroy(sctx->blitter);
93
94 r600_common_context_cleanup(&sctx->b);
95
96 LLVMDisposeTargetMachine(sctx->tm);
97
98 r600_resource_reference(&sctx->trace_buf, NULL);
99 r600_resource_reference(&sctx->last_trace_buf, NULL);
100 radeon_clear_saved_cs(&sctx->last_gfx);
101
102 pb_slabs_deinit(&sctx->bindless_descriptor_slabs);
103 util_dynarray_fini(&sctx->bindless_descriptors);
104
105 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
106 _mesa_hash_table_destroy(sctx->img_handles, NULL);
107
108 util_dynarray_fini(&sctx->resident_tex_handles);
109 util_dynarray_fini(&sctx->resident_img_handles);
110 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
111 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
112 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
113 FREE(sctx);
114 }
115
116 static enum pipe_reset_status
117 si_amdgpu_get_reset_status(struct pipe_context *ctx)
118 {
119 struct si_context *sctx = (struct si_context *)ctx;
120
121 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
122 }
123
124 /* Apitrace profiling:
125 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
126 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
127 * and remember its number.
128 * 3) In Mesa, enable queries and performance counters around that draw
129 * call and print the results.
130 * 4) glretrace --benchmark --markers ..
131 */
132 static void si_emit_string_marker(struct pipe_context *ctx,
133 const char *string, int len)
134 {
135 struct si_context *sctx = (struct si_context *)ctx;
136
137 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
138 }
139
140 static LLVMTargetMachineRef
141 si_create_llvm_target_machine(struct si_screen *sscreen)
142 {
143 const char *triple = "amdgcn--";
144 char features[256];
145
146 snprintf(features, sizeof(features),
147 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
148 sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
149 sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca",
150 sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : "");
151
152 return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
153 r600_get_llvm_processor_name(sscreen->b.family),
154 features,
155 LLVMCodeGenLevelDefault,
156 LLVMRelocDefault,
157 LLVMCodeModelDefault);
158 }
159
160 static struct pipe_context *si_create_context(struct pipe_screen *screen,
161 unsigned flags)
162 {
163 struct si_context *sctx = CALLOC_STRUCT(si_context);
164 struct si_screen* sscreen = (struct si_screen *)screen;
165 struct radeon_winsys *ws = sscreen->b.ws;
166 int shader, i;
167
168 if (!sctx)
169 return NULL;
170
171 if (flags & PIPE_CONTEXT_DEBUG)
172 sscreen->record_llvm_ir = true; /* racy but not critical */
173
174 sctx->b.b.screen = screen; /* this must be set first */
175 sctx->b.b.priv = NULL;
176 sctx->b.b.destroy = si_destroy_context;
177 sctx->b.b.emit_string_marker = si_emit_string_marker;
178 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
179 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
180 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
181
182 if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
183 goto fail;
184
185 if (sscreen->b.info.drm_major == 3)
186 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
187
188 si_init_blit_functions(sctx);
189 si_init_compute_functions(sctx);
190 si_init_cp_dma_functions(sctx);
191 si_init_debug_functions(sctx);
192
193 if (sscreen->b.info.has_hw_decode) {
194 sctx->b.b.create_video_codec = si_uvd_create_decoder;
195 sctx->b.b.create_video_buffer = si_video_buffer_create;
196 } else {
197 sctx->b.b.create_video_codec = vl_create_decoder;
198 sctx->b.b.create_video_buffer = vl_video_buffer_create;
199 }
200
201 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
202 si_context_gfx_flush, sctx);
203
204 /* SI + AMDGPU + CE = GPU hang */
205 if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
206 sscreen->b.chip_class != SI &&
207 /* These can't use CE due to a power gating bug in the kernel. */
208 sscreen->b.family != CHIP_CARRIZO &&
209 sscreen->b.family != CHIP_STONEY) {
210 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
211 if (!sctx->ce_ib)
212 goto fail;
213
214 if (ws->cs_add_const_preamble_ib) {
215 sctx->ce_preamble_ib =
216 ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
217
218 if (!sctx->ce_preamble_ib)
219 goto fail;
220 }
221
222 sctx->ce_suballocator =
223 u_suballocator_create(&sctx->b.b, 1024 * 1024, 0,
224 PIPE_USAGE_DEFAULT,
225 R600_RESOURCE_FLAG_UNMAPPABLE, false);
226 if (!sctx->ce_suballocator)
227 goto fail;
228 }
229
230 sctx->b.gfx.flush = si_context_gfx_flush;
231
232 /* Border colors. */
233 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
234 sizeof(*sctx->border_color_table));
235 if (!sctx->border_color_table)
236 goto fail;
237
238 sctx->border_color_buffer = (struct r600_resource*)
239 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
240 SI_MAX_BORDER_COLORS *
241 sizeof(*sctx->border_color_table));
242 if (!sctx->border_color_buffer)
243 goto fail;
244
245 sctx->border_color_map =
246 ws->buffer_map(sctx->border_color_buffer->buf,
247 NULL, PIPE_TRANSFER_WRITE);
248 if (!sctx->border_color_map)
249 goto fail;
250
251 si_init_all_descriptors(sctx);
252 si_init_state_functions(sctx);
253 si_init_shader_functions(sctx);
254 si_init_ia_multi_vgt_param_table(sctx);
255
256 if (sctx->b.chip_class >= CIK)
257 cik_init_sdma_functions(sctx);
258 else
259 si_init_dma_functions(sctx);
260
261 if (sscreen->b.debug_flags & DBG_FORCE_DMA)
262 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
263
264 sctx->blitter = util_blitter_create(&sctx->b.b);
265 if (sctx->blitter == NULL)
266 goto fail;
267 sctx->blitter->draw_rectangle = r600_draw_rectangle;
268
269 sctx->sample_mask.sample_mask = 0xffff;
270
271 /* these must be last */
272 si_begin_new_cs(sctx);
273
274 if (sctx->b.chip_class >= GFX9) {
275 sctx->wait_mem_scratch = (struct r600_resource*)
276 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
277 if (!sctx->wait_mem_scratch)
278 goto fail;
279
280 /* Initialize the memory. */
281 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
282 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
283 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
284 S_370_WR_CONFIRM(1) |
285 S_370_ENGINE_SEL(V_370_ME));
286 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
287 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
288 radeon_emit(cs, sctx->wait_mem_number);
289 }
290
291 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
292 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
293 if (sctx->b.chip_class == CIK) {
294 sctx->null_const_buf.buffer =
295 r600_aligned_buffer_create(screen,
296 R600_RESOURCE_FLAG_UNMAPPABLE,
297 PIPE_USAGE_DEFAULT, 16,
298 sctx->screen->b.info.tcc_cache_line_size);
299 if (!sctx->null_const_buf.buffer)
300 goto fail;
301 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
302
303 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
304 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
305 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
306 &sctx->null_const_buf);
307 }
308 }
309
310 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
311 &sctx->null_const_buf);
312 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
313 &sctx->null_const_buf);
314 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
315 &sctx->null_const_buf);
316 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
317 &sctx->null_const_buf);
318 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
319 &sctx->null_const_buf);
320
321 /* Clear the NULL constant buffer, because loads should return zeros. */
322 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
323 sctx->null_const_buf.buffer->width0, 0,
324 R600_COHERENCY_SHADER);
325 }
326
327 uint64_t max_threads_per_block;
328 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
329 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
330 &max_threads_per_block);
331
332 /* The maximum number of scratch waves. Scratch space isn't divided
333 * evenly between CUs. The number is only a function of the number of CUs.
334 * We can decrease the constant to decrease the scratch buffer size.
335 *
336 * sctx->scratch_waves must be >= the maximum posible size of
337 * 1 threadgroup, so that the hw doesn't hang from being unable
338 * to start any.
339 *
340 * The recommended value is 4 per CU at most. Higher numbers don't
341 * bring much benefit, but they still occupy chip resources (think
342 * async compute). I've seen ~2% performance difference between 4 and 32.
343 */
344 sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
345 max_threads_per_block / 64);
346
347 sctx->tm = si_create_llvm_target_machine(sscreen);
348
349 /* Create a slab allocator for all bindless descriptors. */
350 if (!pb_slabs_init(&sctx->bindless_descriptor_slabs, 6, 6, 1, sctx,
351 si_bindless_descriptor_can_reclaim_slab,
352 si_bindless_descriptor_slab_alloc,
353 si_bindless_descriptor_slab_free))
354 goto fail;
355
356 util_dynarray_init(&sctx->bindless_descriptors, NULL);
357
358 /* Bindless handles. */
359 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
360 _mesa_key_pointer_equal);
361 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
362 _mesa_key_pointer_equal);
363
364 util_dynarray_init(&sctx->resident_tex_handles, NULL);
365 util_dynarray_init(&sctx->resident_img_handles, NULL);
366 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
367 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
368 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
369
370 return &sctx->b.b;
371 fail:
372 fprintf(stderr, "radeonsi: Failed to create a context.\n");
373 si_destroy_context(&sctx->b.b);
374 return NULL;
375 }
376
377 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
378 void *priv, unsigned flags)
379 {
380 struct si_screen *sscreen = (struct si_screen *)screen;
381 struct pipe_context *ctx;
382
383 if (sscreen->b.debug_flags & DBG_CHECK_VM)
384 flags |= PIPE_CONTEXT_DEBUG;
385
386 ctx = si_create_context(screen, flags);
387
388 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
389 return ctx;
390
391 /* Clover (compute-only) is unsupported.
392 *
393 * Since the threaded context creates shader states from the non-driver
394 * thread, asynchronous compilation is required for create_{shader}_-
395 * state not to use pipe_context. Debug contexts (ddebug) disable
396 * asynchronous compilation, so don't use the threaded context with
397 * those.
398 */
399 if (flags & (PIPE_CONTEXT_COMPUTE_ONLY | PIPE_CONTEXT_DEBUG))
400 return ctx;
401
402 /* When shaders are logged to stderr, asynchronous compilation is
403 * disabled too. */
404 if (sscreen->b.debug_flags & (DBG_VS | DBG_TCS | DBG_TES | DBG_GS |
405 DBG_PS | DBG_CS))
406 return ctx;
407
408 return threaded_context_create(ctx, &sscreen->b.pool_transfers,
409 r600_replace_buffer_storage,
410 &((struct si_context*)ctx)->b.tc);
411 }
412
413 /*
414 * pipe_screen
415 */
416 static bool si_have_tgsi_compute(struct si_screen *sscreen)
417 {
418 /* Old kernels disallowed some register writes for SI
419 * that are used for indirect dispatches. */
420 return (sscreen->b.chip_class >= CIK ||
421 sscreen->b.info.drm_major == 3 ||
422 (sscreen->b.info.drm_major == 2 &&
423 sscreen->b.info.drm_minor >= 45));
424 }
425
426 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
427 {
428 struct si_screen *sscreen = (struct si_screen *)pscreen;
429
430 switch (param) {
431 /* Supported features (boolean caps). */
432 case PIPE_CAP_ACCELERATED:
433 case PIPE_CAP_TWO_SIDED_STENCIL:
434 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
435 case PIPE_CAP_ANISOTROPIC_FILTER:
436 case PIPE_CAP_POINT_SPRITE:
437 case PIPE_CAP_OCCLUSION_QUERY:
438 case PIPE_CAP_TEXTURE_SHADOW_MAP:
439 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
440 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
441 case PIPE_CAP_TEXTURE_SWIZZLE:
442 case PIPE_CAP_DEPTH_CLIP_DISABLE:
443 case PIPE_CAP_SHADER_STENCIL_EXPORT:
444 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
445 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
446 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
447 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
448 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
449 case PIPE_CAP_SM3:
450 case PIPE_CAP_SEAMLESS_CUBE_MAP:
451 case PIPE_CAP_PRIMITIVE_RESTART:
452 case PIPE_CAP_CONDITIONAL_RENDER:
453 case PIPE_CAP_TEXTURE_BARRIER:
454 case PIPE_CAP_INDEP_BLEND_ENABLE:
455 case PIPE_CAP_INDEP_BLEND_FUNC:
456 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
457 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
458 case PIPE_CAP_USER_CONSTANT_BUFFERS:
459 case PIPE_CAP_START_INSTANCE:
460 case PIPE_CAP_NPOT_TEXTURES:
461 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
462 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
463 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
464 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
465 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
466 case PIPE_CAP_TGSI_INSTANCEID:
467 case PIPE_CAP_COMPUTE:
468 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
469 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
470 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
471 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
472 case PIPE_CAP_CUBE_MAP_ARRAY:
473 case PIPE_CAP_SAMPLE_SHADING:
474 case PIPE_CAP_DRAW_INDIRECT:
475 case PIPE_CAP_CLIP_HALFZ:
476 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
477 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
478 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
479 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
480 case PIPE_CAP_TGSI_TEXCOORD:
481 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
482 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
483 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
484 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
485 case PIPE_CAP_SHAREABLE_SHADERS:
486 case PIPE_CAP_DEPTH_BOUNDS_TEST:
487 case PIPE_CAP_SAMPLER_VIEW_TARGET:
488 case PIPE_CAP_TEXTURE_QUERY_LOD:
489 case PIPE_CAP_TEXTURE_GATHER_SM5:
490 case PIPE_CAP_TGSI_TXQS:
491 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
492 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
493 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
494 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
495 case PIPE_CAP_INVALIDATE_BUFFER:
496 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
497 case PIPE_CAP_QUERY_MEMORY_INFO:
498 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
499 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
500 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
501 case PIPE_CAP_GENERATE_MIPMAP:
502 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
503 case PIPE_CAP_STRING_MARKER:
504 case PIPE_CAP_CLEAR_TEXTURE:
505 case PIPE_CAP_CULL_DISTANCE:
506 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
507 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
508 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
509 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
510 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
511 case PIPE_CAP_DOUBLES:
512 case PIPE_CAP_TGSI_TEX_TXF_LZ:
513 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
514 case PIPE_CAP_BINDLESS_TEXTURE:
515 case PIPE_CAP_QUERY_TIMESTAMP:
516 case PIPE_CAP_QUERY_TIME_ELAPSED:
517 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
518 case PIPE_CAP_QUERY_SO_OVERFLOW:
519 return 1;
520
521 case PIPE_CAP_INT64:
522 case PIPE_CAP_INT64_DIVMOD:
523 case PIPE_CAP_TGSI_CLOCK:
524 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
525 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
526 return 1;
527
528 case PIPE_CAP_TGSI_VOTE:
529 return HAVE_LLVM >= 0x0400;
530
531 case PIPE_CAP_TGSI_BALLOT:
532 return HAVE_LLVM >= 0x0500;
533
534 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
535 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
536
537 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
538 return (sscreen->b.info.drm_major == 2 &&
539 sscreen->b.info.drm_minor >= 43) ||
540 sscreen->b.info.drm_major == 3;
541
542 case PIPE_CAP_TEXTURE_MULTISAMPLE:
543 /* 2D tiling on CIK is supported since DRM 2.35.0 */
544 return sscreen->b.chip_class < CIK ||
545 (sscreen->b.info.drm_major == 2 &&
546 sscreen->b.info.drm_minor >= 35) ||
547 sscreen->b.info.drm_major == 3;
548
549 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
550 return R600_MAP_BUFFER_ALIGNMENT;
551
552 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
553 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
554 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
555 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
556 case PIPE_CAP_MAX_VERTEX_STREAMS:
557 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
558 return 4;
559
560 case PIPE_CAP_GLSL_FEATURE_LEVEL:
561 if (sscreen->b.debug_flags & DBG_NIR)
562 return 140; /* no geometry and tessellation shaders yet */
563 if (si_have_tgsi_compute(sscreen))
564 return 450;
565 return 420;
566
567 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
568 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
569
570 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
571 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
572 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
573 /* SI doesn't support unaligned loads.
574 * CIK needs DRM 2.50.0 on radeon. */
575 return sscreen->b.chip_class == SI ||
576 (sscreen->b.info.drm_major == 2 &&
577 sscreen->b.info.drm_minor < 50);
578
579 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
580 /* TODO: GFX9 hangs. */
581 if (sscreen->b.chip_class >= GFX9)
582 return 0;
583 /* Disable on SI due to VM faults in CP DMA. Enable once these
584 * faults are mitigated in software.
585 */
586 if (sscreen->b.chip_class >= CIK &&
587 sscreen->b.info.drm_major == 3 &&
588 sscreen->b.info.drm_minor >= 13)
589 return RADEON_SPARSE_PAGE_SIZE;
590 return 0;
591
592 /* Unsupported features. */
593 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
594 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
595 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
596 case PIPE_CAP_USER_VERTEX_BUFFERS:
597 case PIPE_CAP_FAKE_SW_MSAA:
598 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
599 case PIPE_CAP_VERTEXID_NOBASE:
600 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
601 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
602 case PIPE_CAP_NATIVE_FENCE_FD:
603 case PIPE_CAP_TGSI_FS_FBFETCH:
604 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
605 case PIPE_CAP_UMA:
606 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
607 case PIPE_CAP_POST_DEPTH_COVERAGE:
608 case PIPE_CAP_MEMOBJ:
609 return 0;
610
611 case PIPE_CAP_QUERY_BUFFER_OBJECT:
612 return si_have_tgsi_compute(sscreen);
613
614 case PIPE_CAP_DRAW_PARAMETERS:
615 case PIPE_CAP_MULTI_DRAW_INDIRECT:
616 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
617 return sscreen->has_draw_indirect_multi;
618
619 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
620 return 30;
621
622 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
623 return sscreen->b.chip_class <= VI ?
624 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
625
626 /* Stream output. */
627 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
628 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
629 return 32*4;
630
631 /* Geometry shader output. */
632 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
633 return 1024;
634 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
635 return 4095;
636
637 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
638 return 2048;
639
640 /* Texturing. */
641 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
642 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
643 return 15; /* 16384 */
644 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
645 /* textures support 8192, but layered rendering supports 2048 */
646 return 12;
647 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
648 /* textures support 8192, but layered rendering supports 2048 */
649 return 2048;
650
651 /* Viewports and render targets. */
652 case PIPE_CAP_MAX_VIEWPORTS:
653 return R600_MAX_VIEWPORTS;
654 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
655 case PIPE_CAP_MAX_RENDER_TARGETS:
656 return 8;
657
658 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
659 case PIPE_CAP_MIN_TEXEL_OFFSET:
660 return -32;
661
662 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
663 case PIPE_CAP_MAX_TEXEL_OFFSET:
664 return 31;
665
666 case PIPE_CAP_ENDIANNESS:
667 return PIPE_ENDIAN_LITTLE;
668
669 case PIPE_CAP_VENDOR_ID:
670 return ATI_VENDOR_ID;
671 case PIPE_CAP_DEVICE_ID:
672 return sscreen->b.info.pci_id;
673 case PIPE_CAP_VIDEO_MEMORY:
674 return sscreen->b.info.vram_size >> 20;
675 case PIPE_CAP_PCI_GROUP:
676 return sscreen->b.info.pci_domain;
677 case PIPE_CAP_PCI_BUS:
678 return sscreen->b.info.pci_bus;
679 case PIPE_CAP_PCI_DEVICE:
680 return sscreen->b.info.pci_dev;
681 case PIPE_CAP_PCI_FUNCTION:
682 return sscreen->b.info.pci_func;
683 }
684 return 0;
685 }
686
687 static int si_get_shader_param(struct pipe_screen* pscreen,
688 enum pipe_shader_type shader,
689 enum pipe_shader_cap param)
690 {
691 struct si_screen *sscreen = (struct si_screen *)pscreen;
692
693 switch(shader)
694 {
695 case PIPE_SHADER_FRAGMENT:
696 case PIPE_SHADER_VERTEX:
697 case PIPE_SHADER_GEOMETRY:
698 case PIPE_SHADER_TESS_CTRL:
699 case PIPE_SHADER_TESS_EVAL:
700 break;
701 case PIPE_SHADER_COMPUTE:
702 switch (param) {
703 case PIPE_SHADER_CAP_PREFERRED_IR:
704 return PIPE_SHADER_IR_NATIVE;
705
706 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
707 int ir = 1 << PIPE_SHADER_IR_NATIVE;
708
709 if (si_have_tgsi_compute(sscreen))
710 ir |= 1 << PIPE_SHADER_IR_TGSI;
711
712 return ir;
713 }
714
715 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
716 uint64_t max_const_buffer_size;
717 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
718 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
719 &max_const_buffer_size);
720 return MIN2(max_const_buffer_size, INT_MAX);
721 }
722 default:
723 /* If compute shaders don't require a special value
724 * for this cap, we can return the same value we
725 * do for other shader types. */
726 break;
727 }
728 break;
729 default:
730 return 0;
731 }
732
733 switch (param) {
734 /* Shader limits. */
735 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
736 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
737 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
738 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
739 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
740 return 16384;
741 case PIPE_SHADER_CAP_MAX_INPUTS:
742 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
743 case PIPE_SHADER_CAP_MAX_OUTPUTS:
744 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
745 case PIPE_SHADER_CAP_MAX_TEMPS:
746 return 256; /* Max native temporaries. */
747 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
748 return 4096 * sizeof(float[4]); /* actually only memory limits this */
749 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
750 return SI_NUM_CONST_BUFFERS;
751 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
752 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
753 return SI_NUM_SAMPLERS;
754 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
755 return SI_NUM_SHADER_BUFFERS;
756 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
757 return SI_NUM_IMAGES;
758 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
759 return 32;
760 case PIPE_SHADER_CAP_PREFERRED_IR:
761 if (sscreen->b.debug_flags & DBG_NIR &&
762 (shader == PIPE_SHADER_VERTEX ||
763 shader == PIPE_SHADER_FRAGMENT))
764 return PIPE_SHADER_IR_NIR;
765 return PIPE_SHADER_IR_TGSI;
766 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
767 return 3;
768
769 /* Supported boolean features. */
770 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
771 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
772 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
773 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
774 case PIPE_SHADER_CAP_INTEGERS:
775 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
776 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
777 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
778 return 1;
779
780 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
781 /* TODO: Indirect indexing of GS inputs is unimplemented. */
782 return shader != PIPE_SHADER_GEOMETRY &&
783 (sscreen->llvm_has_working_vgpr_indexing ||
784 /* TCS and TES load inputs directly from LDS or
785 * offchip memory, so indirect indexing is trivial. */
786 shader == PIPE_SHADER_TESS_CTRL ||
787 shader == PIPE_SHADER_TESS_EVAL);
788
789 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
790 return sscreen->llvm_has_working_vgpr_indexing ||
791 /* TCS stores outputs directly to memory. */
792 shader == PIPE_SHADER_TESS_CTRL;
793
794 /* Unsupported boolean features. */
795 case PIPE_SHADER_CAP_SUBROUTINES:
796 case PIPE_SHADER_CAP_SUPPORTED_IRS:
797 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
798 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
799 return 0;
800 }
801 return 0;
802 }
803
804 static const struct nir_shader_compiler_options nir_options = {
805 .vertex_id_zero_based = true,
806 .lower_scmp = true,
807 .lower_flrp32 = true,
808 .lower_fsat = true,
809 .lower_fdiv = true,
810 .lower_sub = true,
811 .lower_pack_snorm_2x16 = true,
812 .lower_pack_snorm_4x8 = true,
813 .lower_pack_unorm_2x16 = true,
814 .lower_pack_unorm_4x8 = true,
815 .lower_unpack_snorm_2x16 = true,
816 .lower_unpack_snorm_4x8 = true,
817 .lower_unpack_unorm_2x16 = true,
818 .lower_unpack_unorm_4x8 = true,
819 .lower_extract_byte = true,
820 .lower_extract_word = true,
821 .max_unroll_iterations = 32,
822 .native_integers = true,
823 };
824
825 static const void *
826 si_get_compiler_options(struct pipe_screen *screen,
827 enum pipe_shader_ir ir,
828 enum pipe_shader_type shader)
829 {
830 assert(ir == PIPE_SHADER_IR_NIR);
831 return &nir_options;
832 }
833
834 static void si_destroy_screen(struct pipe_screen* pscreen)
835 {
836 struct si_screen *sscreen = (struct si_screen *)pscreen;
837 struct si_shader_part *parts[] = {
838 sscreen->vs_prologs,
839 sscreen->tcs_epilogs,
840 sscreen->gs_prologs,
841 sscreen->ps_prologs,
842 sscreen->ps_epilogs
843 };
844 unsigned i;
845
846 if (!sscreen->b.ws->unref(sscreen->b.ws))
847 return;
848
849 util_queue_destroy(&sscreen->shader_compiler_queue);
850 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
851
852 for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
853 if (sscreen->tm[i])
854 LLVMDisposeTargetMachine(sscreen->tm[i]);
855
856 for (i = 0; i < ARRAY_SIZE(sscreen->tm_low_priority); i++)
857 if (sscreen->tm_low_priority[i])
858 LLVMDisposeTargetMachine(sscreen->tm_low_priority[i]);
859
860 /* Free shader parts. */
861 for (i = 0; i < ARRAY_SIZE(parts); i++) {
862 while (parts[i]) {
863 struct si_shader_part *part = parts[i];
864
865 parts[i] = part->next;
866 radeon_shader_binary_clean(&part->binary);
867 FREE(part);
868 }
869 }
870 mtx_destroy(&sscreen->shader_parts_mutex);
871 si_destroy_shader_cache(sscreen);
872 r600_destroy_common_screen(&sscreen->b);
873 }
874
875 static bool si_init_gs_info(struct si_screen *sscreen)
876 {
877 switch (sscreen->b.family) {
878 case CHIP_OLAND:
879 case CHIP_HAINAN:
880 case CHIP_KAVERI:
881 case CHIP_KABINI:
882 case CHIP_MULLINS:
883 case CHIP_ICELAND:
884 case CHIP_CARRIZO:
885 case CHIP_STONEY:
886 sscreen->gs_table_depth = 16;
887 return true;
888 case CHIP_TAHITI:
889 case CHIP_PITCAIRN:
890 case CHIP_VERDE:
891 case CHIP_BONAIRE:
892 case CHIP_HAWAII:
893 case CHIP_TONGA:
894 case CHIP_FIJI:
895 case CHIP_POLARIS10:
896 case CHIP_POLARIS11:
897 case CHIP_POLARIS12:
898 case CHIP_VEGA10:
899 case CHIP_RAVEN:
900 sscreen->gs_table_depth = 32;
901 return true;
902 default:
903 return false;
904 }
905 }
906
907 static void si_handle_env_var_force_family(struct si_screen *sscreen)
908 {
909 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
910 unsigned i;
911
912 if (!family)
913 return;
914
915 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
916 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
917 /* Override family and chip_class. */
918 sscreen->b.family = sscreen->b.info.family = i;
919
920 if (i >= CHIP_VEGA10)
921 sscreen->b.chip_class = sscreen->b.info.chip_class = GFX9;
922 else if (i >= CHIP_TONGA)
923 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
924 else if (i >= CHIP_BONAIRE)
925 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
926 else
927 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
928
929 /* Don't submit any IBs. */
930 setenv("RADEON_NOOP", "1", 1);
931 return;
932 }
933 }
934
935 fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
936 exit(1);
937 }
938
939 static void si_test_vmfault(struct si_screen *sscreen)
940 {
941 struct pipe_context *ctx = sscreen->b.aux_context;
942 struct si_context *sctx = (struct si_context *)ctx;
943 struct pipe_resource *buf =
944 pipe_buffer_create(&sscreen->b.b, 0, PIPE_USAGE_DEFAULT, 64);
945
946 if (!buf) {
947 puts("Buffer allocation failed.");
948 exit(1);
949 }
950
951 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
952
953 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_CP) {
954 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
955 ctx->flush(ctx, NULL, 0);
956 puts("VM fault test: CP - done.");
957 }
958 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SDMA) {
959 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
960 ctx->flush(ctx, NULL, 0);
961 puts("VM fault test: SDMA - done.");
962 }
963 if (sscreen->b.debug_flags & DBG_TEST_VMFAULT_SHADER) {
964 util_test_constant_buffer(ctx, buf);
965 puts("VM fault test: Shader - done.");
966 }
967 exit(0);
968 }
969
970 static void radeonsi_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
971 {
972 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
973 }
974
975 static void radeonsi_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
976 {
977 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
978
979 ac_compute_device_uuid(&rscreen->info, uuid, PIPE_UUID_SIZE);
980 }
981
982 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
983 const struct pipe_screen_config *config)
984 {
985 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
986 unsigned num_threads, num_compiler_threads, num_compiler_threads_lowprio, i;
987
988 if (!sscreen) {
989 return NULL;
990 }
991
992 /* Set functions first. */
993 sscreen->b.b.context_create = si_pipe_create_context;
994 sscreen->b.b.destroy = si_destroy_screen;
995 sscreen->b.b.get_param = si_get_param;
996 sscreen->b.b.get_shader_param = si_get_shader_param;
997 sscreen->b.b.get_compiler_options = si_get_compiler_options;
998 sscreen->b.b.get_device_uuid = radeonsi_get_device_uuid;
999 sscreen->b.b.get_driver_uuid = radeonsi_get_driver_uuid;
1000 sscreen->b.b.resource_create = r600_resource_create_common;
1001
1002 si_init_screen_state_functions(sscreen);
1003
1004 /* Set these flags in debug_flags early, so that the shader cache takes
1005 * them into account.
1006 */
1007 if (driQueryOptionb(config->options,
1008 "glsl_correct_derivatives_after_discard"))
1009 sscreen->b.debug_flags |= DBG_FS_CORRECT_DERIVS_AFTER_KILL;
1010 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1011 sscreen->b.debug_flags |= DBG_SI_SCHED;
1012
1013 if (!r600_common_screen_init(&sscreen->b, ws) ||
1014 !si_init_gs_info(sscreen) ||
1015 !si_init_shader_cache(sscreen)) {
1016 FREE(sscreen);
1017 return NULL;
1018 }
1019
1020 /* Only enable as many threads as we have target machines, but at most
1021 * the number of CPUs - 1 if there is more than one.
1022 */
1023 num_threads = sysconf(_SC_NPROCESSORS_ONLN);
1024 num_threads = MAX2(1, num_threads - 1);
1025 num_compiler_threads = MIN2(num_threads, ARRAY_SIZE(sscreen->tm));
1026 num_compiler_threads_lowprio =
1027 MIN2(num_threads, ARRAY_SIZE(sscreen->tm_low_priority));
1028
1029 if (!util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
1030 32, num_compiler_threads,
1031 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
1032 si_destroy_shader_cache(sscreen);
1033 FREE(sscreen);
1034 return NULL;
1035 }
1036
1037 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1038 "si_shader_low",
1039 32, num_compiler_threads_lowprio,
1040 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1041 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1042 si_destroy_shader_cache(sscreen);
1043 FREE(sscreen);
1044 return NULL;
1045 }
1046
1047 si_handle_env_var_force_family(sscreen);
1048
1049 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1050 si_init_perfcounters(sscreen);
1051
1052 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1053 * around by setting 4K granularity.
1054 */
1055 sscreen->tess_offchip_block_dw_size =
1056 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
1057
1058 sscreen->has_distributed_tess =
1059 sscreen->b.chip_class >= VI &&
1060 sscreen->b.info.max_se >= 2;
1061
1062 sscreen->has_draw_indirect_multi =
1063 (sscreen->b.family >= CHIP_POLARIS10) ||
1064 (sscreen->b.chip_class == VI &&
1065 sscreen->b.info.pfp_fw_version >= 121 &&
1066 sscreen->b.info.me_fw_version >= 87) ||
1067 (sscreen->b.chip_class == CIK &&
1068 sscreen->b.info.pfp_fw_version >= 211 &&
1069 sscreen->b.info.me_fw_version >= 173) ||
1070 (sscreen->b.chip_class == SI &&
1071 sscreen->b.info.pfp_fw_version >= 79 &&
1072 sscreen->b.info.me_fw_version >= 142);
1073
1074 sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
1075 sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
1076 sscreen->b.family <= CHIP_POLARIS12) ||
1077 sscreen->b.family == CHIP_VEGA10 ||
1078 sscreen->b.family == CHIP_RAVEN;
1079 /* While it would be nice not to have this flag, we are constrained
1080 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1081 * on GFX9.
1082 */
1083 sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI;
1084
1085 sscreen->b.has_cp_dma = true;
1086 sscreen->b.has_streamout = true;
1087
1088 /* Some chips have RB+ registers, but don't support RB+. Those must
1089 * always disable it.
1090 */
1091 if (sscreen->b.family == CHIP_STONEY ||
1092 sscreen->b.chip_class >= GFX9) {
1093 sscreen->b.has_rbplus = true;
1094
1095 sscreen->b.rbplus_allowed =
1096 !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
1097 (sscreen->b.family == CHIP_STONEY ||
1098 sscreen->b.family == CHIP_RAVEN);
1099 }
1100
1101 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1102 sscreen->use_monolithic_shaders =
1103 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
1104
1105 sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1106 SI_CONTEXT_INV_VMEM_L1;
1107 if (sscreen->b.chip_class <= VI)
1108 sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1109
1110 sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
1111
1112 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1113 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
1114
1115 for (i = 0; i < num_compiler_threads; i++)
1116 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
1117 for (i = 0; i < num_compiler_threads_lowprio; i++)
1118 sscreen->tm_low_priority[i] = si_create_llvm_target_machine(sscreen);
1119
1120 /* Create the auxiliary context. This must be done last. */
1121 sscreen->b.aux_context = si_create_context(&sscreen->b.b, 0);
1122
1123 if (sscreen->b.debug_flags & DBG_TEST_DMA)
1124 r600_test_dma(&sscreen->b);
1125
1126 if (sscreen->b.debug_flags & (DBG_TEST_VMFAULT_CP |
1127 DBG_TEST_VMFAULT_SDMA |
1128 DBG_TEST_VMFAULT_SHADER))
1129 si_test_vmfault(sscreen);
1130
1131 return &sscreen->b.b;
1132 }